S32k310 RTDs port on TCM memories Hi There, I would run some deterministic Functions on TCM, and by consecuence some RTDs (ADC, PWM,...). I noticed, in *Memmap.h files,  that mcal_* linker sections  are spread in few linker sections; for example some sections are cacheable other non  canheable and other unknown sections. I read the RTD IM and UM manuals but there is no info about TCM topic Is there some documentation to port RTDs memory section on I/D TCMs ? NB Also, in s321k310 there is 16kb of SRAM and 64k od DTCM, so an efficient  and accurate partiting of data memory  mapping is almost necessary in any case. Best Regards Fabio  Best Regards Fabio Re: S32k310 RTDs port on TCM memories Hi@FabioG Please refer to the attachment.

I2C MPC5478G こんにちは、MPC5748Gを使ってアンプと通信したいです。パワー・アーキテクチャーのi2c_transfer_mpc5748gのサンプルコードを使っています。アンプのアドレスは0x70です。これを実現するにはどのような変更が必要ですか？また、 i2Cドライバーはアドレス-> データを送信しますが、私はそれをアンプ（アドレス）-> アンプレジスタ（サブアドレス）-> データのアドレスにしたいです。

i.MXRT1176 SAI1 Data channels 2,3,4 & fifo combine Hi there.  I'm trying to use as many SAI data pins as possible on the RT1176.  I am aware that for SAI 1 data channels 2, 3, and 4, the Tx and Rx data lines share a pin, and so can only be assigned to Tx or Rx. Lets try and use all 3 of them all for Tx anyway.. So my configuration is  SAI 1 pins: - Tx1 - Rx1 - Tx2 - Tx3 - Tx4 Using the config tool, I do this on the 'playback' tab Then I generate the code and run, but I hit an assert in fsl_sai_edma.c: #if defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE /* Allow multi-channel transfer only if FIFO Combine mode is enabled */ assert( (saiConfig->channelNums <= 1U) || ((saiConfig->channelNums > 1U) && ((saiConfig->fifo.fifoCombine == kSAI_FifoCombineModeEnabledOnWrite) || (saiConfig->fifo.fifoCombine == kSAI_FifoCombineModeEnabledOnReadWrite)))); #endif   This suggests that you MUST use fifo combine if you use more than 1 SAI data channel. The manual states (p.3475): Combining FIFOs for transmit data channels allows one data channel to use the FIFOs of all enabled channel FIFOs, with identical data output on each enabled data channel. Combining FIFOs for receive data channels allows one data channel to use the FIFOs of all enabled channel FIFOs, with received data from channel 0 stored into each enabled data channel. This suggest that if using SAI 1 data pin2, 3, or 4 for Tx, they will all just output the same data as on pin1?! And if using them for Rx... well it doesn't say but it sounds like pins 2,3 and 4 will be ignored? Can you please clarify this or point me to some more detailed documentation?  Are SAI1 data pins 2,3,4 independently usable at all?   Many thanks. Re: i.MXRT1176 SAI1 Data channels 2,3,4 & fifo combine Thanks for the reply, I tested this today and it appears to work as described. It would be really useful to have this functionality detailed in the SAI FIFO combine section of the RT1176 ref manual because it currently reads as though it is not possible to have different data on different SAI 1 pins. Many thanks Re: i.MXRT1176 SAI1 Data channels 2,3,4 & fifo combine Hello @mttjcksn, I highly recommend consulting this application note, where the multi-channel functionality is explained in greater detail. Additionally, the FCOMB register indicates the following: This means that the FIFO will store data for each enabled channel. Also, if you exprience any issue, do not hesitate to let me know. BR Habib

LSDK21.08 LS1043AQDS SETUP Hello, Wang. With your help, my board ls1043aqds has entered uboot. I use LSDK 21.08 for development, and the boot mode is TF-A. But my qspi flash is small, only 16MB, so I can't write itb directly to flash and start kernel and ramdisk from qspi. I think the next priority is to burn the kernel and ramdisk into 16GB emmc, and then load the kernel from emmc. But I don't know if I have to use an external writer to burn emmc at the moment, and I don't know exactly what needs to be modified and compiled in the next work. I really hope to get your help and look forward to your reply as soon as possible. thank you. @yipingwang Re: LSDK21.08 LS1043AQDS SETUP Dear WANG,Thank you very much for your help, I can now enter the official ubuntu file system. Re: LSDK21.08 LS1043AQDS SETUP You need to modify LS1043AQDS device tree according to your custom board. In LSDK 21.08 build environment: $ source setup.env $ flex-builder -c linux -m ls1043aqds Go to Linux Kernel source code components/linux/linux, please modify arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts according to your custom board. For example, please delete the following device node, if there is no IFC NOR flash on your custom board. nor@0,0 { compatible = "cfi-flash"; reg = <0x0 0x0 0x8000000>; big-endian; bank-width = <2>; device-width = <1>; }; Then rebuild Linux Kernel $ flex-builder -c linux -m ls1043aqds Regenerate itb image $ flex-builder -i mkitb -r yocto:tiny Get the image flexbuild_lsdk2108_github/build/images/lsdk2108_yocto_tiny_LS_arm64.itb If you need to the bootpartition image, please regenerate it with the following command $ flex-builder -i mkbootpartition -a arm64 Re: LSDK21.08 LS1043AQDS SETUP Wang,Thank you very much for your technical reply, and I am honored to get your help in debugging this series of boards for the first time. I have made some progress following your suggestions, but it seems that the kernel is stuck and cannot continue. I have attached the log, and I hope to get your help on what I should do next so that I can successfully enter ramdisk. @yipingwang  Re: LSDK21.08 LS1043AQDS SETUP The emmc device is not removable, you could copy all your images to the USB device, then boot up the target board with image lsdk2108_yocto_tiny_LS_arm64.itb and deploy Ubuntu rootfs to emmc device in Linux on the target board. For example under u-boot, => ext2load usb 0:1 0xa0000000 lsdk2108_yocto_tiny_LS_arm64.itb => bootm 0xa0000000#ls1043aqds Under Linux on the target board, please run the following commands to deploy Kernel and Ubuntu rootfs to emmc device. $ flex-installer -i pf -d /dev/mmcblk0 $ flex-installer -b boot_LS_arm64_lts_5.10.tgz -r rootfs_lsdk2108_ubuntu_main_arm64.tgz -d /dev/mmcblk0 Note:/dev/mmcblk0 is the emmc device name on the target board.

How qemu load dtb on LS2088ardb I'm buiding images for LS2088ardb by using Yocto command "bitbake fsl-image-networking" Now I load the dtb in the QEMU but can't boot into kernel and step by step SOP as below:  Open 2 terminals in my host PC (Ubuntu 20.04)  Use the command to run QEMU in first terminal: $ qemu-system-aarch64 \   -smp 8 \   -machine type=virt,gic-version=3 \   -m 2048 \   -cpu cortex-a72 \   -kernel Image \   -serial tcp::4446,server,telnet \   -drive if=none,file=fsl-image-networking-ls2088ardb.rootfs-20240711074828.ext4,id=foo,format=raw \   -device virtio-blk-device,drive=foo \   -append 'root=/dev/vda rw console=ttyAMA0,115200 rootwait earlyprintk' \   -monitor stdio Output as below QEMU 4.2.1 monitor - type 'help' for more information (qemu) qemu-system-aarch64: -serial tcp::4446,server,telnet: info: QEMU waiting for connection on: disconnected:telnet:0.0.0.0:4446,server Use the command to connect QEMU in second terminal: telnet 0.0.0.0 4446 I can success to boot into kernel Trying 0.0.0.0... Connected to 0.0.0.0. Escape character is '^]'. [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd083] [ 0.000000] Linux version 6.6.23-gb586a521770e (oe-user@oe-host) (aarch64-fsl-linux-gcc (GCC) 13.2.0, GNU ld (GNU Binutils) 2.42.0.20240216) #1 SMP PREEMPT Fri Jun 7 13:15:57 UTC 2024 [ 0.000000] KASLR disabled due to lack of seed [ 0.000000] Machine model: linux,dummy-virt ... ... ls2088ardb login: root root@ls2088ardb:~# Trying to use the command to load device tree in first terminal $ qemu-system-aarch64 \ -smp 8 \ -machine type=virt,gic-version=3 \ -m 2048 \ -cpu cortex-a72 \ -kernel Image \ -serial tcp::4446,server,telnet \ -dtb fsl-ls2088a-rdb.dtb \ -drive if=none,file=fsl-image-networking-ls2088ardb.rootfs-20240711074828.ext4,id=foo,format=raw \ -device virtio-blk-device,drive=foo \ -append 'root=/dev/vda rw console=ttyAMA0,115200 rootwait earlyprintk' \ -monitor stdio Output as below QEMU 4.2.1 monitor - type 'help' for more information (qemu) qemu-system-aarch64: -serial tcp::4446,server,telnet: info: QEMU waiting for connection on: disconnected:telnet:0.0.0.0:4446,server Use the command to connect QEMU in second terminal Trying 0.0.0.0... Connected to 0.0.0.0. Escape character is '^]'. It stay here and can't boot into kernel I try to add debug info and step same as Step4-5 -d int,cpu_reset Output  CPU Reset (CPU 0) R00=00000000 R01=00000000 R02=00000000 R03=00000000 R04=00000000 R05=00000000 R06=00000000 R07=00000000 R08=00000000 R09=00000000 R10=00000000 R11=00000000 R12=00000000 R13=00000000 R14=00000000 R15=00000000 PSR=40000000 -Z-- A usr26 CPU Reset (CPU 1) R00=00000000 R01=00000000 R02=00000000 R03=00000000 R04=00000000 R05=00000000 R06=00000000 R07=00000000 R08=00000000 R09=00000000 R10=00000000 R11=00000000 R12=00000000 R13=00000000 R14=00000000 R15=00000000 PSR=40000000 -Z-- A usr26 CPU Reset (CPU 2) R00=00000000 R01=00000000 R02=00000000 R03=00000000 R04=00000000 R05=00000000 R06=00000000 R07=00000000 R08=00000000 R09=00000000 R10=00000000 R11=00000000 R12=00000000 R13=00000000 R14=00000000 R15=00000000 PSR=40000000 -Z-- A usr26 CPU Reset (CPU 3) R00=00000000 R01=00000000 R02=00000000 R03=00000000 R04=00000000 R05=00000000 R06=00000000 R07=00000000 R08=00000000 R09=00000000 R10=00000000 R11=00000000 R12=00000000 R13=00000000 R14=00000000 R15=00000000 PSR=40000000 -Z-- A usr26 CPU Reset (CPU 4) R00=00000000 R01=00000000 R02=00000000 R03=00000000 R04=00000000 R05=00000000 R06=00000000 R07=00000000 R08=00000000 R09=00000000 R10=00000000 R11=00000000 R12=00000000 R13=00000000 R14=00000000 R15=00000000 PSR=40000000 -Z-- A usr26 CPU Reset (CPU 5) R00=00000000 R01=00000000 R02=00000000 R03=00000000 R04=00000000 R05=00000000 R06=00000000 R07=00000000 R08=00000000 R09=00000000 R10=00000000 R11=00000000 R12=00000000 R13=00000000 R14=00000000 R15=00000000 PSR=40000000 -Z-- A usr26 CPU Reset (CPU 6) R00=00000000 R01=00000000 R02=00000000 R03=00000000 R04=00000000 R05=00000000 R06=00000000 R07=00000000 R08=00000000 R09=00000000 R10=00000000 R11=00000000 R12=00000000 R13=00000000 R14=00000000 R15=00000000 PSR=40000000 -Z-- A usr26 CPU Reset (CPU 7) R00=00000000 R01=00000000 R02=00000000 R03=00000000 R04=00000000 R05=00000000 R06=00000000 R07=00000000 R08=00000000 R09=00000000 R10=00000000 R11=00000000 R12=00000000 R13=00000000 R14=00000000 R15=00000000 PSR=40000000 -Z-- A usr26 CPU Reset (CPU 0) PC=0000000000000000 X00=0000000000000000 X01=0000000000000000 X02=0000000000000000 X03=0000000000000000 X04=0000000000000000 X05=0000000000000000 X06=0000000000000000 X07=0000000000000000 X08=0000000000000000 X09=0000000000000000 X10=0000000000000000 X11=0000000000000000 X12=0000000000000000 X13=0000000000000000 X14=0000000000000000 X15=0000000000000000 X16=0000000000000000 X17=0000000000000000 X18=0000000000000000 X19=0000000000000000 X20=0000000000000000 X21=0000000000000000 X22=0000000000000000 X23=0000000000000000 X24=0000000000000000 X25=0000000000000000 X26=0000000000000000 X27=0000000000000000 X28=0000000000000000 X29=0000000000000000 X30=0000000000000000 SP=0000000000000000 PSTATE=400003c5 -Z-- EL1h CPU Reset (CPU 1) PC=0000000000000000 X00=0000000000000000 X01=0000000000000000 X02=0000000000000000 X03=0000000000000000 X04=0000000000000000 X05=0000000000000000 X06=0000000000000000 X07=0000000000000000 X08=0000000000000000 X09=0000000000000000 X10=0000000000000000 X11=0000000000000000 X12=0000000000000000 X13=0000000000000000 X14=0000000000000000 X15=0000000000000000 X16=0000000000000000 X17=0000000000000000 X18=0000000000000000 X19=0000000000000000 X20=0000000000000000 X21=0000000000000000 X22=0000000000000000 X23=0000000000000000 X24=0000000000000000 X25=0000000000000000 X26=0000000000000000 X27=0000000000000000 X28=0000000000000000 X29=0000000000000000 X30=0000000000000000 SP=0000000000000000 PSTATE=400003c5 -Z-- EL1h CPU Reset (CPU 2) PC=0000000000000000 X00=0000000000000000 X01=0000000000000000 X02=0000000000000000 X03=0000000000000000 X04=0000000000000000 X05=0000000000000000 X06=0000000000000000 X07=0000000000000000 X08=0000000000000000 X09=0000000000000000 X10=0000000000000000 X11=0000000000000000 X12=0000000000000000 X13=0000000000000000 X14=0000000000000000 X15=0000000000000000 X16=0000000000000000 X17=0000000000000000 X18=0000000000000000 X19=0000000000000000 X20=0000000000000000 X21=0000000000000000 X22=0000000000000000 X23=0000000000000000 X24=0000000000000000 X25=0000000000000000 X26=0000000000000000 X27=0000000000000000 X28=0000000000000000 X29=0000000000000000 X30=0000000000000000 SP=0000000000000000 PSTATE=400003c5 -Z-- EL1h CPU Reset (CPU 3) PC=0000000000000000 X00=0000000000000000 X01=0000000000000000 X02=0000000000000000 X03=0000000000000000 X04=0000000000000000 X05=0000000000000000 X06=0000000000000000 X07=0000000000000000 X08=0000000000000000 X09=0000000000000000 X10=0000000000000000 X11=0000000000000000 X12=0000000000000000 X13=0000000000000000 X14=0000000000000000 X15=0000000000000000 X16=0000000000000000 X17=0000000000000000 X18=0000000000000000 X19=0000000000000000 X20=0000000000000000 X21=0000000000000000 X22=0000000000000000 X23=0000000000000000 X24=0000000000000000 X25=0000000000000000 X26=0000000000000000 X27=0000000000000000 X28=0000000000000000 X29=0000000000000000 X30=0000000000000000 SP=0000000000000000 PSTATE=400003c5 -Z-- EL1h CPU Reset (CPU 4) PC=0000000000000000 X00=0000000000000000 X01=0000000000000000 X02=0000000000000000 X03=0000000000000000 X04=0000000000000000 X05=0000000000000000 X06=0000000000000000 X07=0000000000000000 X08=0000000000000000 X09=0000000000000000 X10=0000000000000000 X11=0000000000000000 X12=0000000000000000 X13=0000000000000000 X14=0000000000000000 X15=0000000000000000 X16=0000000000000000 X17=0000000000000000 X18=0000000000000000 X19=0000000000000000 X20=0000000000000000 X21=0000000000000000 X22=0000000000000000 X23=0000000000000000 X24=0000000000000000 X25=0000000000000000 X26=0000000000000000 X27=0000000000000000 X28=0000000000000000 X29=0000000000000000 X30=0000000000000000 SP=0000000000000000 PSTATE=400003c5 -Z-- EL1h CPU Reset (CPU 5) PC=0000000000000000 X00=0000000000000000 X01=0000000000000000 X02=0000000000000000 X03=0000000000000000 X04=0000000000000000 X05=0000000000000000 X06=0000000000000000 X07=0000000000000000 X08=0000000000000000 X09=0000000000000000 X10=0000000000000000 X11=0000000000000000 X12=0000000000000000 X13=0000000000000000 X14=0000000000000000 X15=0000000000000000 X16=0000000000000000 X17=0000000000000000 X18=0000000000000000 X19=0000000000000000 X20=0000000000000000 X21=0000000000000000 X22=0000000000000000 X23=0000000000000000 X24=0000000000000000 X25=0000000000000000 X26=0000000000000000 X27=0000000000000000 X28=0000000000000000 X29=0000000000000000 X30=0000000000000000 SP=0000000000000000 PSTATE=400003c5 -Z-- EL1h CPU Reset (CPU 6) PC=0000000000000000 X00=0000000000000000 X01=0000000000000000 X02=0000000000000000 X03=0000000000000000 X04=0000000000000000 X05=0000000000000000 X06=0000000000000000 X07=0000000000000000 X08=0000000000000000 X09=0000000000000000 X10=0000000000000000 X11=0000000000000000 X12=0000000000000000 X13=0000000000000000 X14=0000000000000000 X15=0000000000000000 X16=0000000000000000 X17=0000000000000000 X18=0000000000000000 X19=0000000000000000 X20=0000000000000000 X21=0000000000000000 X22=0000000000000000 X23=0000000000000000 X24=0000000000000000 X25=0000000000000000 X26=0000000000000000 X27=0000000000000000 X28=0000000000000000 X29=0000000000000000 X30=0000000000000000 SP=0000000000000000 PSTATE=400003c5 -Z-- EL1h CPU Reset (CPU 7) PC=0000000000000000 X00=0000000000000000 X01=0000000000000000 X02=0000000000000000 X03=0000000000000000 X04=0000000000000000 X05=0000000000000000 X06=0000000000000000 X07=0000000000000000 X08=0000000000000000 X09=0000000000000000 X10=0000000000000000 X11=0000000000000000 X12=0000000000000000 X13=0000000000000000 X14=0000000000000000 X15=0000000000000000 X16=0000000000000000 X17=0000000000000000 X18=0000000000000000 X19=0000000000000000 X20=0000000000000000 X21=0000000000000000 X22=0000000000000000 X23=0000000000000000 X24=0000000000000000 X25=0000000000000000 X26=0000000000000000 X27=0000000000000000 X28=0000000000000000 X29=0000000000000000 X30=0000000000000000 SP=0000000000000000 PSTATE=400003c5 -Z-- EL1h Exception return from AArch64 EL1 to AArch64 EL1 PC 0x423790d0 Taking exception 1 [Undefined Instruction] ...from EL1 to EL1 ...with ESR 0x0/0x2000000 ...with ELR 0xffff800080027b20 ...to EL1 PC 0xffff800080011200 PSTATE 0x3c5 Here is my build image folder boot_ls2088ardb_lts_6.6.tgz core-image-minimal-ls2088ardb.rootfs-20240711074828.cpio.gz core-image-minimal-ls2088ardb.rootfs-20240711074828.cpio.gz.u-boot core-image-minimal-ls2088ardb.rootfs-20240711074828.manifest core-image-minimal-ls2088ardb.rootfs-20240711074828.spdx.tar.zst core-image-minimal-ls2088ardb.rootfs-20240711074828.tar.gz core-image-minimal-ls2088ardb.rootfs-20240711074828.testdata.json core-image-minimal-ls2088ardb.rootfs.cpio.gz->core-image-minimal-ls2088ardb.rootfs-20240711074828.cpio.gz core-image-minimal-ls2088ardb.rootfs.cpio.gz.u-boot->core-image-minimal-ls2088ardb.rootfs-20240711074828.cpio.gz.u-boot core-image-minimal-ls2088ardb.rootfs.manifest->core-image-minimal-ls2088ardb.rootfs-20240711074828.manifest core-image-minimal-ls2088ardb.rootfs.spdx.tar.zst->core-image-minimal-ls2088ardb.rootfs-20240711074828.spdx.tar.zst core-image-minimal-ls2088ardb.rootfs.tar.gz->core-image-minimal-ls2088ardb.rootfs-20240711074828.tar.gz core-image-minimal-ls2088ardb.rootfs.testdata.json->core-image-minimal-ls2088ardb.rootfs-20240711074828.testdata.json fitImage->fitImage--6.6.23+git0+b586a52177-r0-ls2088ardb-20240711074828.bin fitImage--6.6.23+git0+b586a52177-r0-ls2088ardb-20240711074828.bin fitImage-core-image-minimal-ls2088ardb.rootfs--6.6.23+git0+b586a52177-r0-ls2088ardb-20240711074828.bin fitImage-core-image-minimal-ls2088ardb.rootfs-ls2088ardb->fitImage-core-image-minimal-ls2088ardb.rootfs--6.6.23+git0+b586a52177-r0-ls2088ardb-20240711074828.bin fitImage-its--6.6.23+git0+b586a52177-r0-ls2088ardb-20240711074828.its fitImage-its-core-image-minimal-ls2088ardb.rootfs--6.6.23+git0+b586a52177-r0-ls2088ardb-20240711074828.its fitImage-its-core-image-minimal-ls2088ardb.rootfs-ls2088ardb->fitImage-its-core-image-minimal-ls2088ardb.rootfs--6.6.23+git0+b586a52177-r0-ls2088ardb-20240711074828.its fitImage-its-ls2088ardb->fitImage-its--6.6.23+git0+b586a52177-r0-ls2088ardb-20240711074828.its fitImage-linux.bin--6.6.23+git0+b586a52177-r0-ls2088ardb-20240711074828.bin fitImage-linux.bin-ls2088ardb->fitImage-linux.bin--6.6.23+git0+b586a52177-r0-ls2088ardb-20240711074828.bin fitImage-ls2088ardb.bin->fitImage--6.6.23+git0+b586a52177-r0-ls2088ardb-20240711074828.bin fsl-image-networking-ls2088ardb.rootfs-20240711074828.cpio.gz fsl-image-networking-ls2088ardb.rootfs-20240711074828.cpio.gz.u-boot fsl-image-networking-ls2088ardb.rootfs-20240711074828.ext4 fsl-image-networking-ls2088ardb.rootfs-20240711074828.manifest fsl-image-networking-ls2088ardb.rootfs-20240711074828.spdx.tar.zst fsl-image-networking-ls2088ardb.rootfs-20240711074828.tar.gz fsl-image-networking-ls2088ardb.rootfs-20240711074828.testdata.json fsl-image-networking-ls2088ardb.rootfs.cpio.gz->fsl-image-networking-ls2088ardb.rootfs-20240711074828.cpio.gz fsl-image-networking-ls2088ardb.rootfs.cpio.gz.u-boot->fsl-image-networking-ls2088ardb.rootfs-20240711074828.cpio.gz.u-boot fsl-image-networking-ls2088ardb.rootfs.ext4->fsl-image-networking-ls2088ardb.rootfs-20240711074828.ext4 fsl-image-networking-ls2088ardb.rootfs.manifest->fsl-image-networking-ls2088ardb.rootfs-20240711074828.manifest fsl-image-networking-ls2088ardb.rootfs.spdx.tar.zst->fsl-image-networking-ls2088ardb.rootfs-20240711074828.spdx.tar.zst fsl-image-networking-ls2088ardb.rootfs.tar.gz->fsl-image-networking-ls2088ardb.rootfs-20240711074828.tar.gz fsl-image-networking-ls2088ardb.rootfs.testdata.json->fsl-image-networking-ls2088ardb.rootfs-20240711074828.testdata.json fsl-ls2088a-qds--6.6.23+git0+b586a52177-r0-ls2088ardb-20240711074828.dtb->fsl-ls2088a-qds.dtb fsl-ls2088a-qds.dtb fsl-ls2088a-qds-ls2088ardb.dtb->fsl-ls2088a-qds.dtb fsl-ls2088a-rdb--6.6.23+git0+b586a52177-r0-ls2088ardb-20240711074828.dtb->fsl-ls2088a-rdb.dtb fsl-ls2088a-rdb.dtb fsl-ls2088a-rdb-ls2088ardb.dtb->fsl-ls2088a-rdb.dtb Image->Image--6.6.23+git0+b586a52177-r0-ls2088ardb-20240711074828.bin Image--6.6.23+git0+b586a52177-r0-ls2088ardb-20240711074828.bin Image-ls2088ardb.bin->Image--6.6.23+git0+b586a52177-r0-ls2088ardb-20240711074828.bin ls2088ardb_boot.scr modules--6.6.23+git0+b586a52177-r0-ls2088ardb-20240711074828.tgz modules-ls2088ardb.tgz->modules--6.6.23+git0+b586a52177-r0-ls2088ardb-20240711074828.tgz u-boot.bin->u-boot-tfa-2024.04++fslgit-r0.bin u-boot.bin-tfa->u-boot-tfa-2024.04++fslgit-r0.bin u-boot.bin-tfa-secure-boot->u-boot-tfa-secure-boot-2024.04++fslgit-r0.bin u-boot-ls2088ardb.bin->u-boot-tfa-2024.04++fslgit-r0.bin u-boot-ls2088ardb.bin-tfa->u-boot-tfa-2024.04++fslgit-r0.bin u-boot-ls2088ardb.bin-tfa-secure-boot->u-boot-tfa-secure-boot-2024.04++fslgit-r0.bin u-boot-qoriq-initial-env-ls2088ardb-tfa->u-boot-qoriq-initial-env-ls2088ardb-tfa-2024.04++fslgit-r0 u-boot-qoriq-initial-env-ls2088ardb-tfa-2024.04++fslgit-r0 u-boot-qoriq-initial-env-ls2088ardb-tfa-secure-boot->u-boot-qoriq-initial-env-ls2088ardb-tfa-secure-boot-2024.04++fslgit-r0 u-boot-qoriq-initial-env-ls2088ardb-tfa-secure-boot-2024.04++fslgit-r0 u-boot-qoriq-initial-env-tfa->u-boot-qoriq-initial-env-ls2088ardb-tfa-2024.04++fslgit-r0 u-boot-qoriq-initial-env-tfa-secure-boot->u-boot-qoriq-initial-env-ls2088ardb-tfa-secure-boot-2024.04++fslgit-r0 u-boot-tfa-2024.04++fslgit-r0.bin u-boot-tfa-secure-boot-2024.04++fslgit-r0.bin Thanks Re: How qemu load dtb on LS2088ardb You cannot emulate the device in a PC. This would need to create a new QEMU image that works with all the modules of the LS2088A and we do not have any image like that. What I understood was to simulate an Arm OS with QEMU in the board and you can for sure do that.

FS4500ウェイクアップ 助けを求めること、 1.FS4500のスリープモードを設定するときに、SPI命令を呼び出すだけでGO_LPOFFビットを1に設定すればよいかどうかを知りたいです。SPI命令が正常に記述されると、コード実行現象は次のコードの実行を停止します。 2。1145トランシーバーのINHピンがFS4500のIO_0に接続されている場合、1145トランシーバーを使用してFS4500をLPOFFからウェイクアップする場合、ホストコンピューターを使用してCANパケットを送信するだけで1145トランシーバーをウェイクアップする必要がありますか？1145トランシーバーのINHピンは自動的にFS4500のIO_0に影響を与え、FS4500をウェイクアップします。次のコードを続けてもいいですか、それともFS4500を起動するには別の方法が必要ですか？ 助けを求める Re: FS4500 wake up どこの会社ですか？ウェブサイトはありますか？ Re: FS4500 wake up こんにちは。まだ社内メールアドレスはお持ちではありませんが、社内WeChatはございます。関連情報を社内WeChatから送っていただけますか？ 社内WeChatの受信ボックス：[email protected] Re: FS4500 wake up 現在使用しているボードは複数の層があり、層間の配線が中央にあるため、簡単には切断できません。マニュアルによると、IO_0は入力であるはずです。なぜSPI操作のFS4500命令がスリープモードに入り、1145のINH出力に影響を与えるのか分かりません。 Re: FS4500 wake up これは何が原因でしょうか? Re: FS4500 wake up 3番目のステップでは、1145のINHを切断し、SBC IO0がHighかINHがHighかを確認します。何も操作しない場合は、1145はまだスリープ状態です。 Re: FS4500 wake up ある現象をテストしました。 1. 1145 トランシーバーが初期化され、スリープ モードに入った後、1145 の INH ピンがロー レベルであることが測定され、この時点で FS4500 の IO_0 ピンがロー レベルであることがテストされます (これは正しいです)。 2. 次に、FS4500 は初期化プロセスを実行し、FS4500 は通常モードに変更され、1145 の INH ピンが低レベルであることを測定し、FS4500 の IO_0 ピンが低レベルであることをテストします (これは正しいです)。 3. SPI命令（レジスタGO_LPOFFを1に変更する）でFS4500をスリープモードに設定した後、1145のINHピンがHighになり、FS4500のIO_0ピンもHighになります。この時点では、ホストコンピュータにメッセージは送信されません。なぜでしょうか？しかし、このコード現象は依然として発生し、後続のコードの実行は停止します。 Re: FS4500 wake up ご回答ありがとうございます。確認させていただきたいです。 1. SPI 命令を使用してレジスタ GO_LPOFF を 1 に設定した後、この時点でコードの実行が停止するのは正常ですか? 2. マニュアルによると、現在の状態がLPOFFスリープまたはディープフェイルセーフのいずれであっても、IO_0でウェイクアップできます。SPI命令を使用してFS4500を低消費電力モードに設定する前に、1145をスリープモードに設定し、FS4500のレジスタWU_IO0_1:0を01に設定しておきます。他に何か操作が必要ですか？その後、ホストコンピュータを使用してCANメッセージを送信し、1145をウェイクアップします。現象：FS4500は低消費電力モードから抜け出せず、コードの実行を継続できません。 Re: FS4500 wake up レジスタを見て 1145 の状態を確認することで、その状態を確認できます。 Re: FS4500 wake up 1. SPI 命令を使用してレジスタ GO_LPOFF を 1 に設定した後、この時点でコードの実行が停止するのは正常ですか? 【gw】下記の説明を参照してください。MCU はスリープ モードに入った後に電源が切れます。 2. マニュアルによると、現在の状態がLPOFFスリープまたはディープフェイルセーフのいずれであっても、IO_0でウェイクアップできます。SPI命令を使用してFS4500を低消費電力モードに設定する前に、1145をスリープモードに設定し、FS4500のレジスタWU_IO0_1:0を01に設定しておきます。他に何か操作が必要ですか？その後、ホストコンピュータを使用してCANメッセージを送信し、1145をウェイクアップします。現象：FS4500は低消費電力モードから抜け出せず、コードの実行を継続できません。 【gw】スリープに入ってから、INHの電圧変化波形をキャプチャしましたか？ Re: FS4500 wake up こんにちは、会社のウェブサイト https://gkanghui.com/ Re: FS4500 wake up このウェイクアップ構成は、通常フェーズではなく、初期化 INIT フェーズ中に構成されます。 初期化中にこのレジスタに触れましたか? Re: FS4500ウェイクアップ 1.FS4500のスリープモードを設定するときに、SPI命令を呼び出すだけでGO_LPOFFビットを1に設定すればよいかどうかを知りたいです。SPI命令が正常に記述されると、コード実行現象は次のコードの実行を停止します。 [GW]看我标出来的箭头两个方式进入sleep的模式。 DFS要不要进入看上面的SELECTpin设定 2。1145トランシーバーのINHピンがFS4500のIO_0に接続されている場合、1145トランシーバーを使用してFS4500をLPOFFからウェイクアップする場合、ホストコンピューターを使用してCANパケットを送信するだけで1145トランシーバーをウェイクアップする必要がありますか？1145トランシーバーのINHピンは自動的にFS4500のIO_0に影響を与え、FS4500をウェイクアップします。次のコードを続けてもいいですか、それともFS4500を起動するには別の方法が必要ですか？ [gw]你是想通过1145的INHpin唤醒FS45吗从LPOFF模式？可以看下面圈出来的唤醒方式，如果是通过IO唤醒在进入sleep之前就要设定好，你要看不同模式下1145 INH的状态是不是符合唤醒的要求从而决定要不要1145 进入低功耗模式，逻辑很清楚需要您自己去设计这个功能 Re: FS4500 wake up 1145のINHピンのテストがあります。低電力モードに入った直後、マルチメーターでテストすると0Vになります。ホストコンピュータを使用してメッセージを送信した後、INHピンを再度テストすると12Vになります。 Re: FS4500 wake up ご回答ありがとうございます。問題の原因が分かりました。 Re: FS4500 wake up どちらの会社に所属されていますか？会社のメールアドレスを使って質問してもよろしいでしょうか？ 個人のメールアドレスを使用すると、より低いレベルで処理できるため

I2C接口的MPC5478G 你好，我想使用 MPC5748G 与放大器通信。我正在使用 Power Architecture 的 i2c_transfer_mpc5748g 示例代码。放大器的地址是0x70。我需要做哪些修改才能实现这一点？此外，i2c 驱动程序发送 地址->数据，但我想使其成为放大器的地址（地址）->放大器寄存器（子地址）->数据。

I2C MPC5478G Hi, I want to communicate with an amplifier using the MPC5748G. I'm using the i2c_transfer_mpc5748g sample code from the Power Architecture. The amplifier's address is 0x70. What modifications do I need to make to achieve this? also i2c driver sends adress->data  but i want to make it adress of amplifier(adress) ->amplifier register(subadress)-> data. Re: I2C MPC5478G Hi, the Slave device address is set within Component inspector and it is automatically sent as first byte after START is issued. The Slave’s register/memory address, must be stored into first byte(s) of the “txBuffer” depending on address size.   So assuming 16bit address is used and you want to write 8 bytes (1,2,3,..,8) to Slave address 0x000C, then prepare txBuffer as   txBuffer = {0x00, 0x0C, 1, 2, 3, 4, 5, 6, 7, 8};   and use I2C_DRV_MasterSendDataBlocking(instance, txBuffer, 10, true, timeout);   If you want to read 8 bytes from the same memory address then use this   I2C_DRV_MasterSendDataBlocking(instance, txBuffer, 2, false, timeout); // just memory/register address will be sent after Slave address so total 3 bytes, STOP is not generated I2C_DRV_MasterReceiveDataBlocking(instance, rxBuffer, 8, true, timeout); // Repeat Start is issued following Slave address and waiting reading for 8 bytes Hope it helps. BR, Petr

FRDM-MCXN947 : smartdma_camera_flexio_mculcd demo example issue : only one line on LCD Hello, I successfully solder and connect my FRDM-MCXN947 to OV7670 camera and LCD PAR-LCD-S035 since I am able to run the demo "Multiple face detection on MCXN947" provided using MCUXpresso Projects from Application Code Hub.  My problem is that I encounter the following issue executing the "frdmmcxn947_smartdma_camera_flexio_mculcd example" : only one line of the camera is displayed on the top of the LCD display. I am running the latest MCUXpresso version (24.12) I get the "frdmmcxn947_smartdma_camera_flexio_mculcd example" directly from MCUXpresso using "Welcome"->Import SDK Examples ->Go straight to the Wizard" then frdmmcxn947 board (SDK 2.x_MCXN947/version 2.16.100/Manifest 3.14.00), then "display_examples" then "smartdma_camera_flexio_mculcd".  This project compiles, download and executes correctly but I get a black lcd screen with only one line updated by the camera. I read the doc given on AN14191.pdf ( on https://docs.nxp.com/bundle/AN14191/page/topics/software.html#topic_30f829c2-0650-45e1-ab55-320979025292__fig_xmg_lpv_c1c" ) but that doesn't help much to understand the poorly commented code of the example. Many thanks for your help, Thierry MCXN Re: FRDM-MCXN947 : smartdma_camera_flexio_mculcd demo example issue : only one line on LCD Dear Alice, Thank you so much, it works now : the problem was the source code example : I used the one provided from the MCUxpresso interface (Import SDK Examples ->Go straight to the Wizard" then frdmmcxn947 board (SDK 2.x_MCXN947/version 2.16.100/Manifest 3.14.00), then "display_examples" then "smartdma_camera_flexio_mculcd") which is faulty. The AN14191SW.zip  is perfect ! (and totaly different). Have a nice day ! Re: FRDM-MCXN947 : smartdma_camera_flexio_mculcd demo example issue : only one line on LCD Hello @tgrandpi  Please download the code from the AN14191 resource https://www.nxp.com/docs/en/application-note-software/AN14191SW.zip .  I've tested it on my end, it works well. Thank you. BR Alice Re: FRDM-MCXN947 : smartdma_camera_flexio_mculcd demo example issue : only one line on LCD Thank you Alice, but I already did that 3 modifications in order to run successfully the "Multiple face detection"  demo. So this is not a hardware problem since that demo work. Thank you for your help. Re: FRDM-MCXN947 : smartdma_camera_flexio_mculcd demo example issue : only one line on LCD Hello @tgrandpi  Please rework your board according to the following picture: BR Alice

FS4500唤醒 寻求帮助， 1.我想知道在设置FS4500睡眠模式时是否只需要调用SPI指令将GO_LPOFF位置1即可。SPI指令写入成功后，会出现代码跑分现象，停止执行后续代码。 2、假设1145收发器的INH引脚连接到FS4500的IO_0，如果要使用1145收发器将FS4500从LPOFF唤醒，是否只需要使用上位机发送CAN数据包即可唤醒1145收发器？1145收发器的INH引脚自动影响FS4500的IO_0，从而唤醒FS4500。后续的代码还能继续吗，还是需要其他方法来唤醒FS4500？ 寻求帮助 Re: FS4500 wake up 1145的wake引脚导致的 Re: FS4500 wake up 我现在用的板子是好几层的，他们之间的走线在中间，不太好断开，根据手册，IO_0应该就是输入，不明确SPI操作FS4500指令进入睡眠模式，为什么会影响到1145的INH输出 Re: FS4500 wake up 请问您是哪个公司？能否用公司的邮箱提问呢？ 因为用个人邮箱我们处理起来等级比较低 Re: FS4500 wake up 你好，我们还没有企业邮箱，有企业微信，相关资料你可以通过企业微信发给我吗，企业微信收件箱：[email protected] Re: FS4500 wake up 请问你们是什么公司啊？有网址吗？ Re: FS4500 wake up 你好，公司网址 https://gkanghui.com/ Re: FS4500 wake up 感谢你的回答，我还想确认下， 1、在使用SPI指令设置寄存器GO_LPOFF设置为1后，代码此时停止运行是否是正常的 2、从手册中获取到不管当前的状态处于LPOFF—sleep还是Deep fail safe,都是可以通过IO_0唤醒，在使用SPI指令设置FS4500 进入低功耗时前，已将1145设置进入睡眠模式，并且FS4500的寄存器WU_IO0_1:0已经设置成01，除此之外还需要什么操作吗，然后使用上位机发送CAN报文唤醒1145，现象：不能够使FS4500退出低功耗，代码不能够继续运行起来 Re: FS4500 wake up 1、在使用SPI指令设置寄存器GO_LPOFF设置为1后，代码此时停止运行是否是正常的 【gw】看下面的描述进入sleep以后 MCU都没电了 2、从手册中获取到不管当前的状态处于LPOFF—sleep还是Deep fail safe,都是可以通过IO_0唤醒，在使用SPI指令设置FS4500 进入低功耗时前，已将1145设置进入睡眠模式，并且FS4500的寄存器WU_IO0_1:0已经设置成01，除此之外还需要什么操作吗，然后使用上位机发送CAN报文唤醒1145，现象：不能够使FS4500退出低功耗，代码不能够继续运行起来 【gw】在进入sleep以后，你有抓到测试到INH的电压变化吗波形？ Re: FS4500 wake up 有测试1145的INH引脚，在初始进入低功耗模式时，使用万用表测试为0，使用上位机发送报文后，再次测试INH的引脚为12v Re: FS4500 wake up 这个配置唤醒的口是在初始化INIT的阶段配置的不是在normal下配置的 你在初始化阶段动过这个寄存器吗？ Re: FS4500 wake up 我现在测试到一种现象， 1、在1145收发器初始化进入睡眠模式之后，测量1145的INH引脚为低电平,测试FS4500的IO_0引脚此时是低电平（此时是正确的）， 2、然后FS4500执行初始化流程，FS4500变成normal模式，测量1145的INH引脚为低电平,测试FS4500的IO_0引脚此时是低电平（此时是正确的）， 3、通过SPI指令设置FS4500进入睡眠模式后（只是修改寄存器GO_LPOFF设置为1），此时测量1145的INH引脚为高电平,测试FS4500的IO_0引脚此时是高电平，当前没有对使用上位机发送任何报文，这个是为什么，不过代码现象还是停止执行后续代码， Re: FS4500 wake up 第三步你把1145 INH断开，再看看到地是SBC IO0 是高的还是INH是高的，如果你没有操作1145任然在sleep下。 Re: FS4500 wake up 你可以查看1145的状态通过寄存器查看下，看看目前是在哪个状态。 Re: FS4500 wake up 谢谢你的回答，我现在找到问题的原因了 Re: FS4500 wake up 那是什么原因导致的？ 回复：FS4500 唤醒 1.我想知道在设置FS4500睡眠模式时是否只需要调用SPI指令将GO_LPOFF位置1即可。SPI指令写入成功后，会出现代码跑分现象，停止执行后续代码。 [GW]看我标出来的箭头两个方式进入sleep的模式。 DFS要不要进入看上面的SELECTpin设定 2. 1145收发器的INH引脚连接到FS4500的IO_0，如果要用1145收发器将FS4500从LPOFF状态唤醒，是不是只需要上位机发送CAN数据包就可以唤醒1145收发器？1145收发器的INH引脚会自动影响FS4500的IO_0，从而唤醒FS4500。后续代码可以继续写吗，还是需要其他方法来唤醒FS4500？ [gw]你是想通过1145的INHpin唤醒FS45吗从LPOFF模式？可以看下面圈出来的唤醒方式，如果是通过IO唤醒在进入sleep之前就要设定好，你要看不同模式下1145 INH的状态是不是符合唤醒的要求从而决定要不要1145 进入低功耗模式，逻辑很清楚需要您自己去设计这个功能

FS4500 wake up Asking for help, 1. I want to know whether it is only necessary to call the SPI instruction to set the GO_LPOFF bit to 1 when setting the FS4500 sleep mode. After the SPI instruction is written successfully, the code running phenomenon will stop executing the subsequent code. 2. Given that the INH pin of 1145 transceiver is connected to IO_0 of FS4500, if you want to use 1145 transceiver to wake up FS4500 from LPOFF, do you only need to use the host computer to send CAN packet to wake up 1145 transceiver? The INH pin of the 1145 transceiver automatically affects the IO_0 of the FS4500 to wake up the FS4500. Can the subsequent code be continued, or does another method be required to wake up the FS4500? Asking for help Re: FS4500 wake up 1. I want to know whether it is only necessary to call the SPI instruction to set the GO_LPOFF bit to 1 when setting the FS4500 sleep mode. After the SPI instruction is written successfully, the code running phenomenon will stop executing the subsequent code. [GW]看我标出来的箭头两个方式进入sleep的模式。 DFS要不要进入看上面的SELECTpin设定 2. Given that the INH pin of 1145 transceiver is connected to IO_0 of FS4500, if you want to use 1145 transceiver to wake up FS4500 from LPOFF, do you only need to use the host computer to send CAN packet to wake up 1145 transceiver? The INH pin of the 1145 transceiver automatically affects the IO_0 of the FS4500 to wake up the FS4500. Can the subsequent code be continued, or does another method be required to wake up the FS4500? [gw]你是想通过1145的INHpin唤醒FS45吗从LPOFF模式？可以看下面圈出来的唤醒方式，如果是通过IO唤醒在进入sleep之前就要设定好，你要看不同模式下1145 INH的状态是不是符合唤醒的要求从而决定要不要1145 进入低功耗模式，逻辑很清楚需要您自己去设计这个功能 Re: FS4500 wake up Hello, we don’t have a corporate email yet, but we have corporate WeChat. Can you send me the relevant information through corporate WeChat? Corporate WeChat inbox: [email protected] Re: FS4500 wake up The board I am using now has several layers, and the wiring between them is in the middle, which is not easy to disconnect. According to the manual, IO_0 should be input. I am not sure why the SPI operation FS4500 instruction enters sleep mode and affects the INH output of 1145 Re: FS4500 wake up What caused this? Re: FS4500 wake up There is a test of the INH pin of 1145. When it initially enters the low power mode, it is 0 when tested with a multimeter. After sending a message using the host computer, the INH pin is tested again and it is 12v. Re: FS4500 wake up 1. After using the SPI instruction to set the register GO_LPOFF to 1, is it normal for the code to stop running at this time? 【gw】See the description below and the MCU is out of power after entering sleep mode. 2. From the manual, no matter the current state is LPOFF-sleep or Deep fail safe, it can be awakened by IO_0. Before using the SPI instruction to set FS4500 to enter low power consumption, 1145 has been set to sleep mode, and the register WU_IO0_1:0 of FS4500 has been set to 01. Is there any other operation required? Then use the host computer to send CAN message to wake up 1145. Phenomenon: FS4500 cannot exit low power consumption and the code cannot continue to run 【gw】After entering sleep, did you capture the voltage change waveform of INH? Re: FS4500 wake up I have tested a phenomenon. 1. After the 1145 transceiver is initialized and enters sleep mode, the INH pin of 1145 is measured to be low level, and the IO_0 pin of FS4500 is tested to be low level at this time (this is correct). 2. Then FS4500 executes the initialization process, FS4500 changes to normal mode, measures the INH pin of 1145 to be low level, and tests the IO_0 pin of FS4500 to be low level (this is correct). 3. After setting FS4500 to sleep mode through SPI instruction (just modify register GO_LPOFF to 1), the INH pin of 1145 is high at this time, and the IO_0 pin of FS4500 is high at this time. Currently, no message is sent to the host computer. Why is this? However, the code phenomenon still stops executing subsequent codes. Re: FS4500 wake up What company are you from? Do you have a website? Re: FS4500 wake up Thank you for your answer, I found the cause of the problem now. Re: FS4500 wake up This wake-up configuration is configured during the initialization INIT phase, not during the normal phase. Did you touch this register during initialization? Re: FS4500 wake up In the third step, disconnect 1145 INH and see if SBC IO0 is high or INH is high. If you do not operate, 1145 is still in sleep. Re: FS4500 wake up Thanks for your answer, I want to confirm. 1. After using the SPI instruction to set the register GO_LPOFF to 1, is it normal for the code to stop running at this time? 2. From the manual, no matter the current state is LPOFF-sleep or Deep fail safe, it can be awakened by IO_0. Before using the SPI instruction to set FS4500 to enter low power consumption, 1145 has been set to sleep mode, and the register WU_IO0_1:0 of FS4500 has been set to 01. Is there any other operation required? Then use the host computer to send CAN message to wake up 1145. Phenomenon: FS4500 cannot exit low power consumption and the code cannot continue to run Re: FS4500 wake up Hello, company website https://gkanghui.com/ Re: FS4500 wake up Which company are you from? Can I use the company's email address to ask questions? Because we can handle it at a lower level if you use a personal email address

S32K311-寄存器无法访问 大家好， 我最近从 S32K312 切换到 S32K311 统一引导加载程序，但我遇到了一些驱动程序寄存器不再可访问的问题。具体来说，我正在使用 CAN 通信，某些寄存器（SFR）似乎无法访问。我附上了一张图片来说明这个问题。 有人能提供关于这个问题的潜在原因或解决方案的见解吗？如能就 S32K312 和 S32K311 之间的配置差异（可能影响寄存器（SFR）访问）提出任何建议，我们将不胜感激。 提前谢谢！ 顺祝商祺！

S32K311 - Register Can not Access Hi all, I recently switched from the S32K312 to the S32K311 Unified Bootloader, but I am encountering an issue where some of the driver registers are no longer accessible. Specifically, I am using CAN communication, and certain registers (SFRs) seem to be unreachable. I’ve attached an image to illustrate the issue. Could anyone provide insights into potential causes or solutions for this problem? Any advice on configuration differences between the S32K312 and S32K311 that could be affecting register (SFRs) access would be greatly appreciated. Thank you in advance! Best regards. Re: S32K311 - Register Can not Access Hi The S32K3XXRM mentions: The peripherals working on the system clock should be clock-gated used the MC_ME.PRTNx_COFBy_CLKEN configurations. According to Table 260. MC_ME partition peripheral mapping and clock control, please check the value of FlexCAN 0: PRTN1_COFB2_CLKEN[REQ65] If this bit was 0, Please check whether the FlexCAN 0 clock gate is enabled in the S32 Configuration Tool. Also, does your program call the Clock_Ip_Init function? Best Regards, Robin ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "ACCEPT AS SOLUTION" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. -------------------------------------------------------------------------------

S32K311-登録にアクセスできません 皆さん、こんにちは 最近、S32K312からS32K311ユニファイドブートローダーに切り替えましたが、一部のドライバーレジスターにアクセスできなくなるという問題が発生しています。具体的には、CAN通信を使用していますが、特定のレジスタ（SFR）にアクセスできないようです。問題を説明する画像を添付しました。 この問題の潜在的な原因や解決策についての洞察を誰かが提供できますか？レジスタ（SFR）へのアクセスに影響する可能性のあるS32K312とS32K311の設定の違いに関するアドバイスをいただければ幸いです。 お手数ですが、よろしくお願いいたします。 よろしくお願いいたします。

How to suppress a specific compiler warning message CW 11.1 Hi, I'm using CW 11.1 because my processor is MC9S08DZ60A. I am porting some code from another compiler. I would like to suppress compiler warning C1420, return value ignored, because it flags every printf. I found a screen that looks likely, but I put C1420 in there, and also tried just 1420, and the warnings still come up. See attached screenshot. Is there a way to stop a specific warning message number, or a list of them? Thanks, Lloyd Re: How to suppress a specific compiler warning message CW 11.1 Thank you so much! That worked! Then I added more on the same line like this: -WmsgSd1420 -WmsgSd2705 I appreciate the help! Lloyd Re: How to suppress a specific compiler warning message CW 11.1 Hi @lslonim  Please add  -WmsgSd1420 to compiler setting to disable C1420 Thanks, Jun Zhang

NCJ29D5の安全なNVストレージエリアにあるキーをTrace32で削除できますか？ こんにちは、皆さん。 私はUCJ29D5を使ってUWBレンジングを行っています。 キーをNVエリアに保存することに成功しましたが、trace32を使ってキーを消去する方法はありますか？ 'FLASH.ERASE'コマンドで試してみましたが、失敗しました。 メモリ領域は保護領域だと思いますが、何か方法を知りたいです。 ありがとうございます。

S32DS_ARM_Win32_v2.2 activation code acquisition problem S32DS_ARM_Win32_v2.2 The official website does not provide an activation code now, and I can't find a link. However, the customer's software has expired and I want to continue using version 2.2. Can you help me provide an activation code? Re: S32DS_ARM_Win32_v2.2 激活码获取问题 Hi,  I checked the account related to the activation key and it looks, that the S32DS license is already extended.  Re: S32DS_ARM_Win32_v2.2 激活码获取问题 Hi,  your S32DS license has been extended.  Re: S32DS_ARM_Win32_v2.2 激活码获取问题 My S32DS_ARM_Win32_v2.2 license has expired too.  Could you please extend the license for me?  59DD-0D10-2BAA-6F30 Re: S32DS_ARM_Win32_v2.2 激活码获取问题 Sorry , it's S32DS_Power_Win32_v2.1 Software Activation Code is already used on this station for 3 Activated 2.2.   AI润色 130/5000   This is my activation code. B029-D748-6F13-04AD Software Activation Code is already used on this station for 3 Activated 2.2. Could you please help me? Thank you!! Re: S32DS_ARM_Win32_v2.2 激活码获取问题 您好，我的也无法激活，显示“Your  Software Activation Code is for another feature. Do you want to return it?”能帮我解决一下吗？ Re: S32DS_ARM_Win32_v2.2 激活码获取问题 Product: S32 Design Studio for ARM Activation ID: 9123-5215-159A-B8D0 Could you please help to extend the license? Thank you. 回复： S32DS_ARM_Win32_v2.2 激活码获取问题 Could you help me apply for a new license since my current license has expired? 4249-2545-9811-9321 thank you Re: S32DS_ARM_Win32_v2.2 激活码获取问题 Could you help me apply for a new license since my current license is about to expire? 0513-AA9F-08E2-FFE7 thank you

S32DS_ARM_Win32_v2.2 アクティベーションコード取得問題 S32DS_ARM_Win32_v2.2 公式サイトでは現在アクティベーションコードが提供されておらず、リンクも見つかりません。しかし、お客様のソフトウェアの有効期限が切れているため、バージョン2.2を引き続き使用したいのですが、アクティベーションコードの提供をお手伝いいただけますか？ Re: S32DS_ARM_Win32_v2.2 激活码获取问题 申し訳ありませんが、S32DS_Power_Win32_v2.1です Re: S32DS_ARM_Win32_v2.2 激活码获取问题 こんにちは、 S32DS ライセンスが延長されました。 Re: S32DS_ARM_Win32_v2.2 激活码获取问题 私のS32DS_ARM_Win32_v2.2ライセンスも期限切れです。ライセンスを延長していただけますか? 59DD-0D10-2BAA-6F30 Software Activation Code is already used on this station for 3 Activated 2.2.   愛润色 130 / 5000   これが私の認証コードです。B029-D748-6F13-04AD ソフトウェアのアクティベーションコードは、このステーションで既に3つのアクティベート済み2.2に使用されています。 手伝っていただけませんか？ありがとう！！ Re: S32DS_ARM_Win32_v2.2 激活码获取问题 您好，我的也無法激活，显表示「あなたのソフトウェア アクティベーション コードは別の機能用です。返却しますか?」能帮我解决一下吗? Re: S32DS_ARM_Win32_v2.2 激活码获取问题 製品：S32 Design Studio for ARM アクティベーションID: 9123-5215-159A-B8D0 ライセンスの延長にご協力いただけますでしょうか？ありがとう。 回复： S32DS_ARM_Win32_v2.2 激活码获取问题 現在の免許証の有効期限が切れたので、新しい免許証の申請手続きを手伝っていただけますか？ 4249-2545-9811-9321 よろしくお願い申し上げます。 Re: S32DS_ARM_Win32_v2.2 激活码获取问题 私の現在の免許証の有効期限が間もなく切れるので、新しい免許証の申請手続きを手伝っていただけませんか？ 0513-AA9F-08E2-FFE7 ありがとう

我可以通过 Trace32 删除 NCJ29D5 安全 NV 存储区域中的密钥吗？ 大家好， 我正在使用 NCJ29D5 进行 UWB 测距。 我成功地将密钥存储到 NV 区域，但是有没有办法使用 trace32 擦除它？ 当我尝试使用“FLASH.ERASE”命令时，失败了。 我认为内存区域是安全区域，但我想知道任何方法。 谢谢。

Can I delete a key in the secure NV storage area of NCJ29D5 by Trace32? Hi All, I'm working with NCJ29D5 for UWB ranging. I succeed to store a key into NV area, but is there any way to erase it using the trace32? When I tried it with 'FLASH.ERASE' command, i failed. I think the memory area is secured area, but I want to know any method. Thanks. Re: Can I delete a key in the secure NV storage area of NCJ29D5 by Trace32? Hello, Hope you are doing well. Sorry for the inconvenience this might cause you but as the information of this product it's under NDA (Non-Disclosure Agreement) the information it's not public. For more information about the chip could you please contact one of our distributors available in the Distributor Network|NXP? Or if you have any direct contact who helped you getting this device, please contact them. Regards, Ricardo