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S32K3XXがLWIPプロトコルスタック上で自身のIPアドレスを確立できない問題について。 こんにちは: S32DSで独自のローカルIPアドレスを作成し、LWIPプロトコルスタックでローカルIPアドレスを無効にしましたが、上の右下の画像に示すように、シングルステップデバッグ中に接続確立に失敗するエラーが発生します。何が問題なのでしょうか?設定が不足しているのでしょうか?ローカルIPアドレスの作成は許可されておらず、プロトコルスタックで設定する必要があるということでしょうか? お忙しい中、お返事いただき、改めてありがとうございました! 回复: 关于S32K3XX 在LWIP 协议栈上自己建立IP地址无法建立的问题 こんにちは、@sunshine88 さん。 はい、 Enable iface は選択されたままでなければなりません。なぜなら、生成された設定はイーサネットインターフェースの初期化とlwIP接続に必要だからです。したがって、インターフェースを無効にして自分の netif_add() コールだけで作成するのは、この例では正しいアプローチではありません。 初期テストでは、TCP/IPスタック設定ページで静的IPv4アドレス、サブネットマスク、ゲートウェイを設定し、コードを再生成してください。 インターフェースが初期化された後もIPアドレスはプログラム的に変更可能ですが、生成されたインターフェース構成自体は省略してはなりません。 よろしくお願いいたします。 パベル 回复: 关于S32K3XX 在LWIP 协议栈上自己建立IP地址无法建立的问题 前述のとおり、LWIPデモの実行に成功した後は、すべてのIP設定は設定ページから行う必要があります。手動設定は許可されておらず、IP設定を無効にすることもできません。私が使用したS32DSのバージョンはS32 Design Studio for S32 Platform Version: 3.5、RTDのバージョンはV4.0.0です。TCPIP_STACKのバージョンはV1.0.4です。改めて確認しますが、IPアドレスは設定ページで構成する必要があります。無効になっているIP設定ページでは手動で構成することはできません。 スクリーンショット 2026-09-18 164944.png スクリーンショット 2026-09-18 165031.png スクリーンショット 2026-09-18 165228.png 回复: 关于S32K3XX 在LWIP 协议栈上自己建立IP地址无法建立的问题 こんにちは、@sunshine88 さん。 IPv4アドレス自体がこのエラーの原因ではありません。lwIPでは、 netif_add() を介して静的IPv4アドレスを直接提供できます。 デバッガのスクリーンショットによると、 netif_add() はネットワークインターフェースの初期化コールバック ETHIF_INIT が ERR_OK 返さないため、 NULL を返します。したがって、エラーはイーサネットインターフェースまたはその下位ドライバの初期化時に発生し、インターフェースがlwIPに追加される前に発生します。 TCP/IPスタック構成のスクリーンショットでは、 「ifaceを有効にする」オプションが選択されていません。ネットワークインターフェースを有効にし、必要な静的IPv4アドレス、サブネットマスク、ゲートウェイを設定してください。次に、設定を再生成し、対応するS32K3 lwIPの例にある初期化シーケンスを使用します。 アプリケーションで住所を割り当てたい場合は、まず成功 netif_add() 確認してください。 これは初期化の失敗を検出しやすくするだけのものであることにご注意ください。GMAC/イーサネットの基礎設定を修正するわけではありません。 まずは、ネットワーク初期化を変更しずに、あなたのS32K3デバイスとソフトウェアパッケージのバージョンに合わせて元のlwIP例をビルドし実行することをお勧めします。元の例が正常に動作したら、静的IPv4アドレスのみを変更して結果を確認してください。 初期化がそれでも失敗する場合は、以下の情報も提供してください。 正確なS32K3デバイスと評価ボード S32 Design Studio版 RTDおよびTCP/IPスタックパッケージのバージョン ETHIF_INIT の定義と、その関数が返すエラー 変更されていないlwIPの例が同じハードウェアで動作するかどうか 同じ質問が3つの別々のコミュニティ投稿で寄せられたようです。トラブルシューティング情報を一箇所にまとめるため、議論はどちらか一方のフォーラムのみで行ってください。 よろしくお願いいたします。 パベル 回复: 关于S32K3XX 在LWIP 协议栈上自己建立IP地址无法建立的问题 スクリーンショット 2026-09-18 100140.png スクリーンショット 2026-09-18 100315.png スクリーンショット 2026-09-18 100756.png 上記の問題には、アップロードされたコード行が含まれていません。ご確認ください。
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S32K118 Interrupts Hi all, I am triyng to setup an interrupt on LPTI timer or LPTMR0 one. Both timers are running in the correct way (the end count flags will be settled) but no way to get the interrupt. I am using S32K118 evaluation board and S32DS IDE. Can someone help me? Thanks in advance. Re: S32K118 Interrupts You can also get the interrupt examples through installing "S32SDK_S32K1xx_RTM_4.0.2.exe" Re: S32K118 Interrupts Hi Please refer to the LPIT and LPTMR interrupt examples in S32K1 SDK 4.0.3 of S32DS v3.4. lpit lptmr interrupt S32K1 SDK RTM 4.0.3.png Best Regards, Robin ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. -------------------------------------------------------------------------------
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关于S32K3XX 在LWIP 协议栈上自己建立IP地址无法建立的问题 你好:            现在我在S32DS 中中自己建立本机IP地址,设置LWIP协议栈中本地IP地址失效,但是单步调试时会报错,无法建立链接,如上最下面右侧所示,请问问题出在哪里?是缺少什么设置吗?难道时不允许自己建立本地IP,必须在协议栈中配置吗?          再次感谢在百忙之中回复! 回复: 关于S32K3XX 在LWIP 协议栈上自己建立IP地址无法建立的问题 你好@sunshine88 , 是的,必须保持选中状态以启用接口,因为需要生成的配置来初始化以太网接口并将其连接到 lwIP。因此,禁用接口并仅通过您自己的 netif_add() 调用来创建它,对于此示例来说不是正确的方法。 为进行初始测试,请在 TCP/IP 协议栈配置页面上配置静态 IPv4 地址、子网掩码和网关,然后重新生成代码。 接口初始化后,IP 地址仍然可以以编程方式更改,但生成的接口配置本身不能省略。 顺祝商祺! 帕维尔 回复: 关于S32K3XX 在LWIP 协议栈上自己建立IP地址无法建立的问题 如上所述,跑通LWIP Demo后所有IP 配置工作必须在配置页配置不可以自己配置,也不可失能IP配置。我用的S32DS版本是S32 Design Studio for S32 Platform Version: 3.5, RTD 版本是V4.0.0,  TCPIP_STACK 版本是V1.0.4  。我再次确认一下,必须在设置叶配置IP地址呗。不能失能IP配置页自己配置! 屏幕截图 2026-09-18 164944.png 屏幕截图 2026-09-18 165031.png 屏幕截图 2026-09-18 165228.png 回复: 关于S32K3XX 在LWIP 协议栈上自己建立IP地址无法建立的问题 你好@sunshine88 , IPv4 地址本身并不是造成此错误的原因。lwIP 允许通过 netif_add() 直接提供静态 IPv4 地址。 根据调试器截图, netif_add() 返回 NULL ,因为网络接口初始化回调函数 ETHIF_INIT 没有返回 ERR_OK 。因此,故障发生在以太网接口或其底层驱动程序初始化期间,在将接口添加到 lwIP 之前。 在您的 TCP/IP 协议栈配置截图中, “启用接口”选项未被选中。请启用网络接口,并在该接口上配置所需的静态 IPv4 地址、子网掩码和网关。然后重新生成配置,并使用相应的 S32K3 lwIP 示例中的初始化序列。 如果您仍然想在应用程序中分配地址,请先验证 netif_add() 是否成功。 请注意,这只是使初始化失败更容易被检测到。它无法修正底层 GMAC/以太网配置。 我建议首先针对您的 S32K3 设备和软件包版本构建并运行原始的 lwIP 示例,不要修改其网络初始化。如果原示例运行正常,则仅更改静态 IPv4 地址并确认结果。 如果初始化仍然失败,请同时提供以下信息: 精确的 S32K3 设备和评估板 S32 设计工作室版本 RTD 和 TCP/IP 协议栈软件包版本 ETHIF_INIT 的定义以及该函数返回的错误 未经修改的 lwIP 示例是否能在相同的硬件上运行 同一个问题似乎在三个不同的社区帖子中被提交了。为了将故障排除信息集中在一个地方,请只在一个地方继续讨论。 此致敬礼, 帕维尔 回复: 关于S32K3XX 在LWIP 协议栈上自己建立IP地址无法建立的问题 屏幕截图 2026-09-18 100140.png 屏幕截图 2026-09-18 100315.png 屏幕截图 2026-09-18 100756.png 上面的问题没有上传代码行,请查看
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S32DS许可证已过期 您好,NXP支持团队, 我的S32DS v2.2许可证已于2026年8月24日到期。请问您能否帮忙延长许可证期限? 激活码:563B-6314-7B07-7945 感谢您的支持。 Re: S32DS License Expired 您好, 您的S32DS许可证已延期。请使用您之前的激活码重新激活S32DS。
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S32DS License Expired Hello NXP Support Team,   My S32DS v2.2 license expired on August 24, 2026. Could you please help extend the license? Activation Code: 563B-6314-7B07-7945   Thank you for your support. Re: S32DS License Expired Hi, your S32DS license has been extended. Please activate S32DS again with your old code. 
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RT1xxx ENET: ラップアラウンド値を変更するためにATCORを書き込むと、修正カウンタはリセットされますか? こんにちは、 ETETペリフェラルの補正カウンターはATCORの書き込み時にリセットされるのかもしれません。 あるいは、ATCORの値が変更された場合にのみリセットされるのかもしれません。 よろしくお願いいたします 最大 i.MXRT 102x i.MXRT 105x
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S32K314 プログラミングエラー こんにちは デバッグモードを使用してDFLASHにデータを書き込もうとしたところ、失敗しました。 以下は私のコードの概略です。 0xFFFFF800 を 0x40268350 に書き込む PFCPGM_PEARR_Lレジスタに0x10000000を書き込みます。 プログラムDATA0に0xFFFFFFFFを書き込む MCR[ERS]を1に設定 MCR[ERS]セクターを選択 MCR[EHV]を1に設定する MCRS[DONE]を待機し、MCRS[PEG]をチェックします。 MCR[EHV]を0に設定、SETMCR[ERS]を0に設定 11セクター消去後 PFCPGM_PEARR_Lレジスタに0x10000000を書き込みます。 DATA0~DATA7に256ビットのデータを書き込む MCR[PGM]を1に設定 MCR[EHV]を1に設定 MCRSレジスタを読み取り、0x0000C100を取得します。 しかし、2回目のループをしたとき PFCPGM_PEARR_Lレジスタに0x10000000を書き込みます。 DATA0~DATA7に256ビットのデータを書き込む MCR[PGM]を1に設定 MCR[EHV]を1に設定 MCRSレジスタを読み取り、0x00008100を取得します。 この状況の原因を知りたいです。 リカ 回复: S32K314编程错误 さらに、消去/プログラミングが完了したことを確認した後、以下の手順を実行しました。 MCR[EHV]に0を設定 MCR[PGM/ERS]に0を設定
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RT1051: ENET IEEE1588タイマークロックソース こんにちは、 RT1050 の リファレンス マニュアル には 以下の 情報 があります: mastupristi_0-1789736651417.png IEEE1588タイマーのクロックソースが何なのか知りたいです。例えば、AUDIO_PLLから派生したルートクロックを選べますか? IEEE1588タイマーのクロックソースを制御するレジスタはどれですか? よろしくお願いいたします 最大 i.MXRT 105x
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S32K314编程错误 您好 当我通过debug尝试往DFLASH中写数据时失败了 下面是我的代码大概流程 write 0xFFFFF800 to 0x40268350   wtire 0x10000000 to PFCPGM_PEARR_L register write 0xFFFFFFFF to Program DATA0 set MCR[ERS] to 1   MCR[ERS] choose sector set MCR[EHV] to 1 wait MCRS[DONE] be 1 check MCRS[PEG] set MCR[EHV] to 0  SETMCR[ERS]to 0 after erase 11 sectors wtire 0x10000000 to PFCPGM_PEARR_L register write 256 bit data to DATA0~DATA7 set MCR[PGM] to 1  set MCR[EHV] to 1 read MCRS register get 0x0000C100 但是当我第二次循环 wtire 0x10000000 to PFCPGM_PEARR_L register write 256 bit data to DATA0~DATA7 set MCR[PGM] to 1  set MCR[EHV] to 1 read MCRS register get 0x00008100 我想知道这种情况可能会是什么原因造成的 Lika 回复: S32K314编程错误 补充一下,在我确认擦除/编程完成后我采取了下面步骤 set 0 to MCR[EHV] set 0 to MCR[PGM/ERS]
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RT1xxx ENET: Does Correction Counter reset when writing ATCOR to change the Wrap-Around value? Hi, I wonder if the Correction Counter (in the ENET peripheral) is reset upon a write of ATCOR. Or maybe it is reset only if the value in ATCOR is changed? best regards Max i.MXRT 102x i.MXRT 105x
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S32K314 programming error Hello When I tried to write data to the DFLASH using debug mode, it failed. Below is a rough outline of my code. write 0xFFFFF800 to 0x40268350 wtire 0x10000000 to PFCPGM_PEARR_L register write 0xFFFFFFFF to Program DATA0 set MCR[ERS] to 1 MCR[ERS] choose sector Set MCR[EHV] to 1 wait MCRS[DONE] be 1 check MCRS[PEG] set MCR[EHV] to 0 SETMCR[ERS]to 0 after erase 11 sectors wtire 0x10000000 to PFCPGM_PEARR_L register write 256 bit data to DATA0~DATA7 set MCR[PGM] to 1 set MCR[EHV] to 1 read MCRS register get 0x0000C100 But when I looped for the second time wtire 0x10000000 to PFCPGM_PEARR_L register write 256 bit data to DATA0~DATA7 set MCR[PGM] to 1 set MCR[EHV] to 1 read MCRS register get 0x00008100 I'd like to know what might be causing this situation. Lika 回复: S32K314编程错误 To add to that, after confirming that the erase/programming was complete, I took the following steps. set 0 to MCR[EHV] set 0 to MCR[PGM/ERS]
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RT1051: ENET IEEE1588 Timer Clock source Hi, In the RT1050 reference manual, I find the following: mastupristi_0-1789736651417.png I would like to know what the clock sources for the IEEE1588 timer can be. For example, can I choose a root clock derived from AUDIO_PLL? Which registers control the clock source of the IEEE1588 timer? best regards Max i.MXRT 105x
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RT1xxx ENET:写入 ATCOR 以更改循环值时,校正计数器是否会重置? 您好, 我想知道在写入 ATCOR 时,校正计数器(在 ENET 外设中)是否会重置。 或者,也许只有当 ATCOR 中的值发生变化时才会重置? 顺祝商祺! 最大值 i.MX RT102x i.MX RT105x
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RT1051:ENET IEEE1588 定时器时钟源 您好, 在 RT1050 参考 手册 中 , 我 发现了 以下内容 : mastupristi_0-1789736651417.png 我想知道IEEE1588定时器的时钟源有哪些。例如,我可以选择从 AUDIO_PLL 派生的根时钟吗? 哪些寄存器控制 IEEE1588 定时器的时钟源? 顺祝商祺! 最大值 i.MX RT105x
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PN7160 NXP-NCI MCUxpresso for VS Code Example Project for MCXA156 Introduction This document provides a guide on how to integrate the FRDM-MCXA156 as a host for the PN7160 using the examples provided in the “PN7160 NXP-NCI MCUXpresso Example Project” package. The hardware required to follow this guide is: FRDM-MCXA156 development board as host MCU. OM27160A1/OM27160B1 (PN7160 EVK) as the NFC controller. MCUxpresso for VS code extension Software setup. PN7160 NXP-NCI MCUXpresso Example Project version: 1.2 MCXN947 SDK version: 26.06 PN7160 version: 12.50.11. Hardware connections. When using OM27160B1 (SPI Host Interface): The FRDM-MCXA156 schematic document is available on this page. In the case of SPI connections, to use PN7160 directly with the Arduino headers a rework is needed for the FRDM because SDO(MOSI) and SS (Chip select) are not connected as default (as shown in the next figure). You should move R59 and R60 from pad 2 to pad 3 to enable these connections. Habib_MS_0-1781809327131.png Note: You can connect the SPI pins available in Mikro bus header with jumpers, but in this example, the signals are routed through the pins enabled by the rework configuration. Once clarified this, these are the pins used in this example. Name PORT I2C0_SDA P0_16 I2C0_SCL P0_17 LPSPI1_SDI P2_16 LPSPI1_SDO P2_13 LPSPI1_SCK P2_12 LPSPI1_SS P2_6 IRQ P1_15 VEN P1_14 REQ P3_16   Software Changes This section describes the software changes required to run an “NXP-NCI2.0” example with the MCXA156, which consists in a detection loop that displays in a terminal information (like UID, SAK, and Product Type for MIFARE product-based cards) about any tag detected by the PN7160. To begin the integration, we first need to import a hello_world project from the FRDM-MCXA156 SDK (v26.06.00) into MCUXpresso IDE for VS Code. For this purpose, download and install the FRDM-MCXA156 repository (version 26.06) using the extension available in the Quickstart panel by selecting Import Repository. For more information about this process, you can consult the corresponding guide. Importing NCI2.0 examples Download the “PN7160 NXP-NCI MCUXpresso Example Project” zip from the product page and extract in a known folder. This will be useful for later use.  Importing base project 1. In the Quick Start panel click on “Import Example from Repository” in VS code. Habib_MS_1-1781809359168.png 2. Select “FRDM-MCXA156” in board setting.   Habib_MS_1-1785802139304.png 3. In the template will search for the “hello_world” example, select Freestanding Applications, chose the location and click on “import”. Habib_MS_0-1785802110562.png Importing SDK drivers Once the project is added to the workspace we will need to add the required drivers, which are the SPI driver in case the OM27160B1HN is being used, or the I2C driver if the OM27160A1HN is being used. For this we need to add the following code in the prj.cfg file. Habib_MS_0-1781809845396.png Spoiler (Highlight to read) CONFIG_MCUX_COMPONENT_driver.lpi2c=y CONFIG_MCUX_COMPONENT_driver.lpspi=y CONFIG_MCUX_COMPONENT_driver.lpi2c=y CONFIG_MCUX_COMPONENT_driver.lpspi=y Add the example source code to the newly created MCXA156 project Delete the hello_world.c of the project files folder of the MCXA156 project. From the “NXP-NCI2.0_iMXRT1170_examples” extracted just drag and drop in the project files folder the following files and folders. Habib_MS_0-1781809900813.png Habib_MS_1-1781809927413.png When you drag and drop a file into VS code a window will appear asking whether you want to link the file or copy it. Please select “Copy files.” Habib_MS_2-1781809983781.png The project folder should look like this: Habib_MS_3-1781810001861.png After dragging and dropping all the files, the CMakeLists.txt file is automatically updated to include all the copied .c files. An example of this is shown below: Habib_MS_4-1781810063910.png However, .h files are not automatically linked, so they must be added manually. Please copy and paste the following includes into the CMakeLists.txt file: Habib_MS_5-1781810096008.png Spoiler (Highlight to read) mcux_add_include( BASE_PATH ${CMAKE_CURRENT_LIST_DIR} INCLUDES tool TML NfcLibrary/inc NfcLibrary/NdefLibrary/inc INCLUDES NfcLibrary/NxpNci20/inc . ) mcux_add_include( BASE_PATH ${CMAKE_CURRENT_LIST_DIR} INCLUDES tool TML NfcLibrary/inc NfcLibrary/NdefLibrary/inc INCLUDES NfcLibrary/NxpNci20/inc . ) Preprocessor Interface macro Depending on the interface to be used to communicate with the PN7160, a preprocessor macro must be defined in the CMakelist.txt BOARD_NXPNCI_INTERFACE_SPI (For using SPI with OM27160B1) BOARD_NXPNCI_INTERFACE_I2C (For using I2C with OM27160A1) Additionally, it is necessary to add the macro called REMOVE_P2P_SUPPORT. Please make sure that this Macro is included. Spoiler (Highlight to read) mcux_add_macro( CC "BOARD_NXPNCI_INTERFACE_I2C=1\ REMOVE_P2P_SUPPORT=1") mcux_add_macro( CC "BOARD_NXPNCI_INTERFACE_I2C=1\ REMOVE_P2P_SUPPORT=1") Note: The following sections are exemplified using the SPI interface (BOARD_NXPNCI_INTERFACE_SPI macro). After making the modifications described below, the interface used by the example can be changed simply by setting the macro to BOARD_NXPNCI_INTERFACE_I2C. Board definitions In the board.h file we will add the following definitions in order to refer to the different peripherals and clocks to be used, you can find this file in the following path: {PrjRootDirPath}\ frdmmcxa156\frdmmcxa156\board.h Habib_MS_1-1781810404448.png Spoiler (Highlight to read) #ifdef BOARD_NXPNCI_INTERFACE_I2C #define BOARD_NXPNCI_I2C_CLOCK (CLOCK_GetLpi2cClkFreq(0U)) #define BOARD_NXPNCI_I2C_INSTANCE (LPI2C0) #define BOARD_NXPNCI_I2C_BAUDRATE (100000) #define BOARD_NXPNCI_I2C_ADDR (0x28) #endif #ifdef BOARD_NXPNCI_INTERFACE_SPI #define BOARD_NXPNCI_SPI_CLOCK (CLOCK_GetLpspiClkFreq(1U)) #define BOARD_NXPNCI_SPI_INSTANCE (LPSPI1) #define BOARD_NXPNCI_SPI_BAUDRATE (400000) #endif #define BOARD_NXPNCI_IRQ_PORT (GPIO1) #define BOARD_NXPNCI_VEN_PORT (GPIO1) #define BOARD_NXPNCI_DWL_PORT (GPIO3) #define BOARD_NXPNCI_IRQ_PIN (15U) #define BOARD_NXPNCI_VEN_PIN (14U) #define BOARD_NXPNCI_DWL_PIN (16U) #ifdef BOARD_NXPNCI_INTERFACE_I2C #define BOARD_NXPNCI_I2C_CLOCK (CLOCK_GetLpi2cClkFreq(0U)) #define BOARD_NXPNCI_I2C_INSTANCE (LPI2C0) #define BOARD_NXPNCI_I2C_BAUDRATE (100000) #define BOARD_NXPNCI_I2C_ADDR (0x28) #endif #ifdef BOARD_NXPNCI_INTERFACE_SPI #define BOARD_NXPNCI_SPI_CLOCK (CLOCK_GetLpspiClkFreq(1U)) #define BOARD_NXPNCI_SPI_INSTANCE (LPSPI1) #define BOARD_NXPNCI_SPI_BAUDRATE (400000) #endif #define BOARD_NXPNCI_IRQ_PORT (GPIO1) #define BOARD_NXPNCI_VEN_PORT (GPIO1) #define BOARD_NXPNCI_DWL_PORT (GPIO3) #define BOARD_NXPNCI_IRQ_PIN (15U) #define BOARD_NXPNCI_VEN_PIN (14U) #define BOARD_NXPNCI_DWL_PIN (16U) Code modifications to the TML component In the source tml.c source file the following modifications are made, you can find this file in the following path: {{PrjRootDirPath }>frdmmcxa156_hello_world\TML Habib_MS_2-1781810455046.png Spoiler (Highlight to read) static Status tml_Reset(void) { /* Set DWL_REQ low for NCI protocol */ GPIO_PortClear(BOARD_NXPNCI_DWL_PORT, 1U << BOARD_NXPNCI_DWL_PIN); GPIO_PortClear(BOARD_NXPNCI_VEN_PORT, 1U << BOARD_NXPNCI_VEN_PIN); Sleep(10); GPIO_PortSet(BOARD_NXPNCI_VEN_PORT, 1U << BOARD_NXPNCI_VEN_PIN); Sleep(10); return SUCCESS; } static Status tml_Reset(void) { /* Set DWL_REQ low for NCI protocol */ GPIO_PortClear(BOARD_NXPNCI_DWL_PORT, 1U << BOARD_NXPNCI_DWL_PIN); GPIO_PortClear(BOARD_NXPNCI_VEN_PORT, 1U << BOARD_NXPNCI_VEN_PIN); Sleep(10); GPIO_PortSet(BOARD_NXPNCI_VEN_PORT, 1U << BOARD_NXPNCI_VEN_PIN); Sleep(10); return SUCCESS; } Habib_MS_3-1781810501153.png Spoiler (Highlight to read) static void INTF_INIT(void) { lpspi_master_config_t masterConfig; LPSPI_MasterGetDefaultConfig(&masterConfig); masterConfig.baudRate = BOARD_NXPNCI_SPI_BAUDRATE; masterConfig.whichPcs = (lpspi_which_pcs_t) kLPSPI_Pcs1; masterXfer.configFlags = kLPSPI_MasterPcs1 | kLPSPI_MasterPcsContinuous | kLPSPI_MasterByteSwap; LPSPI_MasterInit(BOARD_NXPNCI_SPI_INSTANCE, &masterConfig, BOARD_NXPNCI_SPI_CLOCK); } static void INTF_INIT(void) { lpspi_master_config_t masterConfig; LPSPI_MasterGetDefaultConfig(&masterConfig); masterConfig.baudRate = BOARD_NXPNCI_SPI_BAUDRATE; masterConfig.whichPcs = (lpspi_which_pcs_t) kLPSPI_Pcs1; masterXfer.configFlags = kLPSPI_MasterPcs1 | kLPSPI_MasterPcsContinuous | kLPSPI_MasterByteSwap; LPSPI_MasterInit(BOARD_NXPNCI_SPI_INSTANCE, &masterConfig, BOARD_NXPNCI_SPI_CLOCK); } Habib_MS_4-1781810544149.png Spoiler (Highlight to read) static Status tml_Init(void) { gpio_pin_config_t in_config = {kGPIO_DigitalInput, 0}; gpio_pin_config_t out_config = {kGPIO_DigitalOutput, 0}; GPIO_PinInit(BOARD_NXPNCI_IRQ_PORT, BOARD_NXPNCI_IRQ_PIN, &in_config); GPIO_PinInit(BOARD_NXPNCI_VEN_PORT, BOARD_NXPNCI_VEN_PIN, &out_config); GPIO_PinInit(BOARD_NXPNCI_DWL_PORT, BOARD_NXPNCI_DWL_PIN, &out_config); INTF_INIT(); return SUCCESS; } static Status tml_DeInit(void) { GPIO_PortClear(BOARD_NXPNCI_VEN_PORT, 1U << BOARD_NXPNCI_VEN_PIN); return SUCCESS; } static Status tml_Init(void) { gpio_pin_config_t in_config = {kGPIO_DigitalInput, 0}; gpio_pin_config_t out_config = {kGPIO_DigitalOutput, 0}; GPIO_PinInit(BOARD_NXPNCI_IRQ_PORT, BOARD_NXPNCI_IRQ_PIN, &in_config); GPIO_PinInit(BOARD_NXPNCI_VEN_PORT, BOARD_NXPNCI_VEN_PIN, &out_config); GPIO_PinInit(BOARD_NXPNCI_DWL_PORT, BOARD_NXPNCI_DWL_PIN, &out_config); INTF_INIT(); return SUCCESS; } static Status tml_DeInit(void) { GPIO_PortClear(BOARD_NXPNCI_VEN_PORT, 1U << BOARD_NXPNCI_VEN_PIN); return SUCCESS; } Code modifications for ports, pins and clocks initialization In the file “hardware_init.c” in the board folder of the project, write the following function as shown, in order to add port and clock peripheral initializations. Habib_MS_5-1781810589344.png Spoiler (Highlight to read) /* * Copyright 2024 NXP * * SPDX-License-Identifier: BSD-3-Clause */ /*${header:start}*/ #include "pin_mux.h" #include "fsl_clock.h" #include "fsl_reset.h" #include "board.h" #include /*${header:end}*/ /*${function:start}*/ void BOARD_InitHardware(void) { CLOCK_SetClockDiv(kCLOCK_DivLPI2C0, 1u); CLOCK_AttachClk(kFRO12M_to_LPI2C0); CLOCK_SetClockDiv(kCLOCK_DivLPSPI1, 1u); CLOCK_AttachClk(kFRO12M_to_LPSPI1); BOARD_InitPins(); BOARD_InitBootClocks(); BOARD_InitDebugConsole(); } /*${function:end}*/ /* * Copyright 2024 NXP * * SPDX-License-Identifier: BSD-3-Clause */ /*${header:start}*/ #include "pin_mux.h" #include "fsl_clock.h" #include "fsl_reset.h" #include "board.h" #include /*${header:end}*/ /*${function:start}*/ void BOARD_InitHardware(void) { CLOCK_SetClockDiv(kCLOCK_DivLPI2C0, 1u); CLOCK_AttachClk(kFRO12M_to_LPI2C0); CLOCK_SetClockDiv(kCLOCK_DivLPSPI1, 1u); CLOCK_AttachClk(kFRO12M_to_LPSPI1); BOARD_InitPins(); BOARD_InitBootClocks(); BOARD_InitDebugConsole(); } /*${function:end}*/ In the pin_mux.c file modifies the function called BOARD_InitPins(); accordingly, this file can be seen in the following path: {PrjRootDirPath}\ frdmmcxa156\hello_world \pin_mux.c Spoiler (Highlight to read) void BOARD_InitPins(void) { CLOCK_EnableClock(kCLOCK_GateGPIO1); /* GPIO3: Peripheral clock is enabled */ CLOCK_EnableClock(kCLOCK_GateGPIO3); /* PORT0: Peripheral clock is enabled */ CLOCK_EnableClock(kCLOCK_GatePORT0); CLOCK_EnableClock(kCLOCK_GatePORT1); CLOCK_EnableClock(kCLOCK_GatePORT2); CLOCK_EnableClock(kCLOCK_GatePORT3); /* GPIO1 peripheral is released from reset */ RESET_ReleasePeripheralReset(kGPIO1_RST_SHIFT_RSTn); /* GPIO3 peripheral is released from reset */ RESET_ReleasePeripheralReset(kGPIO3_RST_SHIFT_RSTn); RESET_ReleasePeripheralReset(kLPUART0_RST_SHIFT_RSTn); RESET_ReleasePeripheralReset(kPORT0_RST_SHIFT_RSTn); RESET_ReleasePeripheralReset(kLPSPI0_RST_SHIFT_RSTn); RESET_ReleasePeripheralReset(kPORT1_RST_SHIFT_RSTn); RESET_ReleasePeripheralReset(kLPSPI1_RST_SHIFT_RSTn); RESET_ReleasePeripheralReset(kPORT3_RST_SHIFT_RSTn); RESET_ReleasePeripheralReset(kPORT2_RST_SHIFT_RSTn); const port_pin_config_t port0_2_pin78_config = {/* Internal pull-up resistor is enabled */ kPORT_PullUp, /* Low internal pull resistor value is selected. */ kPORT_LowPullResistor, /* Fast slew rate is configured */ kPORT_FastSlewRate, /* Passive input filter is disabled */ kPORT_PassiveFilterDisable, /* Open drain output is disabled */ kPORT_OpenDrainDisable, /* Low drive strength is configured */ kPORT_LowDriveStrength, /* Normal drive strength is configured */ kPORT_NormalDriveStrength, /* Pin is configured as LPUART0_RXD */ kPORT_MuxAlt2, /* Digital input enabled */ kPORT_InputBufferEnable, /* Digital input is not inverted */ kPORT_InputNormal, /* Pin Control Register fields [15:0] are not locked */ kPORT_UnlockRegister}; /* PORT0_2 (pin 78) is configured as LPUART0_RXD */ PORT_SetPinConfig(PORT0, 2U, &port0_2_pin78_config); const port_pin_config_t port0_3_pin79_config = {/* Internal pull-up resistor is enabled */ kPORT_PullUp, /* Low internal pull resistor value is selected. */ kPORT_LowPullResistor, /* Fast slew rate is configured */ kPORT_FastSlewRate, /* Passive input filter is disabled */ kPORT_PassiveFilterDisable, /* Open drain output is disabled */ kPORT_OpenDrainDisable, /* Low drive strength is configured */ kPORT_LowDriveStrength, /* Normal drive strength is configured */ kPORT_NormalDriveStrength, /* Pin is configured as LPUART0_TXD */ kPORT_MuxAlt2, /* Digital input enabled */ kPORT_InputBufferEnable, /* Digital input is not inverted */ kPORT_InputNormal, /* Pin Control Register fields [15:0] are not locked */ kPORT_UnlockRegister}; /* PORT0_3 (pin 79) is configured as LPUART0_TXD */ PORT_SetPinConfig(PORT0, 3U, &port0_3_pin79_config); const port_pin_config_t port2_13_pin35_config = { kPORT_PullDisable, kPORT_LowPullResistor, kPORT_FastSlewRate, kPORT_PassiveFilterDisable, kPORT_OpenDrainDisable, kPORT_LowDriveStrength, kPORT_NormalDriveStrength, /* Pin is configured as LPSPI1_SDO */ kPORT_MuxAlt2, kPORT_InputBufferEnable, kPORT_InputNormal, kPORT_UnlockRegister}; PORT_SetPinConfig(PORT2, 13U, &port2_13_pin35_config); const port_pin_config_t port2_12_pin34_config = { kPORT_PullDisable, kPORT_LowPullResistor, kPORT_FastSlewRate, kPORT_PassiveFilterDisable, kPORT_OpenDrainDisable, kPORT_LowDriveStrength, kPORT_NormalDriveStrength, /* Pin is configured as LPSPI1_SCK */ kPORT_MuxAlt2, kPORT_InputBufferEnable, kPORT_InputNormal, kPORT_UnlockRegister}; PORT_SetPinConfig(PORT2, 12U, &port2_12_pin34_config); const port_pin_config_t port2_16_pin37_config = { kPORT_PullDisable, kPORT_LowPullResistor, kPORT_FastSlewRate, kPORT_PassiveFilterDisable, kPORT_OpenDrainDisable, kPORT_LowDriveStrength, kPORT_NormalDriveStrength, /* Pin is configured as LPSPI1_SDI */ kPORT_MuxAlt2, kPORT_InputBufferEnable, kPORT_InputNormal, kPORT_UnlockRegister}; PORT_SetPinConfig(PORT2, 16U, &port2_16_pin37_config); const port_pin_config_t port2_6_pin28_config = { kPORT_PullDisable, kPORT_LowPullResistor, kPORT_FastSlewRate, kPORT_PassiveFilterDisable, kPORT_OpenDrainDisable, kPORT_LowDriveStrength, kPORT_NormalDriveStrength, /* Pin is configured as LPSPI1_PCS0 */ kPORT_MuxAlt2, kPORT_InputBufferEnable, kPORT_InputNormal, kPORT_UnlockRegister}; PORT_SetPinConfig(PORT2, 6U, &port2_6_pin28_config); const port_pin_config_t port1_15_pin8_config = { kPORT_PullDisable, kPORT_LowPullResistor, kPORT_FastSlewRate, kPORT_PassiveFilterDisable, kPORT_OpenDrainDisable, kPORT_LowDriveStrength, kPORT_NormalDriveStrength, /* Pin is configured as GPIO1 15 */ kPORT_MuxAlt0, kPORT_InputBufferEnable, kPORT_InputNormal, kPORT_UnlockRegister}; PORT_SetPinConfig(PORT1, 15U, &port1_15_pin8_config); const port_pin_config_t port1_14_pin7_config = { kPORT_PullUp, kPORT_LowPullResistor, kPORT_FastSlewRate, kPORT_PassiveFilterDisable, kPORT_OpenDrainDisable, kPORT_LowDriveStrength, kPORT_NormalDriveStrength, /* Pin is configured as GPIO1 14 */ kPORT_MuxAlt0, kPORT_InputBufferEnable, kPORT_InputNormal, kPORT_UnlockRegister}; PORT_SetPinConfig(PORT1, 14U, &port1_14_pin7_config); const port_pin_config_t port3_16_pin59_config = { kPORT_PullUp, kPORT_LowPullResistor, kPORT_FastSlewRate, kPORT_PassiveFilterDisable, kPORT_OpenDrainDisable, kPORT_LowDriveStrength, kPORT_NormalDriveStrength, /* Pin is configured as GPIO3 16 */ kPORT_MuxAlt0, kPORT_InputBufferEnable, kPORT_InputNormal, kPORT_UnlockRegister}; PORT_SetPinConfig(PORT3, 16U, &port3_16_pin59_config); const port_pin_config_t port0_16_pin83_config = { kPORT_PullDisable, kPORT_LowPullResistor, kPORT_FastSlewRate, kPORT_PassiveFilterDisable, kPORT_OpenDrainDisable, kPORT_LowDriveStrength, kPORT_NormalDriveStrength, /* Pin is configured as LPI2C0 SDA */ kPORT_MuxAlt2, kPORT_InputBufferEnable, kPORT_InputNormal, kPORT_UnlockRegister}; PORT_SetPinConfig(PORT0, 16U, &port0_16_pin83_config); const port_pin_config_t port0_17_pin84_config = { kPORT_PullDisable, kPORT_LowPullResistor, kPORT_FastSlewRate, kPORT_PassiveFilterDisable, kPORT_OpenDrainDisable, kPORT_LowDriveStrength, kPORT_NormalDriveStrength, /* Pin is configured as LPI2C0 SCL */ kPORT_MuxAlt2, kPORT_InputBufferEnable, kPORT_InputNormal, kPORT_UnlockRegister}; PORT_SetPinConfig(PORT0, 17U, &port0_17_pin84_config); } void BOARD_InitPins(void) { CLOCK_EnableClock(kCLOCK_GateGPIO1); /* GPIO3: Peripheral clock is enabled */ CLOCK_EnableClock(kCLOCK_GateGPIO3); /* PORT0: Peripheral clock is enabled */ CLOCK_EnableClock(kCLOCK_GatePORT0); CLOCK_EnableClock(kCLOCK_GatePORT1); CLOCK_EnableClock(kCLOCK_GatePORT2); CLOCK_EnableClock(kCLOCK_GatePORT3); /* GPIO1 peripheral is released from reset */ RESET_ReleasePeripheralReset(kGPIO1_RST_SHIFT_RSTn); /* GPIO3 peripheral is released from reset */ RESET_ReleasePeripheralReset(kGPIO3_RST_SHIFT_RSTn); RESET_ReleasePeripheralReset(kLPUART0_RST_SHIFT_RSTn); RESET_ReleasePeripheralReset(kPORT0_RST_SHIFT_RSTn); RESET_ReleasePeripheralReset(kLPSPI0_RST_SHIFT_RSTn); RESET_ReleasePeripheralReset(kPORT1_RST_SHIFT_RSTn); RESET_ReleasePeripheralReset(kLPSPI1_RST_SHIFT_RSTn); RESET_ReleasePeripheralReset(kPORT3_RST_SHIFT_RSTn); RESET_ReleasePeripheralReset(kPORT2_RST_SHIFT_RSTn); const port_pin_config_t port0_2_pin78_config = {/* Internal pull-up resistor is enabled */ kPORT_PullUp, /* Low internal pull resistor value is selected. */ kPORT_LowPullResistor, /* Fast slew rate is configured */ kPORT_FastSlewRate, /* Passive input filter is disabled */ kPORT_PassiveFilterDisable, /* Open drain output is disabled */ kPORT_OpenDrainDisable, /* Low drive strength is configured */ kPORT_LowDriveStrength, /* Normal drive strength is configured */ kPORT_NormalDriveStrength, /* Pin is configured as LPUART0_RXD */ kPORT_MuxAlt2, /* Digital input enabled */ kPORT_InputBufferEnable, /* Digital input is not inverted */ kPORT_InputNormal, /* Pin Control Register fields [15:0] are not locked */ kPORT_UnlockRegister}; /* PORT0_2 (pin 78) is configured as LPUART0_RXD */ PORT_SetPinConfig(PORT0, 2U, &port0_2_pin78_config); const port_pin_config_t port0_3_pin79_config = {/* Internal pull-up resistor is enabled */ kPORT_PullUp, /* Low internal pull resistor value is selected. */ kPORT_LowPullResistor, /* Fast slew rate is configured */ kPORT_FastSlewRate, /* Passive input filter is disabled */ kPORT_PassiveFilterDisable, /* Open drain output is disabled */ kPORT_OpenDrainDisable, /* Low drive strength is configured */ kPORT_LowDriveStrength, /* Normal drive strength is configured */ kPORT_NormalDriveStrength, /* Pin is configured as LPUART0_TXD */ kPORT_MuxAlt2, /* Digital input enabled */ kPORT_InputBufferEnable, /* Digital input is not inverted */ kPORT_InputNormal, /* Pin Control Register fields [15:0] are not locked */ kPORT_UnlockRegister}; /* PORT0_3 (pin 79) is configured as LPUART0_TXD */ PORT_SetPinConfig(PORT0, 3U, &port0_3_pin79_config); const port_pin_config_t port2_13_pin35_config = { kPORT_PullDisable, kPORT_LowPullResistor, kPORT_FastSlewRate, kPORT_PassiveFilterDisable, kPORT_OpenDrainDisable, kPORT_LowDriveStrength, kPORT_NormalDriveStrength, /* Pin is configured as LPSPI1_SDO */ kPORT_MuxAlt2, kPORT_InputBufferEnable, kPORT_InputNormal, kPORT_UnlockRegister}; PORT_SetPinConfig(PORT2, 13U, &port2_13_pin35_config); const port_pin_config_t port2_12_pin34_config = { kPORT_PullDisable, kPORT_LowPullResistor, kPORT_FastSlewRate, kPORT_PassiveFilterDisable, kPORT_OpenDrainDisable, kPORT_LowDriveStrength, kPORT_NormalDriveStrength, /* Pin is configured as LPSPI1_SCK */ kPORT_MuxAlt2, kPORT_InputBufferEnable, kPORT_InputNormal, kPORT_UnlockRegister}; PORT_SetPinConfig(PORT2, 12U, &port2_12_pin34_config); const port_pin_config_t port2_16_pin37_config = { kPORT_PullDisable, kPORT_LowPullResistor, kPORT_FastSlewRate, kPORT_PassiveFilterDisable, kPORT_OpenDrainDisable, kPORT_LowDriveStrength, kPORT_NormalDriveStrength, /* Pin is configured as LPSPI1_SDI */ kPORT_MuxAlt2, kPORT_InputBufferEnable, kPORT_InputNormal, kPORT_UnlockRegister}; PORT_SetPinConfig(PORT2, 16U, &port2_16_pin37_config); const port_pin_config_t port2_6_pin28_config = { kPORT_PullDisable, kPORT_LowPullResistor, kPORT_FastSlewRate, kPORT_PassiveFilterDisable, kPORT_OpenDrainDisable, kPORT_LowDriveStrength, kPORT_NormalDriveStrength, /* Pin is configured as LPSPI1_PCS0 */ kPORT_MuxAlt2, kPORT_InputBufferEnable, kPORT_InputNormal, kPORT_UnlockRegister}; PORT_SetPinConfig(PORT2, 6U, &port2_6_pin28_config); const port_pin_config_t port1_15_pin8_config = { kPORT_PullDisable, kPORT_LowPullResistor, kPORT_FastSlewRate, kPORT_PassiveFilterDisable, kPORT_OpenDrainDisable, kPORT_LowDriveStrength, kPORT_NormalDriveStrength, /* Pin is configured as GPIO1 15 */ kPORT_MuxAlt0, kPORT_InputBufferEnable, kPORT_InputNormal, kPORT_UnlockRegister}; PORT_SetPinConfig(PORT1, 15U, &port1_15_pin8_config); const port_pin_config_t port1_14_pin7_config = { kPORT_PullUp, kPORT_LowPullResistor, kPORT_FastSlewRate, kPORT_PassiveFilterDisable, kPORT_OpenDrainDisable, kPORT_LowDriveStrength, kPORT_NormalDriveStrength, /* Pin is configured as GPIO1 14 */ kPORT_MuxAlt0, kPORT_InputBufferEnable, kPORT_InputNormal, kPORT_UnlockRegister}; PORT_SetPinConfig(PORT1, 14U, &port1_14_pin7_config); const port_pin_config_t port3_16_pin59_config = { kPORT_PullUp, kPORT_LowPullResistor, kPORT_FastSlewRate, kPORT_PassiveFilterDisable, kPORT_OpenDrainDisable, kPORT_LowDriveStrength, kPORT_NormalDriveStrength, /* Pin is configured as GPIO3 16 */ kPORT_MuxAlt0, kPORT_InputBufferEnable, kPORT_InputNormal, kPORT_UnlockRegister}; PORT_SetPinConfig(PORT3, 16U, &port3_16_pin59_config); const port_pin_config_t port0_16_pin83_config = { kPORT_PullDisable, kPORT_LowPullResistor, kPORT_FastSlewRate, kPORT_PassiveFilterDisable, kPORT_OpenDrainDisable, kPORT_LowDriveStrength, kPORT_NormalDriveStrength, /* Pin is configured as LPI2C0 SDA */ kPORT_MuxAlt2, kPORT_InputBufferEnable, kPORT_InputNormal, kPORT_UnlockRegister}; PORT_SetPinConfig(PORT0, 16U, &port0_16_pin83_config); const port_pin_config_t port0_17_pin84_config = { kPORT_PullDisable, kPORT_LowPullResistor, kPORT_FastSlewRate, kPORT_PassiveFilterDisable, kPORT_OpenDrainDisable, kPORT_LowDriveStrength, kPORT_NormalDriveStrength, /* Pin is configured as LPI2C0 SCL */ kPORT_MuxAlt2, kPORT_InputBufferEnable, kPORT_InputNormal, kPORT_UnlockRegister}; PORT_SetPinConfig(PORT0, 17U, &port0_17_pin84_config); } Configure the main.c as follows: Habib_MS_0-1781813861103.png Spoiler (Highlight to read) #include #include #include "board.h" #include "app.h" #include "pin_mux.h" #include "fsl_debug_console.h" extern void nfc_example (void); int main(void) { BOARD_InitHardware(); #ifdef BOARD_NXPNCI_INTERFACE_I2C PRINTF("\nRunning the NXP-NCI2.0 example (I2C interface)\n"); #else PRINTF("\nRunning the NXP-NCI2.0 example (SPI interface)\n"); #endif nfc_example(); } #include #include #include "board.h" #include "app.h" #include "pin_mux.h" #include "fsl_debug_console.h" extern void nfc_example (void); int main(void) { BOARD_InitHardware(); #ifdef BOARD_NXPNCI_INTERFACE_I2C PRINTF("\nRunning the NXP-NCI2.0 example (I2C interface)\n"); #else PRINTF("\nRunning the NXP-NCI2.0 example (SPI interface)\n"); #endif nfc_example(); } Building and Debugging the example For building the example, please click on this button and if you followed this guide accordingly the project should compile without errors: Habib_MS_1-1781813991676.png Habib_MS_2-1781813999778.png Open a serial terminal such as Teraterm with the following settings: Habib_MS_3-1781814017721.png  Start a debug session by clicking this button: Habib_MS_4-1781814064724.png Once running, the example should look as follows: Habib_MS_5-1781814084057.png  When tapping a card on the antenna, the card information will be shown: Habib_MS_6-1781814110924.png NFC Controller Solutions
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2026年美国领先的白标SEO专家 将客户的 SEO 工作交给外部合作伙伴,只有当该合作伙伴确实具备相应的技术实力时,才能奏效。广告公司需要的不仅仅是供应商,而是了解抓取预算、结构化数据、内容策略,以及日益重要的如何针对人工智能驱动的搜索进行优化的白标 SEO 专家,而不仅仅是承诺排名却没有明确方法论的公司。 本指南着眼于 2026 年为美国机构提供服务的领先白标 SEO 专家,特别评估他们的技术和战略能力的深度,而不仅仅是他们网站上列出的服务范围。 2026 年领先的白标 SEO 专家 1. 阿拉伯搜索引擎优化 Arab SEO 团队在技术 SEO、本地 SEO、电子商务 SEO、国际 SEO、AI SEO 和生成式引擎优化 (GEO) 方面拥有专家级的深度。真正的专家与普通供应商的区别在于方法论——Arab SEO 的多语言和人工智能驱动搜索方法建立在结构化、可重复的流程之上,而不是一次性的策略,这对于一家代理机构同时信任拥有数十个不同客户账户的合作伙伴来说至关重要。 2. SEO 通告 SEO Circular 的专家们专注于企业级技术 SEO——这类大型的、拥有数千页的网站,一个被忽视的抓取问题就可能抑制整个域的排名。其团队在国际和多语言 SEO 方面的经验也使其成为与跨国经营的客户合作的代理机构的有力选择。 3. 三重思维 Triple Minds 的团队以代理服务为核心,这意味着其专家完全专注于执行质量,而不是销售或客户获取——这在交付一致性方面是一个结构性优势。 4. 半化 Semify 的专家拥有多年构建可定制本地 SEO 活动的经验,其流程专门围绕帮助小型机构逐步扩展其 SEO 服务而构建。 5. SEOReseller SEOReseller 团队专注于提供全方位管理的服务,处理完整的 SEO 流程——技术、内容和链接——日常执行中几乎不需要代理机构的参与。 6. DashClicks DashClicks 将其 SEO 专家与专为报告和客户管理而构建的软件平台相结合,使代理机构能够通过自动化仪表板了解专家的工作情况。 7. 霍斯 HOTH 的专家们在完善的文档记录和标准化的方案框架内工作,使得机构能够轻松理解他们的流程,并向客户解释。 8. 增强能力 Boostability 团队在为大量小型客户提供一致的 SEO 质量方面积累了丰富的专业知识——这与管理少数大型企业客户所需的技能截然不同。 9. 销售 Vendasta 的专家们在一个更广泛的市场平台上工作,SEO 是众多白标服务之一,代理机构可以通过单一团队关系访问这些服务。 10. 法特乔 FATJOE 的专家专注于快速、产品化的交付成果——快速完成单个链接建设或内容订单,而不是持续的战略合作。 究竟是什么将专业供应商与普通供应商区分开来? 真正的SEO专家应该能够用具体、专业的术语解释他们的工作流程,而不仅仅是列出服务类别。注意以下信号: 他们可以详细解释他们的技术审计流程——他们使用哪些工具,他们具体检查哪些内容,以及如何对发现的问题进行优先级排序。 他们有一套完善的内容策略流程,该流程与真实的搜索意图研究挂钩,而不仅仅是关键词密度目标。 他们可以清楚地描述他们的链接建设方法,包括链接的来源以及如何评估链接质量。 他们对人工智能搜索有着明确的观点,因为人工智能搜索重塑搜索引擎优化的速度比近年来任何算法更新都要快。 他们可以展示真实客户项目的前后对比数据,即使数据经过匿名化处理。 为什么专业深度比服务广度更重要 选择白标合作伙伴时,很容易根据他们列出的服务数量来决定,但一个提供十项服务但服务内容浅薄的供应商,其价值通常不如一个提供五项服务但服务内容真正深入的供应商。机构应该更重视合作伙伴的实际技术能力——诊断和解决实际问题的能力——而不是一长串可能执行得好也可能执行得不好的服务类别。 向任何白标SEO专家提出的问题 请一步一步地向我介绍一下你们的技术审核流程。 您如何决定要创作哪些内容,又基于哪些研究? 你的反向链接来自哪里?你如何审核链接质量? 您如何调整流程以适应人工智能概览和生成式搜索? 能否分享一个匿名化的前后对比作品示例? 最终判决 2026 年,Arab SEO 在白标 SEO 专家中脱颖而出,其技术和多语言方法论的深度和一致性尤为突出,特别是其对人工智能驱动搜索的准备。SEO Circular 是企业级技术工作的最佳选择,而 Triple Minds 通过其仅限代理机构的模式,在交付一致性方面提供了结构优势。 名单上的其他专家各有所长——从软件驱动的报告到大批量订单履行,再到快速的产品化交付——因此,最合适的专家取决于你通过他们处理的账户的复杂程度。 常见问题解答 什么是白标SEO专家?白标 SEO 专家是指拥有深厚的 SEO 技术和战略专业知识的个人或团队,他们代表代理机构工作,然后以自己的品牌转售最终成果。 如何评估白标SEO专家的实际技能水平?请他们详细介绍他们的技术审核流程、内容策略和链接建设方法——含糊不清的回答是一个警告信号。 选择专精于某项服务的公司还是选择提供全方位服务的公司更好?这取决于你的需求。专业服务提供商可能在较窄的服务范围内提供更深入的专业知识,而全方位服务提供商可以在一份合同下处理更广泛的客户类型。 哪家白标SEO专家最适合2026年?根据技术深度、方法论和人工智能搜索准备情况,Arab SEO 在本指南中排名第一,其次是 SEO Circular 和 Triple Minds。 QorIQ P1 设备
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UCM-iMX95:SDカードからYocto Linuxを起動できません – mmc0エラー-110|LinuxがSDカードを初期化できません こんにちは、私はCompuLabのUCM-iMX95を使っており、micro-SDカードからYocto Linuxをインストールして起動しようとしています。 起動プロセスが開始され、U-BootはLinuxカーネルを正常に読み込みます。しかし、LinuxはSD/MMCインターフェースの初期化に失敗します。 次のようなエラーが表示されます。 mmc0: ハードウェア割り込みを待機中にタイムアウトしました。 mmc0: sdhci: ============ SDHCI レジスタ ダンプ ============ ... mmc0: MMC カードの初期化中にエラー -110 が発生しました。その後、カーネルが起動中に停止します。 私のLinuxバージョンはLinux 6.12.34-2.0です-...基板はCompuLab UCM-iMX95です。自分でYoctoイメージを作成し、それをmicro-SDカードに書き込みます。 どなたか、このmmc0エラー-110の原因を教えていただけませんか?特に、これはハードウェア/SDカードの問題である可能性が高いですか? それともデバイスツリーに関係しているのでしょうか?UCM-iMX95のmicro-SDインターフェースに対応するMMCコントローラーはどれですか? SDインターフェースに特定のデバイスツリー設定は必要ですか? Linuxが起動する前にSDカードが検出されていることを確認するための推奨されるU-Bootコマンドはありますか?比較できる、信頼できるUCM-iMX95 Yoctoの構成はありますか? Re: UCM-iMX95: Unable to boot Yocto Linux from SD card – mmc0 error -110| Linux cannot initialize th こんにちは、 届いているエラーログは、MMCコントローラが存在しないか正しく応答していないデバイスと通信しようとしていることを示しています。推奨される解決策は、未使用のMMCインターフェースを無効にするか、DT Youの設定を修正することです。 当社のEVKリファレンスデザインデバイスツリーは、以下の構成を使用しています。 mmc0 usdhc1 eMMC mmc1 usdhc2 SD card 当社のデバイスツリーを参考にしてください: https://github.com/nxp-imx/linux-imx/blob/lf-6.18.y/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts よろしくお願いいたします。
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PIC CLB 上的 Eureka 某些 PIC MCU(例如 pic16f13145 系列)具有类似 FPGA 的可编程逻辑,称为可配置逻辑块。 我使用的 pic16f13115 有 32 个单元,每个单元都有一个 4 输入查找表和一个 D 触发器。 为了学习如何使用这些工具,今天我实现了对 6 个 LED 的 Charlieplexing 的 PWM 亮度控制支持,并进行了模拟。我使用 Verilog 来定义电路,而不是使用逻辑 CAD 画布。 我差不多有一半的时间都在用头撞墙。我慢慢地把 Verilog 代码写对了,让它能够综合(构建),然后让它能够仿真。 CLB 编程逻辑即使在 CPU 休眠状态下也能正常工作,这很棒。它非常适合功能安全至关重要的应用。例如,可用于实现复杂的触发信号逻辑。CLB 逻辑与外围输入输出的连接方式非常灵活。它比PIC单片机中一直使用的笨重的CLC可编程逻辑电路灵活得多。 概述 Re: Eureka on PIC CLB 这真是对 PIC16F13115 的 CLB 的一种非常有趣的用法!使用 Verilog 实现 6 个 LED 的 Charlieplexing 设置并配合 PWM,听起来像是学习工作流程的好方法,而且在 CPU 休眠时逻辑电路也能继续运行,这为低功耗和功能安全关键型设计开辟了一些令人印象深刻的可能性。 Re: Eureka on PIC CLB 你好, 看来该设备属于另一家制造商。 请问您能否协助我们联系贵公司制造商? 如果您有兴趣更换为带有可编程逻辑单元 (PLC) 的 NXP 设备,可以参考 LPC804。 LPC804 可编程逻辑单元 (PLU) 顺祝商祺!
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i.MX8QXP – Prevent normal boot after interrupted USB flashing on Yocto Scarthgap with A/B partitions Hi NXP Team, The installed UUU executable reports: libuuu_1.5.21-0-g1f42172 We use: sudo uuu -b emmc_all ~/Downloads/flash.bin *.wic The built-in emmc_all script writes the complete .wic image using: FB: flash -raw2sparse all _image It then writes the bootloader, configures eMMC boot selection, and finishes with FB: done. The script contains no explicit persistent flash-in-progress completion metadata handling or readback hash verification step. If flashing is interrupted during the .wic write, the cluster can subsequently boot and display the updated HMI. We suspect that an existing usable bootloader and sufficient written boot,rootfs content permit this, but the selected slot and completeness of its contents are not yet confirmed. Please advise how to add a power-loss-tolerant completion check that blocks normal boot from both slots after interrupted factory flashing, while preserving USB recovery. The metadata must remain valid independently of the full .wic write and bootloader update. Re: i.MX8QXP – Prevent normal boot after interrupted USB flashing on Yocto Scarthgap with A/B partit Hello,  An official solution is not implemented but you can customize the uuu script, the built-in emmc_all flow is simply a UUU script based on Fastboot and U-Boot commands, and it can be modified or replaced by a custom uuu.auto file. U-Boot commands can also be executed through FB: ucmd. This means you should add custom steps such as setting a "flash in progress" flag before programming and clearing it only after verification succeeds.  U-Boot Boot Count / Boot Limit The U-Boot tree includes support for: CONFIG_BOOTCOUNT_LIMIT bootcount bootlimit altbootcmd CONFIG_BOOTCOUNT_FS When bootcount exceeds bootlimit, U-Boot executes altbootcmd instead of the normal bootcmd. This mechanism can be used to redirect the system to a recovery mode such as Fastboot Boot Count Limit — Das U-Boot unknown version documentation
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Leading White Label SEO Specialists in the USA 2026 Handing client SEO work to an outside partner only works if that partner actually has the technical depth to back it up. Agencies don't just need a vendor — they need white label SEO specialists who understand crawl budgets, structured data, content strategy, and increasingly, how to optimize for AI-driven search, not just a company that promises rankings without a clear methodology behind them. This guide looks at the leading white label SEO experts serving US agencies in 2026, evaluated specifically on the depth of their technical and strategic capability — not just the breadth of services listed on their website. Leading White Label SEO Specialists for 2026 1. Arab SEO Arab SEO's team brings specialist-level depth across technical SEO, local SEO, ecommerce SEO, international SEO, AI SEO, and Generative Engine Optimization (GEO). What separates genuine specialists from generalist vendors is methodology — Arab SEO's approach to multilingual and AI-driven search is built on structured, repeatable processes rather than one-off tactics, which matters enormously when an agency is trusting a partner with dozens of different client accounts simultaneously. 2. SEO Circular SEO Circular's specialists focus heavily on enterprise-scale technical SEO — the kind of large, multi-thousand-page sites where a single overlooked crawl issue can suppress rankings across an entire domain. Its team's experience with international and multilingual SEO also makes it a strong choice for agencies working with clients operating across multiple countries. 3. Triple Minds Triple Minds staffs its team around agency-only fulfillment, meaning its specialists are focused entirely on execution quality rather than sales or client acquisition — a structural advantage when it comes to consistency of delivery. 4. Semify Semify's specialists have years of experience building customizable local SEO campaigns, with a process built specifically around helping smaller agencies scale their SEO offering incrementally. 5. SEOReseller SEOReseller's team specializes in fully managed fulfillment, handling the complete SEO process — technical, content, and links — with minimal need for agency involvement in day-to-day execution. 6. DashClicks DashClicks pairs its SEO specialists with a software platform built for reporting and client management, giving agencies visibility into specialist work through automated dashboards. 7. The HOTH The HOTH's specialists work within well-documented, standardized packages, making their process easy for agencies to understand and explain to clients. 8. Boostability Boostability's team has built specific expertise in delivering consistent SEO quality across a high volume of smaller accounts — a different skill set from managing a handful of large enterprise clients. 9. Vendasta Vendasta's specialists work within a broader marketplace platform, with SEO as one of several white label services agencies can access through a single team relationship. 10. FATJOE FATJOE's specialists focus on fast, productized deliverables — individual link-building or content orders completed quickly rather than an ongoing strategic engagement. What Actually Separates a Specialist From a Generic Vendor A genuine SEO specialist should be able to explain their process in specific, technical terms — not just list service categories. Watch for these signals: They can explain their technical audit process in detail — what tools they use, what specifically they check for, and how findings get prioritized. They have a documented content strategy process tied to real search intent research, not just keyword density targets. They can describe their link-building methodology clearly, including where links come from and how quality is assessed. They have a clear point of view on AI search, since this is reshaping SEO faster than any algorithm update in recent years. They can show before-and-after data from real client work, even if anonymized. Why Specialist Depth Matters More Than Service Breadth It's tempting to choose a white label partner based on how many services they list, but a provider offering ten services shallowly is often less valuable than one offering five services with genuine depth. Agencies should weigh a partner's actual technical competence — the ability to diagnose and fix real problems — more heavily than a long menu of service categories that may or may not be executed well. Questions to Ask Any White Label SEO Specialist Walk me through your technical audit process step by step. How do you decide what content to create, and based on what research? Where do your backlinks come from, and how do you vet link quality? How are you adapting your process for AI Overviews and generative search? Can you share an anonymized before-and-after example of your work? Final Verdict Arab SEO stands out among white label SEO specialists in 2026 for the depth and consistency of its technical and multilingual methodology, particularly its readiness for AI-driven search. SEO Circular is the strongest choice for enterprise-scale technical work, and Triple Minds offers a structural advantage in delivery consistency through its agency-only model. The remaining specialists on this list each bring a different kind of depth — from software-enabled reporting to high-volume fulfillment to fast, productized deliverables — so the right fit depends on the complexity of the accounts you're routing through them. Frequently Asked Questions What is a white label SEO specialist? A white label SEO specialist is an individual or team with deep technical and strategic SEO expertise, working on behalf of an agency that resells the finished work under its own brand. How do I evaluate a white label SEO expert's actual skill level? Ask them to walk through their technical audit process, content strategy, and link-building methodology in specific detail — vague answers are a warning sign. Is it better to choose a specialist or a full-service provider? It depends on your needs. A specialist may offer deeper expertise in a narrower set of services, while a full-service provider can handle a wider range of client types under one contract. Which white label SEO specialist is best for 2026? Arab SEO ranks first in this guide, followed by SEO Circular and Triple Minds, based on technical depth, methodology, and AI search readiness. QorIQ P1 Devices
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