MKL02Z32VFK4 PTB2 alternative(2) Rxd Hi, just want to know if anyone came across the same problem as I have with Rx pin PTB2. The thing is that Txd is sending correctly at 115200b(that's verified) but when receiving it it's completely crap but defined crap(like when the baudrate is extremely wrong). I have also verified this by connecting a terminal prog(rxd) to listen to the message, and the message is ok at 115200b but UART is messing it up. If I send 'O','K',cr,lf the message in the rx buffer says 202(dec),106(dec),194(dec). The status flag indicate overrun and frame error all the time. The rx is interrupted, not the tx. Any ideas ? Cheers Claes Kinetis L Series MCUs Re: MKL02Z32VFK4 PTB2 alternative(2) Rxd Hello again @claeskjellstrom , Regarding your question, I understand that you want to modify the trim register that feeds the module, through the Jlink. However, as the following post says, Jlink doesn't support this feature: https://community.nxp.com/t5/Kinetis-Design-Studio/trimming-internal-oscillator/td-p/383412. If you need more information about the trim register, you can consult the reference manual for the chapter 21 called "Multipurpose Clock Generator (MCG)" in the register "MCG Control 3 Register (MCG_C3)" as well as "MCG Control 4 Register (MCG_C4)". BR Habib Re: MKL02Z32VFK4 PTB2 alternative(2) Rxd Hi, It turns out that FLL clock was out of tune, so funny thing was that Tx was sending correct but Rx couldn't receive correct, I had to switch clock to MCGIRCLK instead and now it's working. I would like to know if there is any possibility to trim oscillator through Segger J-link. /Claes Re: MKL02Z32VFK4 PTB2 alternative(2) Rxd Hello @claeskjellstrom , Can you give me more information about how you configured the peripheral? for example: - 115200 baud rate - 8 data bits - No parity - One stop bit - No flow control. For the moment, you can check an example of SDK (version 3.2) called "hello World", in this example, they use UART 0 for communicate at terminal. BR Habib

S32K324 Lpuart_lin Master Continually Returning Status "LPUART_LIN_IP_STATUS_TX_BUSY" Hi, I am using the S32K324 in a project, and am running into issues using the Lpuart_lin driver. Executing the function "Lpuart_Lin_Ip_SendFrame" returns "LPUART_LIN_IP_STATUS_SUCCESS", however when polling the LIN instance's status after it returns "LPUART_LIN_IP_STATUS_TX_BUSY". All subsequent calls to "Lpuart_Lin_Ip_SendFrame" return a fail. I checked the RX and TX lines going into my LIN transcoder, as well as the LIN output and I can see a 650 microsecond low pulse followed by nothing. There is no data sent apart from this break, which is seen on all 3 lines. Any ideas as to what could be causing the issue? I have attached the file containing the Init and Send functions I have created. Thanks! EDIT: Wanted to add, the LIN instance has a "CurrentNodeState" of "LPUART_LIN_IP_NODE_STATE_SEND_BREAK_FIELD". Re: S32K324 Lpuart_lin Master Continually Returning Status "LPUART_LIN_IP_STATUS_TX_BUSY" hello @PetrS  I have encountered the same problem now, when MCU sends as host, LPUART_LIN_IP_STATUS_TX_BUSY, and the LIN instance has a "CurrentNodeState" of "LPUART_LIN_IP_NODE_STATE_SEND_BREAK_FIELD". But now the api for rerouting interrupts seems to have been removed, leaving only the IntCtrl_Ip_Init function. I can't find another solution, please tell me if there is another way to check my error. Re: S32K324 Lpuart_lin Master Continually Returning Status "LPUART_LIN_IP_STATUS_TX_BUSY" Hi Petr, Thanks for the response, I had already added the interrupt handler to IntCtrl_Ip. The issue turned out to be, I was initializing the interrupt and configuring the interrupt routing after initializing the LIN. Now that I am initializing the interrupt before the LIN I am successfully sending LIN frames. Thanks! Re: S32K324 Lpuart_lin Master Continually Returning Status "LPUART_LIN_IP_STATUS_TX_BUSY" Hi, it looks like driver interrupt is not called to next frame bytes are not processed. Try to check that. You can also refer to RTD demo examples. BR, Petr

LLCモードではジッターノイズが発生しますか? 数十年前、私はオスラムのスペクトルランプ用の高周波安定化電源を開発しました。蛍光灯タイプのチョークとスターターから50Hzで作動するアークランプです。電源は20KHzで動作しましたが、起動時には約70KHzでLC共振を使用しました。 私の考えは、電源を85〜250Vacの電圧で広く動作させることで、共振程度で動作させることで、より早く始動するだろうということでした。また、ランプの定格は10W〜60Wであるため、PFCコントローラーは必要ありません。 しかし、私の懸念は、LLCがゼロ電流スイッチングに最適化されているため、スイッチング時間にジッターが発生することですか?このジッターは、おそらく光出力の品質に影響を与えるか、アークランプが持ちがちな小さなちらつきに比べれば些細なことかもしれません。 出力回路と、ランプのセンシング電流トランスから派生したコントローラの低電圧電源をアップロードしましたが、コントローラはアップロードしていません。これは、いずれにせよ、1980年代と1990年代のスロープ補償のない従来の電流モードコントローラです。 間違った方向に進んでいる場合は、別のコントローラーにアドバイスしてください。 Re:LLCモードはジッターノイズを導入しますか? 私は別の会社が彼らを作ることを期待しています、フィリップス/ NXPは一定期間物を作り、その後IPを売る傾向があります。 現在、どのメーカーがそれらの部品を製造しているか知っていますか? Re:LLCモードはジッターノイズを導入しますか? ありがとう、ヨゼフ、 あなたは私にいくつかの興味深いリンクをくれました。それは、ちらつきに対する目の感度というよりは、電子機器のちらつきに対する感度が私の関心事でした。以前に多くの統合を行った後に作成した電源は堅牢で、問題を非常にうまく解決しました。しかし、その効率は本来あるべき姿よりも劣っています。 あなたはマーキュリータイプの電源について言及しましたが、それはそれです。 https://www.nxp.com/docs/en/brochure/75017226.pdf ランプを始動するには、コントローラーがLC共振で動作する必要があることがわかります。実行中、周波数は変化する可能性があります(データシートに説明されているように、少し誘導性があります)。彼らがそれをするかどうかはわかりませんか? とにかく、私はあなたの推薦を検討し、他の道を追求するかもしれませんか? Re:LLCモードはジッターノイズを導入しますか? 親愛なるヨゼフ、 Osramのデータシートを彼らのウェブサイトからアップロードしました。私のブログには、これらのランプの1つが開始して実行しているYouTubeビデオもあります(以下のリンクを参照してください)。 https://blog.andrew-lohmann.me.uk/2018/07/electronics-high-frequency-arc-lamp.html ありがとう アンドリュー

[JN5189] Size of a flash memory page hello It seems that the flash page size for the JN5189 is 512 bytes, as defined in the SDK's app_flash.h file with '#define APP_FLASH_PAGE_SIZE 512'. Is it possible to modify this part to change the unit for writing to flash to 256 bytes? I tested by changing only APP_FLASH_PAGE_SIZE and it seems to read but not write. Do I need further modifications? Is changing the page size not supported originally? Could you guide me on the best approach to take? Thank you. Jonny9. Re: [JN5189] Size of a flash memory page Hi, Thank you for the confirmation. The Page size is something related to the internal flash of the MCU and not should be changed. Regards, Ricardo Re: [JN5189] Size of a flash memory page Hi, I made a mistake. The name I used for #define was FLASH_PAGE_SIZE, not APP_FLASH_PAGE_SIZE. For your reference, the base code is 'jn5189dk6_zigbee_ed_rx_on_bm'. That part is located in 'fsl_flash.h'. I apologize for any confusion this may have caused. Best Regards, Jonny9 Re: [JN5189] Size of a flash memory page Hi, Could you please confirm #define you are using? I could not find it on SDK. Regards, Ricardo Re: [JN5189] Size of a flash memory page Hello, I am using version 2.6.10. Best Regards, Jonny9 Re: [JN5189] Size of a flash memory page Hello, Hope you are doing well. Could you please clarify what SDK version are you using? Best Regards, Ricardo

NFCLIB init issues with PN7642 folowing a failed flash Hello, A board for a ISO 15693 tag reader worked perfectly for two days of testing. While working on another project I clicked on the wrong probe to flash the board, I accidently selected the probe my PN7642 board was connected to instead of the one for the other project. The J-Link driver indicated "CPU not found" but the board reseted and started to reset every few seconds. I can flash and run a program that doesn't require the NFC but if I try to run any program that uses the NFC the following message shows up and the program crashes. "Line: 154 Error - (0x001E) has occurred in NFCLIB" Did I damage something and is there a way to fix it ? Thank you, have a nice day. Re: NFCLIB init issues with PN7642 folowing a failed flash Hello, It solved the problem, thank you ! However I had to use IAR to flash the firmware update project because mcuexpresso couldn't do it. Thank you again for your help. Gwendal Re: NFCLIB init issues with PN7642 folowing a failed flash Hello @glev  Could you try to update FW and test again? Re: NFCLIB init issues with PN7642 folowing a failed flash Hello @KaiLi  It seems to me that the error comes from the PN76_Sys_Clif_Init() function, returning 0x001E. BR Gwendal Re: NFCLIB init issues with PN7642 folowing a failed flash Hello @glev  So when you debug, can you locate which API the error occurred? BR Kelly Re: NFCLIB init issues with PN7642 folowing a failed flash Hello @KaiLi, Thank you for your response. This board is not an NXP demo board, but it's based on the same module as the PNEV7642A and the design is heavily inspired by the demo board. All the proper antenna matching has been done. The two boards we have worked perfectly before this incident and the other one still does work with no issues. I run a custom firmware based on the NfcrdlibEx5_ISO15693 example running freeRTOS, but I also tried running the NfcrdlibEx5_ISO15693 example directly with the same result. "Line: 154 Error - (0x001E) has occurred in NFCLIB" at startup The same programs work perfectly on the other board and the demo board.  I'm using a J-LINK plus probe with IAR to program the device, I have added the proper JLINKscript. I also the direct storage method to program, with the same result. Best Regards Gwendal Re: NFCLIB init issues with PN7642 folowing a failed flash Hello @glev  Is your board an NXP demo board? Are you running the NXP application routine? If so, which routine is it? I may need to run trace on my side. BR kelly

Misleading LPDDR4 size in NXP DDR Tool Hello NXP-Team, hello Forum, we have a custom addapted iMX8mq-based board with 3G, running without any complains. Due to a LPDDR-memory discontinuation, we changed our LPDDR-Memory. Current LPDDR is: MT53B768M32D4NQ-062 New LPDDR is: MT53E768M32D2ZW-46 https://www.farnell.com/datasheets/4000640.pdf  We rerun the DDR-StressTest to configure the correct parameters of our new LPDDR The new LPDDR size is indicated in Excel sheet as expected with 24Gb But after loading the exported DDR-Script into NXP DDR Tool, the LPDDR size is announced with 1576MB. We expeted 3072MB per Controller / of the board. The DDR Stresstest is completed successfully, the Memory can be accessed up to the 3GB adresses within DDR-Tool (0x40000000 to 0xFF000000), In U-Boot, where we changed only the adapted DDR-Setting (code exported from DDR-Tool), runs without any Problem. But Linux boot fails (U-Boot's "Starting kernel ...." is the last reported info) What is the reason of the unexpected 1536MB memory announcment in DDR Tool, which is not according to the 3GB announced by MX8M-RPA-Excel sheet? Is there a misconfiguration, leading to the linux start failure? We are using i.MX 8M Family DDR Register Programming Aid (RPA), v33. Thank you for all your efforts N. Wiedmann i.MX 8 Family | i.MX 8QuadMax (8QM) | 8QuadPlus Re: Misleading LPDDR4 size in NXP DDR Tool Thank you, that is the reason for the incompatibility of the MT53E768M32D2ZW-46 The LPDDR needs 17 row bits to address its number of 98304 rows According to the linked 'memory compatibility guide', the i.MX 8M Quad is limited to 16 row bits. N. Wiedmann Re: Misleading LPDDR4 size in NXP DDR Tool Hi Sir, i.MX8M Quad  only support ROW=16 You can see this link https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-8M-Quad-8M-Mini-8M-Nano-8M-Plus-LPDDR4-DDR4-and-DDR3L/ta-p/1434761 Re: Misleading LPDDR4 size in NXP DDR Tool Hello Salas, thank you for responding. I tried with the Config Tools v15 (selected CPU, completed in the fields in DDRC-Tab, exported .ds and lpppdr4_timing.c file). The StressTestTool still reports the 'incorrect' LPDDR-size 1536MB (instead of 3072), U-Boot is running, Linux doesn't start. Could there be an issue with the "Number of ROW-Adresses"? The 'MT53E768M32D2ZW-46' data sheet reports R[16:0], the ExcelSheet blocks >16, in ConfigTool we tried 17, but it doesn't change the reported LPDDR-size Best regards, N. Wiedmann Re: Misleading LPDDR4 size in NXP DDR Tool Hello @NWiedmann  Could you please try to do the same but with the Config Tools v15 software? I will attach the user guide. Please let me know how it was. Best regards. Salas.

S32K144 EEPROMのデータの書き込み問題 AN11983にS32K144のEEPROMの設定を依頼し、0x14000000 0x14000004など4アドレスごとに正常にデータを書き込むことができますが、上記のアドレスでない場合、例えばデータが0x14000001 0x14000002 0x14000003に書き込まれている場合などは、「F:\...\...\Debug_FLASH/../Project_Settings/Startup_Code/startup_S32K144 です。S」が表示されますが、どこがうまく設定されていないのか、それとも他の理由なのか聞いてもいいですか?

fw_setenv corrupts environment on MTD for Linux kernels after 5.4 I'm using a BoundaryDevices Nitrogen 6 SOM2v2 with an i.MX6Q and sst25vf016b SPI NOR for U-Boot (environment stored on /dev/mtd1). System image is built via buildroot. For our system upgrade process, we need to change U-Boot variables from a shell script which is achieved via fw_setenv. The issue now is, that trying to use a kernel after 5.4 (tested with 5.10. 5.15, and 6.1), fw_setenv destroys the environment on the MTD, making the upgrade process fail (same failure for fw_setenv from UBOOT_TOOLS and LIBUBOOTENV). According to the folks at Boundary Devices, "The issue you're seeing is related to a bug in the MTD driver.  The driver comes from NXP, and we haven't made any modifications." The latest buildroot (2024.02.1), using the defconfig for this board uses the MTD driver from https://github.com/boundarydevices/linux/tree/boundary-imx_6.1.y/drivers/mtd The failure can easily be triggered using the following steps: # fw_printenv bootdelay bootdelay=3 # fw_setenv bootdelay 5 # fw_printenv bootdelay Warning: Bad CRC, using default environment Looking at the stored environment after these steps by means of hexdump -C /dev/mtd1 we can see that everything but the first byte for each block is 0xff, pointing to the erase being successful but the write only writing one byte. Any ideas on how to fix the driver? We really would like to move on past a 5.4 kernel/buildroot 2021.02… i.MX6Quad Linux Re: fw_setenv corrupts environment on MTD for Linux kernels after 5.4 We experienced the same issue using the sst25vf032b and sst26vf032b in both the 6.1 and 6.6 kernels. Thanks for this patch it has fixed the problem in both kernels versions for us as well.  Re: fw_setenv corrupts environment on MTD for Linux kernels after 5.4 After comparing the SPI traffic during write with working vs. non-working kernel issues I was able to track the issue down to the SST write code in the MTD driver and managed to fix this using the attached patch (patch against Linux 6.1, only tested against sst25vf016b). Re: fw_setenv corrupts environment on MTD for Linux kernels after 5.4 If by "Nitrogen" you mean the people at Ezurio (formerly Boundary Devices), I've tried that first and they said that their Linux kernel is the one from NXP so I should try here… Re: fw_setenv corrupts environment on MTD for Linux kernels after 5.4 Hello, Maybe someone of @Nitrogen could help on this. Regards

S32K144 EEPROM的写入数据问题 我参考AN11983对S32K144的EEPROM进行配置，可以正常每隔4个地址比如0x14000000 0x14000004写入数据，但如果不是上述地址，比如在0x14000001 0x14000002 0x14000003等写入数据，就会出现“Can't find a source file at "F:\...\...\Debug_FLASH/../Project_Settings/Startup_Code/startup_S32K144.S"”的警告，请问是我哪里没有配置好，还是有其他原因？

The writing data issues of the S32K144 EEPROM I refer the AN11983 to configure the EEPROM of S32K144, and the data can be written normally every 4 addresses such as 0x14000000 0x14000004, but if it is not the above address, for example, if the data is written in the 0x14000001 0x14000002 0x14000003, etc., the warning "Can't find a source file at "F:\...\...\Debug_FLASH/../Project_Settings/Startup_Code/startup_S32K144.S" " will appear, may I ask where I am not configured well, or is it some other reason? Re: The writing data issues of the S32K144 EEPROM thanks for Julián help.The problem has been solved, and I found that it was my understanding of the pointer, and when I used the 8-bit pointer to point to the address, I was able to store the 8-bit data. RobinY Re: The writing data issues of the S32K144 EEPROM Hi,Julián thanks for your reply. But the problem i want to solve is write 8 bit data int any location of the 4k EEPRAM, but when i write 8 bit data int 0x14000001 or 0x14000002 or 0x14000003, or any other address that can not be Divisible by 4,  the warning is appear "Can't find a source file at "F:\...\...\Debug_FLASH/../Project_Settings/Startup_Code/startup_S32K144.S".  i set the FlexRAM used for normal emulated EEPROM (No quick writes). Best regards, RobinY Re: The writing data issues of the S32K144 EEPROM Hi @RobinY, You can find the reason for this in section 3.2.1.3 (FlexRAM used for EEPROM quick writes) from AN11983: You can also refer to this community post for some notes: Solved: About S32K144 FlexRAM used for EEPROM quick writes - NXP Community Best regards, Julián

config switch PLLCFG0 PLLCFG1 RSTCFG WKPCFG BOOTCFG0 BOOTCFG1 TEST EVTI 怎么控制 您好,  我有个新的问题。   我想问下电路板这些引脚怎么设置才能用调试器从jtag口下载调试呢? Hello, I have a new question. I would like to ask how to set these pins of the circuit board to download debugging from the jtag port with the debugger? Re: config switch PLLCFG0 PLLCFG1 RSTCFG WKPCFG BOOTCFG0 BOOTCFG1 TEST EVTI 怎么控制 好的非常感谢您的回答，请问我们这个硬件需要怎么配pll呢？ Ok, thank you very much for your answer. May I ask how we need pll for this hardware? Re: config switch PLLCFG0 PLLCFG1 RSTCFG WKPCFG BOOTCFG0 BOOTCFG1 TEST EVTI 怎么控制 如果你有 配置启用 = OFF，即忽略其余部分并使用默认的内部晶体参考 等效配置是 CONFIG enable = ON，即RSTCFG = 从下面的引脚配置 BOOTCFG1=关闭， BOOTCFG2=OFF，即内部 PLLCFG0=开启， PLLCFG1=OFF，即晶体参考 WKPCFG = 开启， 您可以在设备的 RM 中找到 BOOTCFG/PLLCFG 描述。 无论如何，PLLCFG 配置需要适合所使用的硬件设置，除非设备受到审查，否则 BOOTCFG 在调试器连接和下载 SW 的环境中并不重要。

PIN Interrupt hi, i am configure  PIN Interrupt in lpc55s16  (level sensitive or active level triggering) using below the registers: Intr_No=0; PINT->ISEL = (1<< LOW_LEVEL); PINT->SIENR = 1UL << (uint32_t)Intr_No; PINT->SIENF= 1UL << (uint32_t)Intr_No; i want to configuration for using level sensitive active low, and active high Re: PIN Interrupt It seems you don't understand what "pin level interrupt" means in this context. This term relates to the logic levels "H" and "L", which are defined and fixed by hardware and supply voltage. You cannot detect other voltage levels that way. If this is your objective use an ADC, or specific external custom hardware. Re: PIN Interrupt In the SDK example pin interrupt level triggering interrurpt is worked but sometimes doesnt worked. controller not detect  varying voltage,  using 3.3 v  controller is detect the interrupt in level triggering same LOW&HIGH. as the same 1.2 v controller is not detected only sometimes i got interrupt. interrupt detect voltage for controller is 0.8v but why? this not happened continue interrupt signal. Re: PIN Interrupt The following SDK examples show you how to use the Pin interrupt & pattern match: Hope it helps you!

XRDC Memory regions HI there, I don't understand the cross reference between MRC Slave protected PFLASH_0, PFLASH_1,...PFLASH_WR, ...,PRAM0,PRAM1 (see below) and the s32k3xx_Memory Maps where FLASH splitted in program flash data flash  and ram is splitted in SRAM0,1,2 (see below). I need to know that in order to configure xrdc configurations Can you help me ? Re: XRDC Memory regions Hi @FabioG, You can see the ports in the block diagram. Figure 8. Block diagram – S32K324, S32K344 and S32K314 The PFLASH_WR port is for writting/programming the flash (not depicted), while other ports are just for reading. Refer to RM sections: 22.1.1 Flash memory architecture 23.1 Chip-specific PRAMC information Regards, Daniel

IVOR1 IRQは、SPC5746R割り込みをトリガーすることによって発生します。 私は現在SPC5746RMMT5チップを使用しており、電源用のS32 DSでeTPU set2をデバッグするときにIVOR1_IRQ割り込みを入力します。 TG機能は今のところ問題なく動作していますが、クランクキャプチャ割り込みを設定すると、IVOR1_IRQ割り込みがトリガーされます。 MCSRが正しく設定されていないか確認してください。 どうすれば修正できますか? Re: IVOR1 IRQ は、SPC5746R が割り込みをトリガーすることによって引き起こされます。 ありがとうございました。あなたは私のためにこの問題を解決しました!

How to use two sets of Ethernet simultaneously on RT106X or RT1170? HI I need to use two ethernet interface and have them both operational. I haven't found any relevant examples in the SDK. Thanks. i.MXRT 106x 回复： How to use two sets of Ethernet simultaneously on RT106X or RT1170? Hi @kevin198776 , Thanks for your feedback. But as far as I know, there shouldn't be any new EVK design for RT106x. But there may be some third parties that are implementing dual network ports. This link: https://community.nxp.com/t5/i-MX-RT/RT1061-Dual-Ethernet-MDIO-Interface-Questions/td-p/1521883 Also, the RT117x has an EVK that supports dual network ports. Best regards, Gavin 回复： How to use two sets of Ethernet simultaneously on RT106X or RT1170? Hi Gavin_Jia, Does NXP have plans to release a two-ethernet-interface EVB? Best regards, Kevin Re: How to use two sets of Ethernet simultaneously on RT106X or RT1170? Hi For the i.MX RT 106x take a look at the uTasker project, which supports flexible networking solutions: Multiple networks on multiple interfaces on - single or dual Ethernet - Wifi - Tethered USB https://www.utasker.com/index.html https://www.utasker.com/docs/uTasker/uTaskerNetworking.pdf https://www.utasker.com/docs/iMX/uTaskerV1.4_iMX.pdf https://www.utasker.com/docs/uTasker/uTaskerRNDIS.pdf https://www.utasker.com/docs/uTasker/uTaskerWIFI.pdf Allowing complete project development,and i.MX RT simulation using VisualStudio (including TCP/IP stack on emulated i.MX RT in real-time). Regards Mark (uTasker project lead) For our discounted i.MX and Kinetis production stock availability see https://www.utasker.com/Shop/semi.html 回复： How to use two sets of Ethernet simultaneously on RT106X or RT1170? Hi @kevin198776 , Thanks for your interest in NXP MIMXRT series! As you said, there is no dual Ethernet demo in the SDK at the moment, which makes it difficult for developers. But our colleagues have worked on a project (unofficially released) for RT106X based dual Ethernet. I don't know if this fully meets your needs, but for that matter, it's the only resource I can find at the moment. Thanks for your kind understanding in advance! Best regards, Gavin

imx8Mplusでhdmiクロックを増やす方法 drivers / phy / free scale / phy-fsl-samsung-hdmi.cのsamsung_phy_pll_cfg機能でHDMIクロックを増やす方法ファイルの解像度は 800x480 で、クロックは 32MHz です。 日時:imx8MplusのHDMIクロックを増やす方法 Shaojun、問題は解決しました。ご支援いただきありがとうございます。 日時:imx8MplusのHDMIクロックを増やす方法 確認してみます。

VR5510 Hi, I have a question when reading the AN13182 document. As shown in the figure below, it explains how to enter the OTP mode and read the corresponding status by register to determine whether the mode entry is successful. However, I did not see the register mentioned in the VR5510 data sheet. If I have misunderstood, please help me to correct how to determine whether the mode has entered. VR5510  Re: VR5510 Hi, @guoweisun  This is registered with my company email address, is this ok? Re: VR5510 No, both can be used. I suggest you use the method I recommend. Re: VR5510 OK, I will check this process carefully. I would also like to ask, regarding controlling VR5510 to enter standby mode, are there any examples of guidance? I have only seen an example about Pmic, which only initializes Pmic and does no other processing. Re: VR5510 OTP-related registers do not support general operations such as reading and writing. In OTP emulation mode, you can read and write the OTP registers. The diagram you just showed has this timing. However, once your product goes into mass production, that is, after OTP has been done, it is not recommended that customers read and write the OTP registers on normal product boards, and reading and writing will be invalid. Re: VR5510 I haven't looked at the software RTD and other drivers carefully. The most difficult part of this SBC is initialization and feeding the dog. The rest is very simple. Just follow the flowchart. It's not difficult. Re: VR5510 OK, I basically understand now, thank you. Then I have another question. In your previous reply, you said that the condition for entering standby is to invert the stby pin. In the pin configuration tool of S32DS, it seems that it cannot set the level. Is this pin just a notification pin? Re: VR5510 That means you can only use the support.nxp.com link to ask questions, https://community.nxp.com/ Is asking a question no longer supported? Re: VR5510 Home (nxp.com) In the future, it is recommended to use the link above to ask questions. It is not public and others cannot see it, only you can see it. Re: VR5510 Look at the following. After the SBC is initialized and RSTB/FS0B/FS1B is released, it can enter standby mode conditionally. This condition is circled below: Re: VR5510 VR5510 | Multi-Channel PMIC for Automotive Applications | NXP Semiconductors Can you download it yourself? I don't support the software here. If it is useless here, then it is basically useless. You just need to understand the logic of entering standby. Writing a program yourself can only Re: VR5510 Maybe there is something wrong with my description. My original intention was to enter the standby mode. I saw the following picture in the VR5510 manual. It says that Valid_STBY is required to enter the standby mode from the INIT_FS/NORMAL_FS state, where VALID_STBY = (STBY_SAFE_DIS_OTP=1 and STBY pintransition and ABIST1_ok) So I checked the STBY_SAFE_DIS_OTP explanation, it belongs to the CFG_2_OTP register, so I want to enter OTP mode to set this register Finally, if my method of entering standby mode is wrong, please help me guide how to enter standby mode; in addition, the VR5510 chip we purchased is not burned Re: VR5510 It is not supported for you to use the current board to directly read the OTP-related registers on the VR5510 chip that has already done OTP. I don't know what your intention is. Do you want to make the OTP yourself? Re: VR5510 This STBY is the INPUT pin and can be changed Re: VR5510 I see in the s32ds configuration tool that the properties of the pmic_stby_mode_b pin are all n/a. Can this pin still be set to a level like a normal pin? Re: VR5510 It needs a level conversion. What does the notification pin mean? Re: VR5510 Ok, thanks for the reminder! Still the original question, since the OTP register cannot be opened, how to determine whether it has entered OTP mode Re: VR5510 OK Is there any example of making both s32g3 and vr5510 enter stanby mode? I have seen a document called "S32G_Standby_Demo_V4-20221116-Eng.pdf", but I can't find the demo described in it on the official website. Do you have any corresponding examples to provide? Re: VR5510 What company are you from? Try to avoid asking questions using your own email address as this will have a very low priority. I suggest you ask using your company email address here or below: Home (nxp.com) Read the value of the register inside OTP, which is not currently available to customers

i.MX Security Reference Design Clarification Questions Hello, We implemented the security reference design described in section 10.9 of i.MX Linux User's Guide. Our custom board is based on the imx8mn_evk machine, and the image complies and boots successfully. However, we have questions based on the security-related messages we see during boot (see attached screenshot): Does "No HAB Events Found!" message mean a successful image authentication? Does the meta-secure-boot layer automatically program the SRK tabe hash fuse, or do we need to do this ourselves? We think we have to program the SRK hash fuse ourselves, but if that is the case, how come we got a successful authentication (assuming "No HAB Events Found!" means successful authentication)? We tried to read the SRK hash fuse (fuse 0x580 [256 bits]) to verify, but we always read zeros using uboot `fuse read` command. Is there a way to read this fuse? Thank you, i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Security Re: i.MX Security Reference Design Clarification Questions After some troubleshooting, the answers are summarized below: Yes No Because HAB 4.1.2 and higher only perform a hash check if SRK keys are not zeros. In this case, the SRK fuse was not programmed, defaulting to zero and, therefore, bypassing the hash check. This is only supported by the table posted below from @Harvey021. I can't find it in AN4581, but it matches what we are experiencing. @Harvey021, could you post the source of that table? A reset is required to read the fuse; otherwise, it reads zero. The combination of 3 and 4 made us doubt if we had a proper image before closing the device. We really wanted to see an intentional authentication failure. The only way to do this is to program the fuse and then generate an image with a different SRK table. Then, you will get the authentication failure messages as shown below. Re: i.MX Security Reference Design Clarification Questions AN4581: i.MX Secure Boot on HABv4 Supported Devices (nxp.com) Or search "AN4581" from nxp.com Have you reset the board before read it?  Please share more details about how you program SRK fuse hashs. Regards Harvey Re: i.MX Security Reference Design Clarification Questions @Harvey021, where did you get the table you copied (5.5.1)? This was not included in AN4581.We are familiar with AN4581, but it does not provide answers to our issue. Have you attempted secure boot on imx8mn EVK? Were you able to read back the SRK fuse after programming, or did you get zeros as well?  Re: i.MX Security Reference Design Clarification Questions Please refer to the AN4581. Regards Harvey Re: i.MX Security Reference Design Clarification Questions Please answer, "Based on this clarification, how come we are passing authentication when the fuse is all zero?" Also, we attempted to program the fuse using uboot fuse commands, but we are still reading zeros. Re: i.MX Security Reference Design Clarification Questions Q1, correct.  Q4, zeros means that there are no fuses hash burned. Regards Harvey Re: i.MX Security Reference Design Clarification Questions This response confirms that the meta-secure-boot layer provided in the security reference design dose not program the SRK fuse and we would have to do it ourselves. Based on this clarification how come we are passing authentication when the fuse is all zero? The statement “HAB (some versions and open device) won't compare SRK table against fuses when fuses are 0's.” does not agree with the statement “All HAB functions are executed as for a closed device.” mentioned in section 6.1.2.5 in imx8mn reference manual. Can you clarify? No answers were given to questions 1 and 4. Could you please provide answers.  thank you. Re: i.MX Security Reference Design Clarification Questions Hi,  HAB (some versions and open device) won't compare SRK table against fuses when fuses are 0's. That is correct, we have to burn SRK hash.  Without burning SRK hash, we will not get complete authentication. I think that the reference from Linux User guide mainly focus on the image signing with automation with Yocto build. Regards Harvey

How to configure clock for TCM on S32K3x? I am currently using the TCM feature of S32K3x in my RTD. I encountered an issue while configuring the TCM clock: According to the source code of RTD, it is necessary to configure a macro definition, CLOCK_IP_HAS_TCM_CM7_0_CLK,  before configuring the TCM clock. However, there is currently no corresponding place for CLOCK_IP_HAS_TCM_CM7_0_CLK. I also couldn't find any configuration options for the TCM clock in S32DS software. Should I manually modify Clock_Ip_Cfg_Defines.h to add this configuration?  (I'm using S32K312 Project)   The version information:   S32DS: 3.5 RTD: S32K3_RTD_3_0_0_D2303_ASR_REL_4_7_REV_0000_20230331 Best regards, Chris Re: How to configure clock for TCM on S32K3x? Hi Mr.Sun: ------ From your appeal description, I cannot infer a solution to the problem. At present, K312 does not seem to support the enable configuration of TCM-CM7_0_CLK. Can you provide a more detailed solution. The problem I am currently facing is that after the interrupt is enabled and triggered, I cannot enter the interrupt. I don't know if it is related to TCM-CM7_0_CLK not being enabled? Re: How to configure clock for TCM on S32K3x? Hi @VaneB  Thank you for your response to my post. Your response resolved my confusion.   Best regards, Chris Re: How to configure clock for TCM on S32K3x? Hi @Chris-Sun  The PRTN2_COFB1_CLKEN[REQ62] field for Cortex-M7_0 is enabled at reset as you can see from the image below: B.R. VaneB

Flashed ELF file onto S32K146 via SEGGER J Link. Now, I am unable to flash other SW or even erase it Hi Community Members,                 We have flashed our own hardware board with S32K146 with an ELF file via Segger J Link Lite version. The file is attached. Now, I was trying to flash a different mot file with a different SW, however it does not allow me to program the chip. I even tried erasing the complete chip, however I get the error saying "CPU could not be halted". (The current consumption through the board is approx. 0.6A with just one Digital output configured. In our other SW, that has around 20 IOs and 20 CAN messages, the current consumption is generally 0.13A.) Is there any other way that we can erase the chip using Segger - jlink SW tool or any other SW? And can we generate .hex/.bin file from the S32DS for s32k146 projects? Re: Flashed ELF file onto S32K146 via SEGGER J Link. Now, I am unable to flash other SW or even eras Hi @Coding_Torque-SDRS, Could you read the MDM_AP registers? Try to follow the instructions with J-Link commander from the following post: Unbricking S32K146 - NXP Community (Also trying to hold the reset pin low externally if the J-Link commander cannot communicate.) Best regards, Julián Re: Flashed ELF file onto S32K146 via SEGGER J Link. Now, I am unable to flash other SW or even eras @Julián_AragónM Thanks for the support, It really help in resolving the issues that I'm currently facing with creating .hex/.bin file generation.  @Julián_AragónM We tried using Manual programming as referred by you to erase the data from the chip, but it's not even connecting to the CPU when Erase Chip is clicked. It's throwing message like "CPU can't be halted". Please do refer some other way to erase the chip.  Thanks, Coding_Torque-SDRS Re: Flashed ELF file onto S32K146 via SEGGER J Link. Now, I am unable to flash other SW or even eras Hi @Coding_Torque-SDRS, You can look into the J-Link Flash Download directly from SEGGER. This tool supports the S32K146 and may help with manual programming:  As for the .hex/.bin files, you can refer to this community post: HOWTO: Generate S-Record/Intel HEX/Binary file - NXP Community Best regards, Julián