Ara240 Module Bring-Up on FRDM-IMX95-PRO Getting Started Video: (function() { var wrapper = document.getElementById('lia-vid-6403214335112w960h540r398'); var videoEl = wrapper ? wrapper.querySelector('video-js') : null; if (videoEl) { if (window.videojs) { window.videojs(videoEl).ready(function() { this.on('loadedmetadata', function() { this.el().querySelectorAll('.vjs-load-progress div[data-start]').forEach(function(bar) { bar.setAttribute('role', 'presentation'); bar.setAttribute('aria-hidden', 'true'); }); }); }); } }})(); (view in My Videos) This guide provides step-by-step instructions on how to verify successful communication and the runtime software environment to interface with the Ara240 module with the FRDM i.MX 95 Pro development board. Out of the Box: Get Familiar with the Ara240 Module Ara240 Module [Back view]Ara240 Module [Back view] Ara240 Module [Top view]Ara240 Module [Top view]         Connecting the M.2 Module This section explains how to connect Ara240, a discrete module, to the FRDM i.MX 95 Pro development board. The instructions in the FRDM i.MX 95 Pro Getting Start Guide will walk you through the boot-up process for the pre-loaded Embedded Linux image on the board and how to connect the USB debug cable. For additional details, see the official FRDM i.MX 95 Pro Development Board documentation. References: FRDM i.MX 95 Pro Quick Start Guide FRDM i.MX 95 Pro Development Board product page  FRDM i.MX 95 Pro Getting started page Getting Started with ARA2-M2-16G-GT Follow the steps below to connect the Ara240 module to the FRDM i.MX 95 Pro development board: Spoiler (Highlight to read) Important: Ensure the board is powered off before making any connections. Important: Ensure the board is powered off before making any connections. Insert the Ara240 module into the M.2 Key-M socket on the FRDM i.MX 95 Pro development board. Using the screw provided, secure the module. Connect the fan cable to the board’s fan header (refer to the FRDM i.MX 95 Pro board documentation for the exact header location). "How to connect two Ara240 devices?" The figure below illustrates the connection of Ara240 devices to the two M.2 Key-M slots on the FRDM i.MX 95 Pro development board. You can install one Ara240 device in either slot or connect two devices simultaneously by using both slots. Connect the Ara240 to the FRDM i.MX 95 Pro development board.Connect the Ara240 to the FRDM i.MX 95 Pro development board. Power on the Board Follow the instructions to power on (boot) the board found in the Getting Started with FRDM-IMX95-Pro. After powering on, verify that the fan and green LED indicators Ara240 module are on are on. Get the Software This section will walk you through the Ara240 Runtime software development kit (SDK), a streamlined subset of the Ara240 SDK designed for rapid enablement and execution on NXP platforms. The Runtime SDK simplifies installation and configuration, enabling developers to quickly deploy and run AI/ML workloads on the Ara240 module with minimal effort. Overview Refer to Ara240 software release notes for details on the Ara240 software development kit (SDK) The Getting Started page for Ara240 only outlines usage on specific i.MX development platforms For any other platforms please reach out to your NXP representative for guidance. Spoiler (Highlight to read) Q2'26 BSP (L6.18.20-2.0.0) onwards runtime environment for i.MX 8MP and i.MX 95 boards is packed with Linux BSP. Q2'26 BSP (L6.18.20-2.0.0) onwards runtime environment for i.MX 8MP and i.MX 95 boards is packed with Linux BSP.     Module Enumeration and Software Configuration This section provides instructions to verify proper installation of Ara240 module and configuration of the Ara240 Runtime SDK on the FRDM i.MX 95 Pro development board. Verify Device Detection Once the board has successfully booted, connect to the serial debug port to monitor system logs. To confirm that the Ara240 module is being detected by the board, run the following command: $ lspci | grep 1e58 Expected output: 0000:01:00.0 Processing accelerators: Device 1e58:0002 (rev 02) Enable Ara240 device For quick enablement, the Ara240 Runtime SDK starts at boot time. Refer to the Ara240 Runtime SDK documentation for detailed instructions and environment setup steps. Spoiler (Highlight to read) Q2'26 BSP (L6.18.20-2.0.0) onwards runtime environment for i.MX 8MP and i.MX 95 boards is packed with Linux BSP. Q2'26 BSP (L6.18.20-2.0.0) onwards runtime environment for i.MX 8MP and i.MX 95 boards is packed with Linux BSP.     Developer Experience This section provides an overview of Ara240 runtime software enablement using the FRDM i.MX 95 Pro development board. Verify Setup Environment Use the following guidance on how to connect required devices. For most of the demos, you would need a camera, keyboard, mouse, internet connection and a HDMI display monitor. Setup preparation for FRDM i.MX 95 Pro boardSetup preparation for FRDM i.MX 95 Pro board Spoiler (Highlight to read)  NOTE: You might need to use a USB hub to connect keyboard, mouse and camera at the same time.  NOTE: You might need to use a USB hub to connect keyboard, mouse and camera at the same time.   Runtime setup Description Runtime SDK delivers a complete runtime environment that enables AI/ML acceleration on the Ara240 module. To run demo applications, ensure that the Ara240 bring-up process has been successfully completed and the system is ready for demo evaluation. Refer to the Runtime SDK documentation for detailed guidance on: Verifying correct installation of the Runtime SDK. Checking and updating the Ara240 firmware version. Validating proxy service bring-up status. Executing benchmark tests on Ara240. Following these steps ensures that the module is properly initialized and ready for use. Ara240 supports the execution of CNNs, LLMs, VLMs, and agentic frameworks, enabling advanced AI workloads to run directly on Ara240. For comprehensive examples and end-to-end workflow guidance, please refer to the Ara SDK documentation page. Ara240 Demos Henceforth Q2'26 Linux BSP, GoPoint can be launched to explore preselected Ara240 demonstrations included in the NXP provided Linux Board Support Package. User Guide: GPNTUG: GoPoint for i.MX Applications Processors User Guide  FRDM-IMX9

Subject: Standalone Evaluation Software / GUI for MC33774A AFE (RD33774CNC3EVB) I am working with the RD33774CNC3EVB (MC33774A-based CMU) and the RD-K358BMU evaluation board. I would like to evaluate and validate the MC33774A AFE independently, without integrating the complete BMS system. My goal is to verify features such as: - Cell voltage measurements - Temperature measurements - Diagnostics and fault reporting - Passive cell balancing - Register configuration - Communication between the BMU and AFE I have the following questions: 1. Does NXP provide a standalone evaluation GUI or PC software for the MC33774A? 2. Is there a FreeMASTER project, demonstration GUI, or any other graphical tool that can be used to monitor and configure the MC33774A through the BMU? 3. Is there a reference application or example firmware that enables evaluation of the MC33774A with minimal software development? 4. Are there any applications describing the recommended setup for evaluating the MC33774A using only the BMU and CMU evaluation boards? My objective is to perform functional validation of the AFE before integrating it into a complete BMS system. Thank you for your support. RD33774CNC3EVB , MC33774 , MC33665A  Re: Subject: Standalone Evaluation Software / GUI for MC33774A AFE (RD33774CNC3EVB) Dear Sanket, 1. Does NXP provide a standalone evaluation GUI or PC software for the MC33774A? [A] Yes, there is an EvalGUI 7 for the MC33774A. Specifically to be used with RD33774ADSTEVB. The GUI is intended to be used with SPI interface for communication between MCU and SPI to TPL transceiver and then via TPL to the MC33774A. Please refer to the UM11816.  JozefKozon_0-1785399710998.png If you are asking if there is a GUI specifically for the RD33774CNC3EVB with populated MC33665A TPL to CAN transceiver for the communication with MCU via CAN interface, unfortunately, there isn't any.  2. Is there a FreeMASTER project, demonstration GUI, or any other graphical tool that can be used to monitor and configure the MC33774A through the BMU? [A] For the BMU and CMU boards you mentioned we have a whole software bundle. However you need an S32DS IDE. JozefKozon_6-1785400949053.png Please refer to this link. Included are Demo projects for the FreeMASTER.  JozefKozon_1-1785400007530.png Please refer to the Release Notes document on the right side. JozefKozon_2-1785400038979.png 3. Is there a reference application or example firmware that enables evaluation of the MC33774A with minimal software development? [A] See above what software is available for the EVBs you have. However, the two boards are not sufficient. You need your own battery pack, with minimally 4 Cells for each MC33774A, or we have BATT-18EMULATOR. Emulating 18 Cells for each MC33774A populated on the RD33774CNC3EVB.  Please refer to the UM11943.  JozefKozon_3-1785400370798.png JozefKozon_4-1785400486233.png 4. Are there any applications describing the recommended setup for evaluating the MC33774A using only the BMU and CMU evaluation boards? [A] Yes there is. However as mentioned above you need either a battery pack or the battery emulator. Please refer to the UM11943 and to this link. JozefKozon_5-1785400737734.png With Best Regards, Jozef Re: Subject: Standalone Evaluation Software / GUI for MC33774A AFE (RD33774CNC3EVB) Can we use RD33774CNT3EVB(which is TPL based) for standalone testing as the mentioned part number is not available with us but RD3374CNT3EVB id available along with the required setup  RD33774CNT3EVB 

PCA9615 I am writing to ask for help with the circuits at either end of dI2C communication - between two PCBs across a twisted wire bundle (DSDAP & DSDAM; DSCLP &  DSCLM; two GND; and two 5V lines). Leading up to this I decided to test Gemini so I regretably relied on AI to generate the parts of the two PCBs that related to the dI2C comms. Attached are the parts of the schematics associated with the dI2C. Unsuprisingly there is no comms between the boards, but my laziness and I have to say stupidity (leason learnt) has cost me a lot of time. I finally referred to the datasheet and the user manual for the demo board and one obvious difference is that there are 600 Ohm resistors between the positive lines (DSCLP and DSDAP) and VDD(B), the same from the negative lines (DSCLM and DSDAM) and VSS, and 120 Ohms between the respective positive and negative lines which apparently result in 100 Ohms between the positive and negative lines (I know that 1/600 + 1/120 = 1/600 + 5/600 = 100, but I can't see it electrically- maybe because I'm a mechanical engineer ??). Is the error (maybe one of a number of errors) caused by not having what may be considered a 600 Ohm pull up resistor, a 600 Ohm pull down resistor and a 120 Ohm resistor between the respective pair of wries (characteristic impedance of a 28 AWG twisted wire pair is about 100 Ohms cabling used in internal data links and USB/Ethernet configurations and 78 Ω to 95 Ω for standard spacing configurations using PVC or FEP insulated wires), but instead a simplified and likely erroneous version of just a single 100 Ohm resitor at either end of the connecting wire on the dI2C side of the PCA9615?  That is one significant difference between what AI gave me and what I see in Figs 1, 7, 8 and 9 of the datasheet. Another difference is that AI suggested different capacitor arrangements for the two PCBs whereas there's only one type of arrangement on the demo board (which I assume gets used on both sides of the dI2C connecting line). Further, there appears to be two capacitors for each of the VDDA pin and the VDDB pin - both ceramic capacitors (although my first thought was that the two yellow capacitors would have been tantalum type). Can I use the capacitor arrangement provided in the demo user manual and ignore what AI provided and shown in the attached? Another issue is that on the master side (on which I am using a 3.3V microcontroller) originally Ai instructed that the enable pin be conencted to the 5V line, but after having had the boards made, the lack of any function across the two boards in part prompted the AI to determined that the enable pin on the master side should have been connected to the 3.3V line (VDD(A) on the master board was connected to the 3.3V line). It then requested that all all supply to the enable pin on the master PCB be cut completely as a test. Can you please advise what supply, if any all, should be channeled to the EN pin? I will not be hot swapping any electrical hardware during test or final operation. I am considering implementing the above changes, but would really appreciate your help before I proceed further with costly boards. Re: PCA9615 Just a further thing regarding the capacitors, only decoupling capacitors were suggested for both VDDA and VDDB pins on the master PCB. Decoupling capacitors were also suggested for the slave PCB, but two additional capacitors were also suggested for the VDDB pin on slave PCB.  Re: PCA9615 Hello! Thank you for the detailed explanation. Please note that NXP provides an evaluation board for the PCA9615 family that can be used as a reference design for your implementation. We strongly recommend comparing your schematic against the PCA9615 evaluation board and its associated user manual, as the design includes the recommended differential I²C termination network, biasing resistors, decoupling capacitors, and EN pin connections that have been validated by NXP. Using the evaluation board schematic as a baseline is often the best approach when designing a custom PCA9615-based system, as it minimizes the risk of configuration or layout issues and follows the recommendations provided in the datasheet and application documentation. We suggest reviewing the evaluation board schematic and updating your design accordingly before committing to another PCB revision. https://www.nxp.com/products/interfaces/ic-spi-i3c-interface-devices/ic-i3c-bus-repeaters-buffers-and-extenders/pca9616pw-demo-board:OM13523UL Hope this helps!

FRDM-IMX95: No Serial Output when Booting from SD Card (Pre-installed eMMC Boot Works Perfectly Hello NXP Community, I am mechanical and electrical engineering background, and this is my first time diving deep into complex System-on-Chips (SoCs) and embedded Operating Systems. For my project, I am using the FRDM-IMX95 development board. My ultimate goal is to run two operating systems in parallel using an IPC (Inter-Process Communication) framework. The board arrived with a pre-installed Linux image on the internal eMMC. This works flawlessly out of the box, and I get full serial output logs in my terminal monitor program. Now, I am trying to follow the official Getting Started Guide to flash the standard Linux BSP image onto a microSD card using UUU (Universal Update Utility) on a Windows host machine. According to the Windows command prompt, the UUU flashing process completes with a "SUCCESS" status. I used the following standard command layout: ".\uuu.exe -b sd_all imx-boot-imx95-15x15-lpddr4x-frdm-sd.bin-flash_all imx-image-full-imx95evk.wic" The Problem: After successful flashing, I turn off the board and configure the physical boot switches for SD Boot Mode by setting SW1 [1:2] to 11 (ON / ON). When I power the board back on, the serial monitor remains completely blank. There is absolutely no text output or hardware initialization visible. 1. Do I have a fundamental misunderstanding of how the boot chain works here? According to the i.MX Linux User's Guide, the .wic image contains all four essential pieces, including the bootloader image (U-Boot). Shouldn't I at least see the initial U-Boot SPL sequence appearing on my serial monitor, since the basic hardware configuration blocks should be read from the card? Any insights, common pitfalls for beginners on this specific FRDM variant, or hidden switch requirements would be highly appreciated! Best regards FRDM-Training Re: FRDM-IMX95: No Serial Output when Booting from SD Card (Pre-installed eMMC Boot Works Perfectly Hello,  I'm testing on my side to share the exact steps for you, I will update soon.  Re: FRDM-IMX95: No Serial Output when Booting from SD Card (Pre-installed eMMC Boot Works Perfectly Thank you for looking into this and testing it on your end! I appreciate the help and look forward to your update. Re: FRDM-IMX95: No Serial Output when Booting from SD Card (Pre-installed eMMC Boot Works Perfectly You have the issue because you are trying to flash to the SD card with the uuu tool, it is made to flash the emmc, if you want to flash the sd card you have to perform the following command in a linux host machine.  $ sudo dd if= .wic of=/dev/sdx bs=1M && sync To identify the device node assigned to the SD/MMC card, carry out the following command: $ cat /proc/partitions major minor #blocks name 8 0 78125000 sda 8 1 75095811 sda1 8 2 1 sda2 8 5 3028221 sda5 8 32 488386584 sdc 8 33 488386552 sdc1 8 16 3921920 sdb 8 18 3905535 sdb1

S32k344 design studio driver example code Hi Team  I wanted to run basic example codes on S32k344.  I have installed  S32 Design Studio for S32 Platform Version: 3.6.0 Build id: 241128 I am unable to find any diver examples in . I even with S32k extension and update to update s32k3xx package but the installation fails every time. It is stuck at 70%. Please let me know if you require any other information and help with basic examples. Regards Gopal Re: S32k344 design studio driver example code Hi @rathi_tg  To get started, we recommend using the latest version of the tools available, which is currently S32 Design Studio 3.6.10. There is no need to install it as a separate instance, as it can be installed as an update to your existing installation. Detailed instructions for this process can be found in the S32 Design Studio 3.6.10 RFP Installation Guide, which is available on the same download page as the S32DS installer. Regarding examples for S32K3 devices, these are included as part of the RTD packages. A good reference is the video How To Download, Install and Configure the RTD 5.0.0 with S32 Design Studio 3.6.0, which explains in detail what components need to be downloaded, how to install them, and how to create a project based on example. Although the video was created for RTD 5.0.0, the procedure is similar for newer RTD releases. Note: The latest RTD release available for S32K3 devices is RTD 7.0.1. Additionally, you may find useful examples and application projects in NXP's Application Code Hub, which contains a variety of ready-to-use examples for different devices and use cases. BR, VaneB Re: S32k344 design studio driver example code Hi   I have successfully imported the driver files and i have imported "Siul2_Dio_Ip_Example_S32K344" project. i have run the mex and updated the code. the code is built without any error. I have S32k344-WB with me which when powered on has a default switch and led program.  When I flash my built file the progress bar shows 100% but  i am unable to see any changes in the board behavior it is still executing the old code.  Regards  Gopal  Re: S32k344 design studio driver example code Hi @rathi_tg  How did you determine that the application is running old code? Also, please note that the example projects are tested with specific boards, which are listed in the description.txt file included with each example. Because different boards can have different hardware configurations, please verify that the pin assignments and configurations match your target board. You may need to update some of the pin settings accordingly to ensure the example works correctly on your hardware. Re: S32k344 design studio driver example code Hi @Valval  The issue got resolved i did not install the debug package  . Regards  Gopal

How Can I Watch All Live Events? Hi everyone, I’m a student and I’m trying to find a simple and reliable way to watch live events, sports, news, and other live programs online without getting confused by too many different websites and apps. I’ve heard people mention IPTVGREAT, but I’m not looking to promote any service. I just want to understand my options and find something that is safe, affordable, and easy for a student to use. If you have experience with watching live content online, could you please share some advice? I’d especially appreciate recommendations for legal and reliable options, free services, or affordable platforms that work well on a laptop or phone. Thanks to anyone who can help. I’m just trying to find a practical solution without spending too much as a student.

Clarifications required regarding Fail safe oscillator drift Fault(FS_OSC_DRIFT) Hi Nxp, I have been using FS2613 SBC chip and I found safety requirement (SM48) which is related to Fail safe oscillator drift Fault (FS_OSC_DRIFT). But ASIL level information is not available in reference manual. So, kindly clarify that, this fault comes under either ASIL B/ ASIL D/ QM? Thanks, Sivahari G Re: Clarifications required regarding Fail safe oscillator drift Fault(FS_OSC_DRIFT) Hello Sivahari Good day! The FS_OSC_DRIFT fault (SM48) corresponds to the monitoring of the independent fail-safe oscillator used by the FS26 fail-safe state machine. According to the FS26 Safety Manual, this mechanism is implemented within the ASIL D fail-safe domain. You can find this representation in Figure 8. Safety architecture. I hope this information has helped you, please let me know if you need help with anything else. Have a great day and best of luck.

IW612 Bluetooth UART not responding on i.MX95 after combo firmware download Hello,     we are bringing up Bluetooth on a Verdin i.MX95 WB running the NXP Android 15 BSP (Linux 6.6.58). The onboard wireless module is a u-blox MAYA-W260 based on NXP IW612. Wi-Fi works correctly over SDIO, and the combo firmware is successfully loaded: Request firmware: sduart_nw61x_v1.bin.se Wlan: FW download over WLAN FW is active ,Bluetooth instead does not appear to work. Whenever we enable it on Android settings, the UI switch is frozen and no BT device is found. Bluetooth is connected to LPUART6 (/dev/ttyLP5). The NXP vendor HAL opens the UART successfully. We initially found that hardware flow control blocked transmission; after temporarily disabling CRTSCTS, the HAL sends the four-byte HCI Reset command: 01 03 0c 00 The UART counters then show: tx:4 rx:0 No response is received from the IW612. The same result occurs with a direct manual UART test at 115200 baud, 8N1, without hardware flow control. Our current configuration is: mchar_port = /dev/ttyLP5 baudrate_fw_init = 115200 enable_download_fw is left disabled because the combo firmware is already downloaded by the Wi-Fi driver. Could you please clarify: After loading sduart_nw61x_v1.bin.se through SDIO, should the IW612 Bluetooth UART respond directly to an HCI Reset at 115200 baud? Is a boot-sleep trigger, wake command, vendor command, or another initialization sequence required first? Is hardware flow control mandatory for IW612, and what should the expected CTS state be after firmware initialization? Should we use the UART firmware-download path with uartspi_n61x_v1.bin.se instead of relying on the combo firmware loaded by Wi-Fi? Is there a recommended bt_vendor.conf for IW612 on i.MX95? Any reference configuration or expected UART trace would be very helpful. Best regards. Android Linux Re: IW612 Bluetooth UART not responding on i.MX95 after combo firmware download Hi, @vins-idg  1. After loading sduart_nw61x_v1.bin.se through SDIO, should IW612 Bluetooth UART respond directly to HCI Reset at 115200? In principle, yes — once the combo firmware is active and the BT UART block is awake/ready, the controller should respond to HCI Reset with a Command Complete event. 2. Is a boot-sleep trigger, wake command, vendor command, or other initialization sequence required first? For normal Android bring-up, do not rely only on manually sending HCI Reset. Let the NXP vendor HAL or NXP UART driver perform the initialization sequence. 3. Is hardware flow control mandatory for IW612? What should CTS state be? For a production IW612 BT UART design, hardware flow control should be enabled and correctly wired. Disabling CRTSCTS is useful only as a diagnostic step; it should not be considered the final fix. 4. Should we use uartspi_n61x_v1.bin.se instead of combo firmware loaded by Wi-Fi? You  can have a try with the seperate FW to debug the issue, but it should not the root cause. With combo FW, should also work as expected. 5.Let me have a try on my local side then share to you a worked on my side conf file to you. Please allow me some time. Best regards, Christine. Re: IW612 Bluetooth UART not responding on i.MX95 after combo firmware download Hi, @vins-idg  How is your side? I took some time to prepare the environment to build Android 16 source code. Now I can build it, it will need some time to finish building, please allow me some more time. Best regards, Christine. Re: IW612 Bluetooth UART not responding on i.MX95 after combo firmware download Hi， @vins-idg  Sorry for my late reply and thanks for your patience. I already finished the local test on my side, and now IW612 can work fine on my I.MX95-19*19-EVK. Because there is no Verdin board，I use I.MX95-19*19-EVK to finish the test. Below is the bt_vendor.conf screenshot and also you can see BT can work fine on the right side. In fact, I just use the default bt_vendor.conf and do not modify anything in it. Hope it can help you somehow. bt_vendor.conf.png If it still could not work on your side, please help to provide me your dts and also dmesg logs for further checking. Because here, the community is a public place, to save your security info, you can send your dts file to my private working email: [email protected].  Best regards, Christine. Re: IW612 Bluetooth UART not responding on i.MX95 after combo firmware download Hi, @vins-idg  Did you get any chance to read my above comment? How is it going on your side? Please let me know if need any further info from my side. Best regards, Christine. Re: IW612 Bluetooth UART not responding on i.MX95 after combo firmware download Hi, @vins-idg  How is it going on your side? Please let me know if need any further info from my side. Best regards, Christine.

i.MX95 FRDM + OX05B1S: Blue/Purple AR coating reflection on eyeglasses under indoor lighting Board/Setup:  - SoC: NXP FRDM i.MX95   - Camera Sensor: OmniVision OX05B1S (connected via MIPI CSI)  - Pipeline / Software: libcamera (v0.5.2) + NXP Neo IPA (nxpneo) + GStreamer (imxvideoconvert_g2d)  - BSP: i.MX Linux BSP Description: When streaming live video from the OX05B1S camera on the FRDM i.MX95, some of the eyeglasses exhibit a dark blue/purple glare spot under indoor office lighting (see attached images). How can we resolve this dark blue/purple glare artifact on reflective surfaces (like glasses)? What are the recommended Neo ISP tuning parameters or tuning tool version available for i.MX95 to fix this? photo_04.jpg photo_07.jpg Re: i.MX95 FRDM + OX05B1S: Blue/Purple AR coating reflection on eyeglasses under indoor lighting Hi @JosephAtNXP, Thank you for the quick response and the insights regarding the lens flare, tone mapping, and black level configurations. We do not currently use a third party for ISP tuning. We are using the tuning file provided by NXP for the OX05B1S sensor, which we found located at /usr/share/libcamera/ipa/nxp/neo/ox05b1s.yaml in our BSP. Is it possible for NXP to provide a newly updated tuning file for the OX05B1S that mitigates this specific lighting artifact? If an updated file isn't available, could you guide us on the exact parameter changes we should manually adjust in our existing ox05b1s.yaml file to fix this issue? Looking forward to your guidance. Regards, Akash H Re: i.MX95 FRDM + OX05B1S: Blue/Purple AR coating reflection on eyeglasses under indoor lighting Hi, Thank you for your interest in NXP Semiconductor products, From the attached image, the dark spots seem like lens flares captured from a specific angle and reflected probably by blue light filters in your glasses. Dark tones might be product of ISP tone mapping or black level configs. I would suggest ISP tuning the sensor, JosephAtNXP_0-1785175157838.png In your projects, are sensors tuned by you or third parties? Regards Re: i.MX95 FRDM + OX05B1S: Blue/Purple AR coating reflection on eyeglasses under indoor lighting Hi @akashhalli, Could you please try with uGuzzi IPA and share the results? Please share the BSP you are using as well. Try with latest BSP and share if you see any different results. Regards, Re: i.MX95 FRDM + OX05B1S: Blue/Purple AR coating reflection on eyeglasses under indoor lighting Hi @akashhalli, Did you get any chance to test my suggestions? Could you please create a technical case for follow up? Regards, Re: i.MX95 FRDM + OX05B1S: Blue/Purple AR coating reflection on eyeglasses under indoor lighting Hi @JosephAtNXP , The current BSP we are using is Linux 6.12.49_2.2.0. Regarding testing with uGuzzi IPA, the camera we were using has unfortunately gone bad, so we are currently unable to perform the requested test. We will repeat the test with a working camera setup and share the results once it is available. We will also check with the latest BSP and update you if we observe any differences. Regards, Akash

S32K144W SDK installed but not available when creating a project Hello, I am having the same problem described in this topic. I am working with an S32K144W. My S32 Design Studio version is: S32 Design Studio for S32 Platform Version: 3.6.10 Build id: 260720 When I create a new S32DS Application Project, select the S32K144W processor, and click the SDK button, no SDK is available. The strange thing is that I have already installed the SDK. It does appear in the SDK Management, so apparently the installation was successful. micael_arkmeds_0-1786395593570.png Figure 1 – SDK Management showing that the SDK is installed. However, when I create a new S32DS Application Project and select the S32K144W, the SDK is not available. micael_arkmeds_2-1786395688395.png Figure 2 – S32K144W selected in the New S32DS Application Project wizard. When I click the SDK button, the list is completely empty: micael_arkmeds_3-1786395712528.png Figure 3 – SDK selection window showing no available SDK. I have been looking for a solution to this problem for quite some time. I also followed the official offline installation procedure described here: https://community.nxp.com/t5/S32-Design-Studio-Knowledge-Base/HOWTO-offline-install-S32K3-RTD-4-0-0-in-S32DS-v3-5/ta-p/1968014 However, this did not solve the problem. So, I would like to understand what exactly is required for an SDK to become available in the project creation wizard for the S32K144W. Is there a specific SDK/RTD version that is compatible with S32 Design Studio 3.6.10 and the S32K144W? Is there any additional package or configuration that I need to install? The fact that the SDK appears in SDK Management, but does not appear when creating a project, makes me think that the SDK is installed but is not being recognized as compatible with the selected processor/project. If anyone has already solved this issue with the S32K144W, I would really appreciate it if you could explain the exact steps. Thank you! Re: S32K144W SDK installed but not available when creating a project Solved! I finally found the solution to this issue. Even though the RTD 3.0.0 was already installed and appeared in SDK Management, it was not available when creating a new project. The solution was to install: NXP GCC for Arm Release version 10.2 build 1728 Then, when creating the project, I selected GCC 10.2 as the project's toolchain. After doing this, RTD 3.0.0 appeared correctly as an available SDK option. 2026-08-10_18-14.png 2026-08-10_18-14_1.png My environment is: S32 Design Studio for S32 Platform 3.6.10 Build id: 260720 S32K144W RTD 3.0.0 NXP GCC for Arm 10.2 build 1728 So, if someone has the same problem where the SDK appears in SDK Management but does not appear in the project wizard, make sure that the corresponding NXP GCC 10.2 toolchain is installed and selected. This solved the problem for me.

S32K144如何开辟一段内存地址 实现独立变量的存储 恩智浦官方的技术人员你们好 我在开发S32K144芯片的过程中遇到了一个问题 Ni__0-1786350352171.png 以上述地址说明为例  我想单独开辟出一段地址 来存放一些全局变量 1.可以实现掉电保存 擦除和改写的功能 2.还有在程序运行的过程中还要可以参与逻辑运算 3.在编译生成srec文件后 可以将这段地址内容数据截取出来 我不清楚  将这些变量放在哪个地址段合适 地址分配的编程语法该怎么写  应该怎么改写工程内部的 Linker_files文件夹中的.ld文件 有没有  这方面的参考资料 提供学习 我对  S32K144芯片的开发还存在不懂的地方 对于 Linker_files文件夹中的.ld文件 flash分配  用语法该怎么写  为什么这么写  我还不知道 我想能得到这方面的知识  能有一个官方明确 正确的 语法规范和内部逻辑说明 以提供学习 衷心期待您的回复    万分感谢！ Re: S32K144如何开辟一段内存地址 实现独立变量的存储 Hi@Ni_ 请下次务必使用贵司的邮箱账户进行提问，对于通用邮箱，例如QQ,163,GMAIL等邮箱账户，我们不会优先处理。 我先回答你的第一个问题： 我以RTM版本提供的链接文件为例，其实在该链接文件中已经告知该如何实现划分独立的地址空间用于自定义数据存储。 细看“m_data_2”,其先在MEMORY定义地址空间范围 （这里你可以自己划分内存，例如你可以把m_text再划分为更多的其它自定义空间，注意其实地址和范围） /* Specify the memory areas */ MEMORY { /* Flash */ m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000400 m_flash_config (RX) : ORIGIN = 0x00000400, LENGTH = 0x00000010 m_text (RX) : ORIGIN = 0x00000410, LENGTH = 0x0007FBF0 /* SRAM_L */ m_data (RW) : ORIGIN = 0x1FFF8000, LENGTH = 0x00008000 /* SRAM_U */ m_data_2 (RW) : ORIGIN = 0x20000000, LENGTH = 0x00007000 } 其次在SECTIONS中定义：".customSection"，其属于m_data_2。 /* Custom Section Block that can be used to place data at absolute address. */ /* Use __attribute__((section (".customSection"))) to place data here. */ .customSectionBlock ORIGIN(m_data_2) : { __customSection_start__ = .; KEEP(*(.customSection)) /* Keep section even if not referenced. */ __customSection_end__ = .; } > m_data_2 最后使用“customSection”的时候，可在程序中定义变量： __attribute__((section (".customSection"))  unsigned int i = 0; 变量“i”会被放置在“customSection”中，可以通过编译后的xx.map文件来查看变量“i‘所在的地址是否正确。 你的第二个问题是关于掉电保存数据，这个你完全可以通过S32K1的EEPROM实现，可参考该链接文章。 https://mp.weixin.qq.com/s?__biz=MzI0MDk0ODcxMw==&mid=2247486584&idx=1&sn=3b8651b928edd19c642b17838a8c75bd&chksm=e91248fede65c1e87214ce913baab45431f816d0bfd0362e00aea1ed4232f200d5ae2720cd71&scene=21#wechat_redirect

Can I use the same IRQ for multi core Hi helper I am using S32K358 multi core. Using Eirq for io interrupt. I have a question: I want core0 use eirq0 and core2 use eirq1 But the two irq channel trigger the same IRQ handler SIUL2_EXT_IRQ_0_7_ISR So there is the problem. If eirq0 and eirq1 both come. The Both core trigger  SIUL2_EXT_IRQ_0_7_ISR. Both core operate the same register. It will be cause bad software expectation.It will clear other non-init channel.   Do I understand OK?   please give me a help. Brs   Re: Can I use the same IRQ for multi core Hello @Licunhao , Your understanding is partially correct. On S32K3 devices, the SIUL2 external interrupt inputs are grouped into interrupt vectors. Therefore, EIRQ0 and EIRQ1 belong to the same interrupt group and are handled by the same grouped interrupt handler, for example SIUL2_EXT_IRQ_0_7_ISR. So, EIRQ0 and EIRQ1 cannot be used as two fully independent interrupt vectors. If the same SIUL2 interrupt group is routed or enabled on more than one core, both cores may enter the same interrupt handler and access the same SIUL2 registers. This can lead to unexpected behavior if the software does not implement proper multicore synchronization and ownership of the SIUL2 interrupt group. However, the SIUL2 interrupt flags are still available per individual EIRQ channel. A correct interrupt handler should check which EIRQ flag is pending and clear only the corresponding flag bit. The status flags should not be cleared globally or with an incorrect mask, otherwise another pending EIRQ flag could be affected. For a multicore application, I would recommend one of these approaches: Assign the whole SIUL2 interrupt group, for example EIRQ0 to EIRQ7, to one core only. This core should handle the grouped ISR and, if needed, notify another core by software or inter-core communication. If you need independent interrupt routing to different cores, use EIRQ channels from different SIUL2 interrupt groups, for example one channel from EIRQ0 to EIRQ7 and another channel from EIRQ8 to EIRQ15, if this is possible with your pin configuration. If both cores must access the same SIUL2 registers, the access must be protected by a proper multicore synchronization mechanism. But in general, a single-owner model for the SIUL2 interrupt group is cleaner and safer. Best regards, Pavel

S32K322 could not view registers when an error occurs Hi NXP Technology Team, The current software version of my project will malfunction after running for a period of time. However, when I try to view the registers, I am unable to do so and the simulation has been disconnected. The screenshot from Lautbach is attached below. I have checked that the 3v3 and 1v5 power supplies for the chips are all normal and show no abnormal waveforms. My situation seems to be similar to that of a previous post.@https://community.nxp.com/t5/S32K/S32K3-core-power-down-error-amp-running-bus-error/m-p/1853122 Could you please tell me how to troubleshoot and solve this problem? RTD version is SW32K3_S32M27x_RTD_4.4_4.0.0_P24_D2405, and it is located in the EB Tresos AUTOSAR. Johnson97_0-1786334605174.jpeg

External Data Abort when calling Clock_Ip_Init() Hi there, I'm attempting to initialise some peripheral clocks using the RTD and S32 DS mex tool. (Note im generating the code in a M7 project, but actually building and running for a A53 project) However, an external data abort occurs inside Clock_Ip_Init(). Specifically, the call stack looks like this: Clock_Ip_Init -> Clock_Ip_InitClock() -> Clock_Ip_DisableCmuFcFceRefCntLfrefHfref(). This appears to be the first attempt to actually write to the CMU peripheral memory. The fault occurs on a LDR instruction on memory 0x4005'C028 which according the S32G3 memory map correctly resides within the CMU memory area. At this stage, the MMU is not enabled, but my understanding is an external data abort occurs outside the CPU/MMU and is probably linked to secure access or a "locked" peripheral. Am i right in saying the CMU needs to be made "accessible" from the A53 core in some manner prior calling Clock_Ip_Init()? If so, could you advise on the steps to do so? Best regards, Jonny Device = S32G399A Compiler = S32DS_GCC _11_4 Core = Cortex A53 Re: External Data Abort when calling Clock_Ip_Init() Hi，jonnyWHIS Thank you for contacting us. Do you intend to create bare-metal code running on the S32G A53 core in the S32DS IDE? BR Joey

DSPI Communication timeout issue I am using the MPC5775B microcontroller with an SPI EEPROM. In my application, CAN messages are received continuously using interrupts, and SPI communication with the EEPROM is also interrupt-driven. Under heavy CAN bus traffic (e.g., five CAN IDs are received every 1 ms), any EEPROM read operation starts timing out. I am using the DSPI_MasterTransferBlocking() API with a timeout of 10 ms. I also tried increasing the timeout value significantly, but the read operation still fails. Interestingly, the behavior depends on the amount of data being read. When I attempt to read only a few bytes from the EEPROM, the SPI transfer times out. However, when I read an entire EEPROM page (256 bytes), the read operation completes successfully. I also observed that if CAN traffic is stopped, the EEPROM read operation succeeds without any issues. I verified the interrupt priorities, and both the CAN and SPI interrupts are configured with the same priority level (priority 0). I would like to understand: Why do small SPI EEPROM read operations time out under heavy CAN interrupt load, while larger (256-byte) page reads complete successfully? Could this be related to interrupt starvation, the implementation of DSPI_MasterTransferBlocking(), or the interaction between the CAN and DSPI interrupt handlers? Is there any known limitation or recommended configuration for using interrupt-driven DSPI transfers concurrently with high-frequency CAN interrupts on the MPC5775B? Additionally i debugged the issue by placing break points inside the DSPI_MasterTransferBlocking(),during the debug  status_t DSPI_MasterTransferBlocking(dspi_instance_t instance, const void * sendBuffer, void * receiveBuffer, uint16_t frames, uint32_t timeout) { DEV_ASSERT((uint32_t)instance < (SPI_INSTANCE_COUNT + DSPI_INSTANCE_COUNT)); status_t status; dspi_state_t * state = DSPI_state[instance]; if (state->status == DSPI_IN_PROGRESS) { return STATUS_BUSY; } state->isBlocking = true; (void)OSIF_SemaWait(&(state->dspiSemaphore), 0); status = DSPI_MasterTransfer(instance, sendBuffer, receiveBuffer, frames); if (status == STATUS_SUCCESS) { status = OSIF_SemaWait(&(state->dspiSemaphore), timeout); if (status != STATUS_SUCCESS) { (void)DSPI_AbortTransfer(instance); state->status = DSPI_TRANSFER_FAIL; return status; } } return STATUS_SUCCESS; } dspi transfer status getting success, but "OSIF_SemaWait" after dspi transfer getting timeout. Re: DSPI Communication timeout issue Hello, Based on the description, the DSPI transfer itself appears to be started successfully, because DSPI_MasterTransfer() returns STATUS_SUCCESS. The timeout occurs later while DSPI_MasterTransferBlocking() is waiting on OSIF_SemaWait() for the transfer-complete notification. Therefore, this symptom is more likely related to the interrupt/completion handling path than to a basic DSPI start failure. In the blocking DSPI API, the transfer is started and the caller waits until the DSPI interrupt/callback path releases the semaphore. If the semaphore is not released before the timeout expires, the API reports timeout and aborts the transfer. The fact that the issue appears only under heavy CAN interrupt load is an important clue. If CAN and DSPI interrupts are configured with the same priority, continuous CAN interrupt activity can delay DSPI interrupt servicing. For short EEPROM reads, the DSPI transaction completes very quickly, so the final DSPI interrupt and semaphore release are timing-sensitive. A longer 256-byte page read keeps the DSPI transaction active for longer and may allow the driver’s interrupt handling path to progress differently, which can explain why the larger transfer completes while the short transfer times out. Recommended checks: Configure the DSPI interrupt with higher priority than the CAN RX interrupt and repeat the test. Keep the CAN ISR as short as possible. Move CAN frame processing out of the ISR into a task/main-loop context if possible. Verify that the DSPI ISR is entered in the failing case. Verify that the DSPI transfer-complete callback or completion path releases state->dspiSemaphore. Toggle GPIOs or use trace points in: CAN RX ISR entry/exit DSPI ISR entry/exit DSPI transfer-complete callback before and after OSIF_SemaWait() Check that the blocking DSPI API is not called from an ISR or from any context where the DSPI interrupt cannot run. As a diagnostic experiment, try a polling-based DSPI transfer or DMA-based DSPI transfer. If polling/DMA works under the same CAN load, it further supports that the issue is in interrupt scheduling/completion handling rather than in the SPI bus itself. For EEPROM accesses, also confirm that the small-read sequence keeps the required command/address/dummy/read phase and chip-select behavior according to the EEPROM protocol. However, since the failure is reported at the semaphore wait, the first focus should be the DSPI completion interrupt path. In summary, the most likely direction is interrupt starvation or missed/delayed DSPI completion handling under high CAN interrupt load. The first practical test should be to raise the DSPI interrupt priority above CAN and instrument whether the DSPI ISR/callback posts the semaphore in the failing case. Best regards, Peter Re: DSPI Communication timeout issue Hello Peter, I tried changing the interrupt priorities as suggested. I configured the CAN interrupt priority to 10 and the DSPI interrupt priority to 1, but I am still seeing the same issue. Could you please help me with implementing DMA for SPI on the MPC5775B? If possible, could you share an example implementation or reference code for this MCU, along with the required DMA/SPI configuration settings? An example with the relevant configuration would be very helpful for us to understand the correct implementation. Thanks in advance for your support.

PPF0900AMBA1ES Hi NXP team, I'm working on a custom board based on the i.MX95 (MIMX9596, 19x19 package, LPDDR5), using the PPF0900AMBA1ES PMIC. Could you please confirm: 1.Does this part number ship with OTP already programmed, or is it a non-programmed engineering sample? 2.If it is non-programmed, what is the recommended procedure to program (or emulate) the OTP configuration for bring-up and evaluation purposes? 3.Is a reference OTP configuration file (.CFG) available for an i.MX95 + LPDDR5 (19x19) implementation that we could use as a starting point? For context, our schematic closely follows the i.MX95 EVK reference design (PF09 + PF5301 + PF5302), and we're currently doing initial power-on bring-up. Thank you. PMIC Re: PPF0900AMBA1ES  PPF0900AMBA1ES is OTP part which mean had already done OTP. https://www.nxp.com/docs/en/supporting-information/MPF0900AMBA1ES.zip OTP file please download from above link.

i.MX8M Nano PTP clock accuracy We are evaluating IEEE 1588 PTP for synchronizing multiple i.MX8M Nano systems that acquire data through the SAI interface. Our synchronization requirement is for the sampling time across multiple units to remain within 2 µs. On our hardware, ENET1_1588_EVENT0_OUT is routed externally back into GPT_CAPTURE1. The intended architecture is: Synchronize the ENET PTP Hardware Clock on each unit using hardware-timestamped PTP. Generate a periodic timing event using ENET1_1588_EVENT0_OUT. Capture that event with GPT to correlate the PTP clock to a local hardware timer. Use the measured relationship between the PTP timebase and the audio clock to adjust the AudioPLL on each slave unit so that its SAI sampling rate tracks the master unit. Maintain both sample-rate synchronization and a known phase/sample-index relationship between units. We found the NXP presentation “i.MX IEEE 1588 1PPS Test”, which shows how to enable the FEC 1588 output and notes that the general procedure applies to the i.MX8M family. However, the presentation demonstrates signal generation only and does not provide any specification or measured result for synchronization accuracy, PPS skew, output jitter, or unit-to-unit phase error. We have also reviewed the i.MX8M Nano datasheet and reference manual, but have not found a guaranteed timing specification for any of the following: Maximum synchronization error between two i.MX8M Nano ENET PTP hardware clocks when using hardware packet timestamping. Timing accuracy or jitter of ENET1_1588_EVENT0_OUT relative to the programmed ENET PTP timer compare value. Unit-to-unit variation in the latency from the ENET PTP timer compare event to the external EVENT0_OUT pin. Total uncertainty when ENET1_1588_EVENT0_OUT is looped back into GPT_CAPTURE1. Expected practical synchronization performance using the NXP Linux BSP and ptp4l. Could NXP provide any guidance on the following? Is there an undocumented characterization result or expected accuracy for the FEC PTP clock and ENET1_1588_EVENT0_OUT? Is the output edge generated entirely in hardware from the ENET PTP timer, with deterministic latency relative to the timer compare? Is the edge timing quantized only by ENET_TIMER_CLK_ROOT, or are there additional asynchronous clock-domain crossings that introduce variable latency? Is there a known maximum uncertainty for GPT input capture when capturing the looped-back event? Has NXP measured PPS-to-PPS skew between two i.MX8M devices synchronized over PTP? Is synchronization within 2 µs considered a reasonable expectation when using hardware timestamping and a controlled wired Ethernet network? Are there recommended ptp4l, FEC driver, clock-tree, or device-tree settings for obtaining the best synchronization accuracy on i.MX8M Nano? Is there any existing NXP example for disciplining the AudioPLL or an SAI media clock from the ENET PTP clock? We plan to verify the implementation experimentally by placing two boards on the same PTP network and measuring the time difference between their ENET1_1588_EVENT0_OUT signals using a two-channel oscilloscope. We would then separately measure SAI frame-clock or sample-clock alignment after implementing the AudioPLL control loop. Would this be the recommended method for characterizing the achievable PTP synchronization accuracy, or is there another internal signal, register, driver statistic, or NXP test method that would provide a better measurement? Any timing characterization data, internal design guidance, relevant application notes, or BSP examples would be appreciated.         i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Re: i.MX8M Nano PTP clock accuracy I searched and consult it, for imx8mn, we only validate the IEEE 1588 PTP support, doesn't do any Timing accuracy or latency testing, we can help customer bring up the IEEE 1588 PTP output setup, but couldn't offer these data since we haven't tested it yet

FRDM-MX95 PRO software packages? I was wondering what OS software packages will be available for the MX95 PRO?  Will Android AAOS be available for it as a demo image?  Is there anyone we can communicate with about what will specifically be available? Re: FRDM-MX95 PRO software packages? currently, only linux 6.18.20_2.0.0 demo images for imx95 frdm pro Embedded Linux for i.MX Applications Processors | NXP Semiconductors you can download demo images from the link above, for android, I checked the board file, the latest android 16.0.0_2.0.0 is based on kernel 6.18.20_2.0.0, so should support frdm pro, but this version android hasn't verified on this board yet, only 19x19 evk and 15x15 frdm joanxie_0-1785570929815.png Re: FRDM-MX95 PRO software packages? Any news if we will get android automotive on the frdm-mx95 or would we have to upgrade to frdm-mx95 pro version? Re: FRDM-MX95 PRO software packages? let me confirm auto android team again, the owner is on vacation, and come back office in next week, any update I will let you know it Re: FRDM-MX95 PRO software packages? refer to the link as below https://www.nxp.com/design/design-center/software/embedded-software/i-mx-software/android-automotive-os-for-i-mx-applications-processors:ANDROID-AUTO auto android demo images are only for imx95 19x19 evk Re: FRDM-MX95 PRO software packages? Are there any plans for android or AAOS?  Seems weird that the FRDM MX95 Pro wouldn't have an AAOS version especially since the Evaluation board 19x19 has been discontinued and benched.  Is there a reason the pro being a 19x19 processor wouldn't work as the evaluation board. Re: FRDM-MX95 PRO software packages? Thanks. There seems to be a genuine lack of Android automotive support. The frdm has a lot of potential but without additional support from nxp we are left on our own. From my understanding the evk has been dropped from support from toradex and discontinued. With the frdm pro having the same hardware there should be some support. We need the BSP which would make building the images a lot easier. Re: FRDM-MX95 PRO software packages? Is there any way i can contact them to ask a question? Or could they give us some instructions on how to compile the new frdm pro board, maybe they can provide the board package file to make it easier for us to compile? Re: FRDM-MX95 PRO software packages? unfortunately, got information from auto android team that they haven't any plan to support any imx95 frdm board Re: FRDM-MX95 PRO software packages? since they don't have plan to support this yet, I don't think they can offer any packages to build

Error reporting module MCU: S32K148 in 144 pin package RTD version: SW32K1_S32M24x_RTD_4.4_3.0.0_QLP03_D2507 S32 DS Version: 3.6.6 Target OS: Bare Metal Host OS: Windows With the above, I cannot find a module called "ERM" (or anything similar) in the driver module. I have looked in both both MCAL and Non-MCAL modules. Is the ERM supported as a driver module or should the user manipulate raw pointers, as it used to be with the older 'Processor Expert' based framework? Re: Error reporting module Hello @VaneB  Thank you for the follow up. So what you are saying is that these modules are supported in the SPD drivers only and not the freely available RTD. Is that right? Is there any reason why someone cannot use these modules just by bit-banging the registers of the module directly? I tried an example for the 'Processor Expert' driver model (using S32 DS v2.2) and it seemed to work. Re: Error reporting module Hi @durga_choudhury  For S32K1 devices, the Safety Peripheral Drivers (SPD) are available. These drivers include the Extended Microcontroller Error Manager (eMCEM), which supports memory error injection and detection through the Error Injection Module (EIM) and Error Reporting Module (ERM) hardware modules. For further information regarding the SPD, please contact your NXP representative or one of our authorized distributors in your region (Distributor Network | NXP Semiconductors). BR, VaneB Re: Error reporting module Hi @durga_choudhury  Yes, your understanding is correct. They are provided as a separate software package and is not included as part of the RTD. Regarding the reason for this separation, I am currently reviewing internaly. However, it is important to note that SAF and SPD were developed as safety-oriented software components in compliance with the ISO 26262 functional safety standard. This enables their integration into applications requiring functional safety support up to ASIL D. Re: Error reporting module Thank you very much for the update.

DUOX PKOC Good afternoon, I am trying to get a DUOX card to support the PKOC credential format.  Is there any doucumentation available for this?  I have the NFC Document from PKOC but it only shows the APDU structure to get the credential.  I cannot find any documentation for how the actual chip has to be programmed.  I have tried many steps and they all have failed.  The one that I am trying now uses the AppMasterTempKey in the application so the application can be a true ECC only application.  I was able to create the tempkey but the documentation is kind of confusing on how to disable it. Under Section 7.8.5.2.2 AppMasterTmpKey of the documentation the following is what is confusing.  Under section KeyChange it states in the first line it states that the temp key is not changeable with ChangeKey or ChangeKeyEV2.  So my question is how do I disable this TempKey so that it is a true ECC Application? I have tried changing the key to disable it as the docuentation states but I keep getting a 9D error.  Any help would be greatly appreciated. Steve Re: DUOX PKOC Have you tried the NXP RFIDDiscover software? Re: DUOX PKOC unfortunately, the information about the PKOC credentials on the DUOX is not available now.