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i.MX95/i.MX952 - LPDDR5/LPDDR4X memory compatibility guide

The purpose of this document is to provide extended guidance for selection of compatible LPDDR5 and LPDDR4x memory devices that are supported by the i.MX 95 and i.MX 952 processors. In all cases, it is strongly recommended to follow the DRAM layout guidelines outlined in the NXP Hardware Developer's Guides for the specific SoCs.

Please note that some of the LPDDR4x devices may not support operation at low speeds and in addition, DQ ODT may not be active, which can impact signal integrity at these speeds. If low speed operation is planned in the use case, please consult with the memory vendor the configuration aspects and possible customization of the memory device so correct functionality is ensured.

LPDDR5 - maximum supported densities

SoC	Max Data bus width	Maximum density	Assumed memory organization	Notes
i.MX 95	32-bit	128Gb/16GB	dual rank, dual channel device with 17-row addresses and x8 (byte mode) organization	1, 3, 7
i.MX 952	32-bit	128Gb/16GB	dual rank, dual channel device with 17-row addresses and x8 (byte mode) organization	1, 3, 7, 9

 

LPDDR5 - list of validated memories

Note: The memory vendors often list their devices as LPDDR5x in their high-level product information while in fact, they are in most cases backward compatible with the LPDDR5 mode. This may lead to the false impression that there are not so many LPDDR5 devices on the market. In such cases, it is strongly recommended to check the full datasheet to confirm if the device is in fact LPDDR5/LPDDR5x or LPDDR5x only. The SoC cannot be used with devices that only support the LPDDR5X mode.

The validation process is an ongoing effort - regular updates of the table are expected.

SoC	Density	Memory Vendor	Validated Memory Part#	Notes
i.MX 95	128Gb/16GB	Micron	MT62F4G32D8DV-023 FAAT:C	-
	64Gb/8GB	Samsung	K3KL9L90QM-MHCT	-
	32Gb/4GB	Samsung	K3KL8L80QM-MHCT	2
	32Gb/4GB	Samsung	K3KL8L80EM-MUCV	2
	64Gb/8GB	SK HYNIX	H58G66DK9VX067N	2
	64Gb/8GB	Micron	MT62F2G32D4DS-023 FAAT:C	2, 6
	32Gb/4GB	Micron	MT62F1G32D2DS-020 WT:D	2
	16Gb/2GB	Micron	MT62F1G16D1DS-023 IT:B	2
	64Gb / 8GB	Rayson	RS2G32LO5D24DB-31BT	2
	64Gb / 8GB	CXMT	CXDB6CCBM-MA-A	2
i.MX 952	128Gb/16GB	Micron	MT62F4G32D8DV-023 FAAT:C	9
	32Gb/4GB	Micron	MT62F1G32D2DS-020 WT:D	2

 

LPDDR5 - list of incompatible devices

The SoC cannot be used with memory devices that only support the LPDDR5x mode.

LPDDR4x - maximum supported densities

SoC	Max Data bus width	Maximum density	Assumed memory organization	Notes
i.MX 95	32-bit	128Gb/16GB	dual rank, dual channel device with 17-row addresses	1
i.MX 952	32-bit	128Gb/16GB	dual rank, dual channel device with 17-row addresses	1, 9

 

LPDDR4x - list of validated memories

The validation process is an ongoing effort - regular updates of the table are expected.

SoC	Density	Memory Vendor	Validated Memory Part#	Notes
i.MX 95	64Gb/8GB	Micron	MT53E2G32D4DE-046 AUT:C	5
	8Gb/1GB	Micron	MT53E256M32D1KS-046 IT:L	2
	128Gb/16GB	Micron	MT53E4G32D8GS-046	2
	64Gb/8GB	SK Hynix	H54G66BYYVPX104	2
	32Gb/4GB	Intelligent Memory	IMBG32L4KBB_V10	2
	48Gb/6GB	Micron	MT53E1536M32D4DT-046 WT:A	3, 8
	24Gb/3GB	Micron	MT53E768M32D4DT-053 AIT:E	3, 8
	8Gb/1GB	Samsung	K4U8E3S4ADGHCL	2
	32Gb/4GB	Intelligent Memory	IMBG32LK4BBG-046I	2
	32Gb/4GB	Alliance Memory	AS4C1G32MD4V-046BIN	2
	64Gb/8GB	Rayson	ATL4X8G32M2D-46IT	2
	64Gb/8GB	Rayson	ATL4X8G32M2D-46AIT	2
	64Gb/8GB	DW	DWCTB36HLC0	2
	8Gb/1GB	Alliance Memory	AS4C256M32MD4V-062BAN	2
	32Gb/4GB	ISSI	IS46LQ32K01S2A-046BLA2	2
	32Gb/4GB	Nanya	NT6AT1024T32AV-J1	2
i.MX 952	64Gb/8GB	Micron	MT53E2G32D4DE-046 AUT:C	9

 

LPDDR4/4X - list of incompatible devices

Note: This SoC supports LPDDR4x memory devices. 
This SoC is not compatible with memories that only support LPDDR4. 
Combo Devices that support both LPDDR4x and LPDDR4 are compatible with the SoC.

Note 1:

The numbers are based purely on the IP documentation for the DDR Controller and the DDR PHY, on the settings of the implementation parameters chosen for their integration into the SoC, SoC reference manual and on the JEDEC standards JESD209-5 (LPDDR5) and JESD209-4C/JESD209-4-1 (LPDDR4/4X). Therefore, they are not backed by validation, unless said otherwise and there is no guarantee that an SoC with the specific density and/or desired internal organization is offered by the memory vendors. Should the customers choose to use the maximum density and assume it in the intended use case, they do it at their own risk.

Note 2:

The memory part number did not undergo full JEDEC verification however, it passed all functional testing items.

Note 3:

Memory devices with binary densities (e.g., 1 GB, 2 GB, 4 GB) are preferred because they simplify memory management by aligning with system addressing schemes and reducing software complexity.

Note 4:

All memory parts are available at vendors unless stated otherwise. Checked Q2 2026

Note 5:

Memory device supports both LPDDR4x and LPDDR4, however can only be used in LPDDR4x mode

Note 6:

Not validated by NXP but confirmed working on a non NXP Board

Note 7:

The maximum density supported may change in the future when DRAM vendors make higher density options available

Note 8:

This DRAM part number is not recommended for new designs

Note 9:

This SoC is in Pre-Production

IMX95EVK