Recommendation for a camera CPU I am currently working on a camera-related project. Could you recommend a model among NXP's CPUs that meets the following three conditions? 1. CMOS sensor interface (CSI) of rt1060 2. MIPI-CSI2 interface of i.MX 8M 3. 1G Ethernet interface Best regards, Re: Recommendation for a camera CPU you can contact local DFAE, the third party company would offer such board and SW for your reference, for SW, you can refer to this https://github.com/nxp-imx/linux-imx/blob/lf-6.1.y/arch/arm/boot/dts/imx6qdl-sabresd.dtsi Re: Recommendation for a camera CPU Thank you for your help. Among the CPUs you recommended, the i.MX6Quad aligns with our concept. Is there an EVK utilizing the i.MX6Quad that includes both Parallel CSI and MIPI-CSI? Additionally, are there any EVKs that can be controlled using firmware (C/C++) rather than operating system? Re: Recommendation for a camera CPU ok, you should mean parallel camera port, you can refer to imx6q or imx8qxp i.MX Applications Processors | Multicore based on 32-bit and 64-bit Arm | NXP Semiconductors Re: Recommendation for a camera CPU We need a CMOS sensor interface (CSI) like RT1060. To connect a special camera, we need pixclk, vsync, hsync, and 16-bit data line. We also need the MIPI-CSI2 interface (like i.MX 8M) to connect a regular camera. Let me add another question. Can the CMOS sensor interface of the RT1060 be implemented in the i.MX8M series? Re: Recommendation for a camera CPU what kind of camera do you need connect? csi is controller and mipi csi is interface, current imx8mq and imx8mm use mipi csi interface and csi controller, so I don't know what kind dual camera you need connect, if you mean mipi csi, you can use imx8mp, which has dual mipi csi, but imx8mp use ISI or ISP, so pls give more detailed about your camera information Re: Recommendation for a camera CPU I'm looking for a CPU that supports the following three interfaces: CMOS sensor interface + MIPI-CSI2 interface + Gigabit Ethernet I need to integrate cameras that use the CMOS sensor interface and MIPI-CSI2 interface. (I will be using two cameras.) I plan to use Gigabit Ethernet as the external interface. Re: Recommendation for a camera CPU what is your detailed use case? and what do you need? I'm confused with your request

相机CPU推荐 我目前正在从事一个与相机相关的项目。 NXP的CPU中，能推荐一款满足下面三个条件的型号吗？ 1. rt1060的CMOS传感器接口（CSI） 2. i.MX 8M的MIPI-CSI2接口 3. 1G以太网接口 顺祝商祺！ 回复：推荐一款相机CPU 你可以联系当地的 DFAE，第三方公司会提供这样的板子和 SW 供你参考，对于 SW，你可以参考这个 https://github.com/nxp-imx/linux-imx/blob/lf-6.1.y/arch/arm/boot/dts/imx6qdl-sabresd.dtsi 回复：推荐一款相机CPU 感谢您的帮助。 在您推荐的CPU中，i.MX6Quad符合我们的理念。 是否有使用 i.MX6Quad 的 EVK，其中包含并行 CSI 和 MIPI-CSI？ 此外，是否有可以使用固件（C/C++）而不是操作系统进行控制的 EVK？ 回复：推荐一款相机CPU 好的，你应该是指并行摄像头端口，你可以参考imx6q或imx8qxp i.MX 应用处理器 | 基于 32 位和 64 位 Arm 的多核 | NXP 半导体 回复：推荐一款相机CPU 我们需要一个像 RT1060 这样的 CMOS 传感器接口 (CSI)。要连接特殊相机， 我们需要 pixclk、vsync、hsync 和 16 位数据线。 我们还需要 MIPI-CSI2 接口（如 i.MX 8M）来连接普通相机。 让我再补充一个问题。 RT1060的CMOS传感器接口可以在i.MX8M系列中实现吗？ 回复：推荐一款相机CPU 您需要连接什么样的相机？csi 是控制器，mipi csi 是接口，当前 imx8mq 和 imx8mm 使用 mipi csi 接口和 csi 控制器，所以我不知道您需要连接哪种双摄像头，如果您指的是 mipi csi，您可以使用 imx8mp，它有双 mipi csi，但 imx8mp 使用 ISI 或 ISP，所以请提供有关您的摄像头信息的更多详细信息 回复：推荐一款相机CPU 我正在寻找支持以下三种接口的CPU： CMOS传感器接口+MIPI-CSI2接口+千兆以太网 我需要集成使用CMOS传感器接口和MIPI-CSI2接口的相机。（我将使用两台相机。） 我计划使用千兆以太网作为外部接口。 回复：推荐一款相机CPU 您的详细用例是什么？您需要什么？我对您的请求感到困惑

カメラCPUの推奨事項 現在、カメラ関連のプロジェクトに取り組んでいます。 NXPのCPUの中で、以下の3つの条件を満たす機種をおすすめいただけますか? 1. rt1060のCMOSセンサーインターフェース(CSI) 2. i.MX 8MのMIPI-CSI2インターフェース 3. 1Gイーサネットインターフェース よろしくお願いいたします。 Re:カメラCPUの推奨事項 あなたは地元のDFAEに連絡することができます、サードパーティの会社はあなたの参照のためにそのようなボードとSWを提供します、SWについては、これを参照することができます https://github.com/nxp-imx/linux-imx/blob/lf-6.1.y/arch/arm/boot/dts/imx6qdl-sabresd.dtsi Re:カメラCPUの推奨事項 ご協力ありがとうございます。 ご提案いただいたCPUの中で、i.MX6Quadは当社のコンセプトに合致しています。 i.MX6Quad を使用した Parallel CSI と MIPI-CSI の両方を含む EVK はありますか? また、オペレーティング システムではなくファームウェア (C/C++) を使用して制御できる EVK はありますか? Re:カメラCPUの推奨事項 わかりました、あなたはパラレルカメラポートを意味するべきです、あなたはimx6qまたはimx8qxpを参照することができます i.MX アプリケーションプロセッサ |32ビットおよび64ビットArmに基づくマルチコア|NXPセミコンダクターズ Re:カメラCPUの推奨事項 RT1060のようなCMOSセンサーインターフェース(CSI)が必要です。特殊なカメラを接続するには、 pixclk、vsync、hsync、および16ビットデータラインが必要です。 また、通常のカメラを接続するには、MIPI-CSI2インターフェース(i.MX 8Mなど)も必要です。 もう一つ質問をさせてください。 RT1060のCMOSセンサーインターフェースはi.MX8Mシリーズに実装できますか? Re:カメラCPUの推奨事項 どのようなカメラを接続する必要がありますか?CSIはコントローラーで、MIPI CSIはインターフェースで、現在のIMX8MQとIMX8mmはMIPI CSIインターフェースとCSIコントローラーを使用しているので、どのようなデュアルカメラを接続する必要があるのかわかりませんが、MIPI CSIを意味する場合は、デュアルMIPI CSIを持つimx8mpを使用できますが、imx8mpはISIまたはISPを使用しますので、plsはカメラ情報についてより詳細に説明します Re:カメラCPUの推奨事項 次の3つのインターフェイスをサポートするCPUを探しています。 CMOSセンサーインターフェース+ MIPI-CSI2インターフェース+ギガビットイーサネット CMOSセンサーインターフェースとMIPI-CSI2インターフェースを使用するカメラを統合する必要があります。(カメラは2台使用します。 外部インターフェースとしてギガビットイーサネットを使用する予定です。 Re:カメラCPUの推奨事項 詳細なユースケースを教えてください。そして、あなたは何が必要ですか?私はあなたの要求と混乱しています

ArduinoのPortenta X8ハードウェアのサポート 私が関わっている研究プロジェクトでは、NXPのMIMX8MM6CVTKZAA SoCをベースにしたArduinoのPortenta X8モジュールを利用したカスタムハードウェアを作成することが決定しました。 https://docs.arduino.cc/hardware/portenta-x8/  プロジェクトの要件により、Arduinoのファームウェアを使用できません(使用したくもありません)。これまで、NXPのピン構成ツールを使用してmex構成ファイルの作成を開始することができましたが、ここからどのように進めるかがわからなくなります。 質問1:NXPプロセッサのJTAGを介したフラッシュオプションは何ですか?MCU-Link Debug ProbeはこのSoCで動作しますか? 質問2:これはEVK開発ボードではないため、ミニマリストのLinuxビルド(yocto)を作成するためのサポートを見つけるのに苦労しています。これにはどのようなサポートがありますか?portenta X8で実行できる新しいLinuxベースのプロジェクトを作成するにはどうすればよいですか? Re:ArduinoのPortenta X8ハードウェアのサポート MIMX8MM6CVTKZAAの内部メモリに画像をフラッシュする方法はありませんか?許してください。私はSWDでマイクロコントローラを操作することに慣れています。 Re:ArduinoのPortenta X8ハードウェアのサポート X8からX8のSTマイコンをフラッシュするための独自のソリューションを生成する必要があることは理解していますが、今はそれについて尋ねているわけではありません。私の質問は次のとおりです。 NXPは、EVKボードがなくてもこのNXPプロセッサにイメージをフラッシュできるようにするために、どのようなデバッグまたはプログラミングハードウェアを提供していますか?たとえば、NXPのMCU-LinkデバッグプローブはNXPデバイスをフラッシュするために機能しますか?

Support for Arduino's Portenta X8 Hardware I'm involved in a research project where it was decided to create custom hardware that utilizes Arduino's Portenta X8 module, which is based on NXP's MIMX8MM6CVTKZAA SoC. https://docs.arduino.cc/hardware/portenta-x8/  Due to project requirements, I can not use Arduino's firmware (nor do I want to). So far I've been able to get a start on creating the mex configuration file using NXP's pin config tool, but this is where I start to become confused on how to proceed. Question 1: What are my flashing options via JTAG for NXP processors? Does the MCU-Link Debug Probe work with this SoC? Question 2: Since this isn't an EVK development board, I'm struggling to find support for creating a minimalist Linux build (yocto). What support is there for this? How do I create a fresh Linux based project compatible to run on the portenta X8? Re: Support for Arduino's Portenta X8 Hardware Hi, Don't worry but there is no way. i.MX processors don't have internal memories because of a normal MPU architecture, You'd have to write it to eMMC, that's why I said it. It can be easily achieved through Serial Download. Regards, Re: Support for Arduino's Portenta X8 Hardware Is there no way to flash an image to internal memory on the MIMX8MM6CVTKZAA? Please forgive me. I'm used to working with microcontrollers over SWD. Re: Support for Arduino's Portenta X8 Hardware Hi, No, that'd be a third issue, you can't flash eMMC from JTAG. You must flash the board from Serial Download which may be possible (due to the ANX7625 addition) in USB-C connector. Otherwise, you could use USB1 from J1 and implement a Serial Download solution as the EVK reference. Please see the attached picture of the reference manual against Portenta BD. Regards, Re: Support for Arduino's Portenta X8 Hardware I understand that I'm going to have to generate my own solution for flashing the X8's ST MCU from the X8, but I'm not asking about that right now. My questions are: What debug or programming hardware does NXP provide that will allow me to flash an image to this NXP processor without having an EVK board? For example, will NXP's MCU-Link debug probe work to flash the NXP device? Re: Support for Arduino's Portenta X8 Hardware Hi, Thank you for your interest in NXP Semiconductor products, I just saw that Portenta HW has an additional STM32 that requires a FW which we could not create or flash. From the other side, if STM32 FW wasn't erased nor updated, you need to port the custom hardware (different DDR, different flash, different interfaces) for BSP layer. Having a BSP layer, you could create a basic yocto image as imx-image-core provided in our yocto implementation. Regards,

支持 Arduino 的 Portenta X8 硬件 我参与了一个研究项目，该项目决定创建利用 Arduino 的 Portenta X8 模块的定制硬件，该模块基于 NXP 的 MIMX8MM6CVTKZAA SoC。 https://docs.arduino.cc/hardware/portenta-x8/ 由于项目要求，我无法使用 Arduino 的固件（我也不想使用）。到目前为止，我已经能够开始使用 NXP 的引脚配置工具创建 mex 配置文件，但这就是我开始对如何继续感到困惑的地方。 问题 1：对于 NXP 处理器，我可以通过 JTAG 进行哪些闪存选择？MCU-Link 调试探针可以与该 SoC 配合使用吗？ 问题 2：由于这不是 EVK 开发板，我很难找到创建极简 Linux 构建（yocto）的支持。对此有什么支持？如何创建一个兼容在 portenta X8 上运行的全新基于 Linux 的项目？ 回复：对 Arduino 的 Portenta X8 硬件的支持 有没有办法将图像刷入 MIMX8MM6CVTKZAA 上的内部存储器？请原谅我。我习惯于通过 SWD 使用微控制器。 回复：对 Arduino 的 Portenta X8 硬件的支持 我知道我必须生成自己的解决方案来从 X8 刷新 X8 的 ST MCU，但我现在不想问这个问题。我的问题是： NXP 提供什么调试或编程硬件，使我能够在没有 EVK 板的情况下将图像闪存到此 NXP 处理器？例如，NXP 的 MCU-Link 调试探针是否可以用于刷新 NXP 设备？

i.mx93 jtag disable Hello, I'm starting evaluating i.mx93 board. I'd like to run WIN 10 IoT OS. I'm wondering what is the best way to disable JTAG in production. The result to achieve is that no one can estabilish a jtag connection and read memory. Is there a way to do so? Thanks. Evaluation Board Re: i.mx93 jtag disable Hi @marco95! No, all made for Windows 10 are something confidential due to the licenses that Windows has. If you need support to customize Windows 10 for your product should be under pro support. Sorry for the mistake! Best Regards! Chavira Re: i.mx93 jtag disable Hello, is there a guide explaining how to set-up the "password based autenthication" for JTAGC? Re: i.mx93 jtag disable Hi @marco95! We have the next user guide for iMX Windows 10: https://www.nxp.com/docs/en/user-guide/IMXWGU.pdf Best Regards! Chavira Re: i.mx93 jtag disable Hello, you mean "i.MX 93 Applications Processir Security Reference Manual"? I attached an image of the description found. How can I get more about the description? Are there any resource example to get started? Thanks Re: i.mx93 jtag disable Hi @marco95! Thank you for contacting NXP Support! You can consult the iMX93 Secure Reference Manual in the chapter "Secure Debug" to consult the best way to protect the SOC. Best Regards! Chavira

HSE S32K312 SHE based secure boot Hi, I am trying to achieve SHE based secure boot using S32K312 microcontroller. My aim is to load the keys to secure NVM of HSE. For loading the keys, I am generating M1, M2 and M3 messages using Miyaguchi-Preneel Compression protocol and AES encryption. I am getting HSE_SRV_RSP_INVALID_PARAM as a response from HSE.  Please check below details. 1) Microcontroller : S32K312_100MQFP 2) IDE: S32DS 3.5  3) SDK Version: PlatformSDK_S32K3_2022_03 Steps I am following : 1) Key Catalogue Formatting -> Getting  HSE_SRV_RSP_OK  2) Load She keys to Secure NVM             2.1. Loading ECU_MASTER_KEY                    2.1.1 Miyaguchi-Preneel Compression                    API : Crypto_Exts_MPCompression(constArr, (uint32)(AES_BLOCK_SIZE * 2), K1, ConstOutLen)                    Parameters: constArr -> const uint8_t *constArr This is input data                                         (uint32)(AES_BLOCK_SIZE * 2) -> Size of input data which is 32 bytes.                                         K1 ->  const uint8_t K1[AES_BLOCK_SIZE * 2]; -> output                                        ConstOutLen -> const uint32_t *ConstOutLen -> length of the output Any help on this topic is highly recommended. Thanks in advance.        Re: HSE S32K312 SHE based secure boot @lukaszadrapa  I am able to load keys to secure NVM by adding key data in non-cacheable memory. Re: HSE S32K312 SHE based secure boot Hi @lukaszadrapa, Can you share configuration file (.mex) for the SHE memory update protocol? So that I could check what I am doing wrong? Re: HSE S32K312 SHE based secure boot Some update: provided code was intended mainly for S32K1 and its CSEc. So, make sure that "CSEC" is not defined because EmptyKey needs to be all '0' for HSE: #ifdef CSEC static uint8 au8EmptyKey[SHE_KEY_SIZE] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; #else /* Array to be passed to Crypto driver during various operations as output buffer */ static uint8 au8EmptyKey[SHE_KEY_SIZE] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; #endif And next thing - CSEc on S32K1 has either 5 or 6 attribute key flags. SHE define 5 flags and there could be one more flag enabled (VERIFY_ONLY). HSE always expects 6 flags. But I can see that the code expects 5 flags only: aM2Plain[3] |= (flags & 0x1e) >> 1U; aM2Plain[4] |= (flags & 0x01) << 7U; You can update it to this: aM2Plain[3] |= (flags & 0x3c) >> 2U; aM2Plain[4] |= (flags & 0x03) << 6U; To understand where it goes - there's 28bit counter in M2 value and then the flags... But if you used flags=0, I don't think this will make a difference. Re: HSE S32K312 SHE based secure boot Still waiting... I'm also checking if there's an option to provide direct support from local FAE team. Re: HSE S32K312 SHE based secure boot Hi @lukaszadrapa  Have you got any update? Re: HSE S32K312 SHE based secure boot Hi @lukaszadrapa, Thank you for the clarification. I am getting HSE_SRV_RSP_KEY_INVALID while caling RetVal = Crypto_KeyElementSet(ECU_MASTER_KEY_ID, SHE_KEY_MATERIAL_ELEMENT_ID, KeyPram, 64) for this error it says in SHE, the key ID provided is either invalid or non-usable due to some flag restrictions. */ I am following example which you shared Crypto_CalculatedM1M2M3 and giving the flag value as 0 and configured the value as VERIFY ONLY from the configurator for the key. I tried by changing these 0 values to 1 for but still error is same. P.S. I am able to load the key in plain format. But when encryption is applied, error is coming. Re: HSE S32K312 SHE based secure boot You can set required flags when calculating M1-M3 values. The function is: void Crypto_CalculatedM1M2M3(CONST(uint8, AUTOMATIC) authKey[16], uint8 authKeyId, uint8 keyId, CONST(uint8, AUTOMATIC) key[16], uint32 counter, CONST(uint8, AUTOMATIC) uid[15], uint8 flags, VAR(uint8, AUTOMATIC) KeyPram[64]) Parameter 'uint8 flags' should be used. The order of bits is: For example, if you want to set VERIFY_ONLY, the 'flags' should be 0x01. There are no general rules which flags should be set, it depends on your requirements and on your application. Regards, Lukas PS. Still waiting for response from SW team... Re: HSE S32K312 SHE based secure boot Hi @lukaszadrapa , What attributes should we set while loading SHE key to secure NVM. In the RM758221-HSE-B Firmware Reference Manual - V2.1(2.1).pdf it is mentioned as below.   However, In the configurator I cannot see the WILDCARD and KEY_USAGE flag. Can you please guide me on this? Re: HSE S32K312 SHE based secure boot @lukaszadrapa Okay. Please let me know if you got anything on this topic. It's a bit urgent. Re: HSE S32K312 SHE based secure boot I'm not sure about this, I'm checking with SW team. It may take some time. Re: HSE S32K312 SHE based secure boot @lukaszadrapa , I tried with 1 as well but no change in results. Please check below configuration. Re: HSE S32K312 SHE based secure boot ECU_MASTER_KEY_ID is defined as 1 in the SHE spec. Isn't this the problem? Re: HSE S32K312 SHE based secure boot Hi @lukaszadrapa, I got HSE_SRV_RSP_OK for Crypto_CalculatedM1M2M3(). but while calling Crypto_KeyElementSet(ECU_MASTER_KEY_ID, SHE_KEY_MATERIAL_ELEMENT_ID, KeyPram, SHE_M1M2M3_SIZE) I am getting HSE_SRV_RSP_KEY_INVALID. ECU_MASTER_KEY_ID = 0 SHE_KEY_MATERIAL_ELEMENT_ID = 1 I have set HSE flag as VERIFY. What could be the reason? Can you please guide me? Re: HSE S32K312 SHE based secure boot Hi @lukaszadrapa  Thank you so much for providing me with test code. I will try this. Regards Shravani Re: HSE S32K312 SHE based secure boot Hi @shravani  I got attached test code which shows how to generate M1-M3 values using Crypto layer. There's a function Crypto_CalculatedM1M2M3(). Regards, Lukas

S32DS3.5 在ubuntu 中SDK识别不到 我在Ubuntu 22.04中安装的S32DS 3.5 IDE ，但在使用RTD时出现了如下的问题 PIT 组建可以添加进工程。但是会提示找不到对应的js，也不会生成代码。 RTD 的安装如下，之使用S32K3系列的组建（使用mcu为S32K312） 这个需要怎么处理呢？

i.MX8qxp can't config ADC_IN as GPIO output Hi, My question is, when I try to config ADC_IN1 as GPIO1_IO09, I cannot control it. This is my dts file. or When I set HIGH or LOW with GPIO1_IO09, it doesn't change. Below is what I tried to do. Even I read below article already, however it isn't help me. Solved: i.MX8 ADC_IN0 pin can't set as GPIO function - NXP Community Re: i.MX8qxp can't config ADC_IN as GPIO output I solved this. Due to incorrect pinctrl group, I couldn't. I referred below. Re: i.MX8qxp can't config ADC_IN as GPIO output Hello Alejandro, Thanks for your reply. I am using custom BSP using IMX8QXP. And I send to you device tree file attached. Please check "pinctrl_mipi_dsi_rst" part. Re: i.MX8qxp can't config ADC_IN as GPIO output Hello @hansung_jung  Could you please share what BSP are you using? Also, if possible, send the device tree file. Best regards. Salas.

USBPHY and USBHS in demo for USB audio device I noticed that the usb_device_audio_generator demo is not actually configuring the USBPHY and USBHS clocks (at least looking at the clock configuration tool). Is this expected? I'm using this demo as starting point for a project (USB audio device / UAC2) and I'm trying to understand whether I have to do that or that is not necessary. Thanks. i.MXRT 600 Re: USBPHY and USBHS in demo for USB audio device Hi @carlocaione, You are correct, the required USB clocks are not enabled using ConfigTools. If they were, their respective code would be present on the BOARD_InitBootClocks() routine on the very top of the main function. However, the clocks for our USB example codes are initialized later on the execution. In this case, they get initialized during the APPInit() routine, using a function called USB_DeviceClockInit(). Please look into this function and let me know if you have further inquiries about this topic. BR, Edwin.

XRDC in s32k344 running in lockstep mode HI There in XRDC module in a s32k344 running in lockstep , I read in manual that  master core could be CM7 or AHBP or AXI. So i am convinced that a s32k344 in lockstep mode is to referring to a AHBP core master access, is it true? in RTD4.0.0 in   Rm RTD module ,the  core types are the following: typedef enum { XRDC_CORE_M7_0 = 0x00U, XRDC_CORE_HSE = 0x03U, XRDC_CORE_M7_1 = 0x04U } Xrdc_Ip_MasterCoreType; It seams that lockstep configuration is not suited for these RTD ...? What is the situation about XRDC in lockstep mode for s32k344 ? best regards, Fabio Re: XRDC in s32k344 running in lockstep mode Hi There, Referring Figure8 Block Diagram page 24 Reference manual: It seems that CM7_1 accesses to bus via MDAC4, when XRDC is enabled. So in Lockstep mode i have to manage only MDAC0 (CM7_0)? Regards Fabio Re: XRDC in s32k344 running in lockstep mode Hi @FabioG  A small explanation of how Lockstep Core works is that two identical processors are initialized to the same state, and they receive the same inputs (code, bus operations, and asynchronous events), so during normal operation, the two processors operate in parallel, executing the same set of instructions simultaneously. The key feature of lockstep is that both cores execute the same instructions and compare their results at every step to ensure they match. If a discrepancy is detected, it indicates a potential error or fault in one of the cores, triggering a fault-handling mechanism. Because of this behavior, in lockstep, there is only a reference to M7_0 and M7_1 would be N/A.  B.R. VaneB

Uart Module of S32G274 Chip Callback Event: LINFLEXD_UART_IP_EVENT_IDLE_STATE mechanism Problem   As shown in the figure above, we see the Uart module timeout related functionality in the Uart module UM. So we Enable the function of "Uart Timeout Enable", generate the configuration file, compile and run in the project.   Within the project, we enable the "Uart Callback Capability" option, using a custom Callback function, where the Callback parameter Event is the enumerated type defined by the Uart module: 、   At the same time, the data on the Uart channel is sent at a frequency of 1Hz. Through Lauderbach debugging, we find that after the program starts running, the program triggers an interrupt of the event LINFLEXD_UART_IP_EVENT_IDLE_STATE and enters the Callback function. Uart then stops updating the data and looks at the register as follows:   Then, we do the corresponding processing under the event, found that when the event is triggered, re-call "Uart_AsyncReceive" function, so that the Timeout event is rolling triggered;   Can we understand the timeout mechanism of uart as follows:   When the Uart channel receives a frame of data, if the Uart is idle, the register UARTCTO will increase one by one. When the UARTCTO is equal to the preset register UARTPTO, the timeout event will be interrupted and RxEn register will be disabled, and the Uart will not actively resume the receiving state. If the Uart_AsyncReceive function is called again after the received data is processed, and the Uart is still idle, it will enter the timeout interrupt again.   We don't know if the chip's Uart mechanism is as we guessed. If not, please correct, so that we can better achieve business function.   We hope that the timeout mechanism of the Uart is as follows: The timeout interrupt only notifies the Uart when it changes from busy to idle. And you don't need to call the Uart_AsyncReceive  function again. In this case, the relevant interrupt is triggered. In this way, we can process the current frame data received when the interrupt is triggered, providing real-time data transmission. Hope NXP can have an expert answer, thank you!   如上图所示，我们在Uart模块的UM中查看到了关于Uart模块的超时的相关功能。于是我们将“Uart Timeout Enable”的功能使能，生成配置文件后，在项目中进行编译运行。   在项目内，我们使能了“Uart Callback Capability”选项，使用自定义的Callback函数，其中Callback的形参Event为Uart模块定义的枚举类型： 、   同时，在该Uart频道上的数据为1Hz的发送频率，通过劳德巴赫调试，我们发现，在程序开始运行之后，程序触发事件为LINFLEXD_UART_IP_EVENT_IDLE_STATE的中断，并进入了Callback函数内。然后Uart就不再更新数据了，查看了寄存器如下:   然后，我们又在该事件下做了相应的处理，发现当触发事件后，重新调用“Uart_AsyncReceive”函数，这样Timeout事件就是滚动触发；   是否可以这样理解uart的超时机制：   当Uart频道接收完一帧数据之后，如果Uart处于空闲状态，寄存器UARTCTO会逐一增加，当UARTCTO等于预设寄存器UARTPTO时，触发超时事件中断，关闭RxEn使能，Uart不会主动恢复接收状态。如果将接收后的数据处理完后，再次调用Uart_AsyncReceive函数，若Uart还是处于空闲时候，又会再次进入超时中断。   我们期望需求：   不知道该芯片的Uart机制是否如上我们猜测这样。如果不是请指正，便于我们更好的实现业务。我们希望的Uart的超时机制为：超时中断只做通知操作，且只在当Uart由繁忙转为空闲的时候，该种情况下会触发相关中断，不需要重复调用 Uart_AsyncReceive 函数。这样我们就能够在中断触发时候对收到的当前帧数据做处理，提供数据传递的实时性。     希望NXP能有专家解答，谢谢！ S32G2  GoldVIP Re: Uart Module of S32G274 Chip Callback Event: LINFLEXD_UART_IP_EVENT_IDLE_STATE mechanism Problem Thank you for your answer. That should answer some of our questions. The baud rate we use is the same, but the output data of the GNSS module is updated once per second, which can be understood in this way. Re: Uart Module of S32G274 Chip Callback Event: LINFLEXD_UART_IP_EVENT_IDLE_STATE mechanism Problem Hi, Thanks for your feedback. We still have some doubts on regards of the application, since UART can only be synchronized if both interfaces are set at the same baudrate, and at this moment we understand that they are not. Again, this seems to be a misunderstanding from our side, we do apologize. As for the overall situation, what you are mentioning under point 5 seems to be correct. If you are expecting to receive information, but you cannot wait for it, AsyncReceive is a non-blocking function which should trigger an interrupt once information is available under the respective buffers. Also, the following recommendations are shown under the S32G2 RM: For which, if the number of bytes to be received are not always the same, the recommendation is to receive byte per byte, to trigger the respective interrupt as expected. Please, let us know. Re: Uart Module of S32G274 Chip Callback Event: LINFLEXD_UART_IP_EVENT_IDLE_STATE mechanism Problem Thank you for your attention, the following questions to clarify and confirm: 1. The version of the RTD is S32_RTD_4.4_4.0.1_D2302, and the version of the Uart module is V4.0.1, AS4.4.0. 2. The development board we use is S32G-VNP-RDB2, namely GoldVIP. Our self-developed T-Box design and development based on reference 3. The example we use is the Autosar version provided by EB, AutoCore_OS, which is modified based on this project 4. The baud rate of the UART channel is set to 460800 BPS, but the GNSS module connected to the channel sends 1bps of data. In addition, the timeout module that we enable is under the LINFlexD module, and the UART mode (UARTCR[UART] = 1) is selected. 5. “The timeout feature will trigger an interrupt, and you are looking for receiving frames in the timeout interrupt?” Basically yes, it is also based on GNSS data frames of indefinite length. We hope to receive an interrupt at the end of receiving, and then the channel will continue to receive. The interrupt can only give a Notification, just like the notification in ADC module. Of course, recently we looked at the relevant manual introduction, it seems that the use of Uart at this stage is the need to constantly call Uart_AsyncReceive related functions to enable the receive register to open the channel, so that the data is constantly rolling reception.   Thanks! Looking forward to your reply Re: Uart Module of S32G274 Chip Callback Event: LINFLEXD_UART_IP_EVENT_IDLE_STATE mechanism Problem Hi, Can you let us know which RTD version are you using? Also, is this a custom board or an NXP reference board? Are you using any NXP examples as a base? As for the overall behavior, we might not understand it correctly. We understand the following: Speed of UART is 1 bps. You enabled the timeout feature under the LINFlexD module. Is this correct? As for the following comment: "We hope that the timeout mechanism of the Uart is as follows: The timeout interrupt only notifies the Uart when it changes from busy to idle. And you don't need to call the Uart_AsyncReceive  function again. In this case, the relevant interrupt is triggered. In this way, we can process the current frame data received when the interrupt is triggered, providing real-time data transmission." We don't understand the reason for the timeout callback. The timeout feature will trigger an interrupt, and you are looking for receiving frames in the timeout interrupt? Help us elaborate more on the application you are looking for, for us to better understand the implementation you require.  We do apologize. Please, let us know.

NX5P3090 FAULT 引脚电压（Vin=0V） 你好。我正在使用 NX5P3090 USB 电源开关，并希望将漏极开路 FAULT 输出拉至 1.8V 电源，即使开关没有输入（Vin=0V）也可以存在。当 Vin=0V 时，FAULT 引脚上存在 1.8V（通过 47kohm 上拉电阻）是否会导致开关出现任何不良行为？我看到这个引脚有 6V 的绝对限制，但我不清楚这是否适用于 Vin=0V 的情况。谢谢。-杰森 回复：NX5P3090 FAULT 引脚电压（Vin=0V） 好的，谢谢。——杰森

NX5P3090 FAULT pin voltage with Vin=0V Hello. I am using the NX5P3090 USB power switch and would like to pull the open-drain FAULT output to a 1.8V supply that can be present even if there is no input to the switch (Vin=0V). Will the presence of 1.8V at the FAULT pin (through a 47kohm pullup) when Vin=0V cause any undesirable behavior in the switch? I see that there is a 6V absolute limit on this pin but it isn't clear to me if this applies when Vin=0V. Thank you.  -Jason Re: NX5P3090 FAULT pin voltage with Vin=0V OK thank you.  -Jason Re: NX5P3090 FAULT pin voltage with Vin=0V Hi  1.8v pull up for this FAULT pin will be no problem without VIN.

PN7160 got TXLDO ripped output voltage Hello, I am working on PN7160 bring up on arm64 ubuntu 18.04. I have ported linux driver and nfcDemoApp Once I ran nfcDemoApp poll, of cause can not detect my Tag (NTAG213), and I probed the PIN14 (VDD TX QFN package--TXLDO ), I got a rippled output. please see the attached (nxp_nfc_pn7160_Vdd_Tx_ripple_voltage.png). I use CFG2 power (VDD_PAD = 1.8V, VDD_UP = VBAT = 3.8V), please see the attached (HW_power.png) and the configuration files. is it the HW issue or the SW configuration issue? all the capacitors are populated as requested. Re: PN7160 got TXLDO ripped output voltage The problem is fixed by changing an antenna. Indeed, there was no FR field before changing to a new one.  Thanks for all your support, Tomas. Re: PN7160 got TXLDO ripped output voltage Thanks, Tomas. I have tried the setting mentioned in AN13892.pdf, but it still can not detect the Tags/Cards. the error code (60 07 01 A1) still be seen. I added it in libnfc-nxp.conf, and tried all the possible values . NXP_RF_CONF_BLK_1={ 20, 02, 4C, 09, A0, 0D, 03, 78, 0D, 02, A0, 0D, 03, 78, 14, 02, A0, 0D, 06, 4C, 44, 65, 09, 00, 00, A0, 0D, 06, 4C, 2D, 05, 35, 1E, 01, A0, 0D, 06, 82, 4A, 55, 07, 00, 07, A0, 0D, 06, 44, 44, 03, 04, C4, 00, A0, 0D, 06, 46, 30, 50, 00, 18, 00, A0, 0D, 06, 48, 30, 50, 00, 18, 00, A0, 0D, 06, 4A, 30, 50, 00, 08, 00 A0, 0D, 06, 3C, 44, 55, 0A, 00, 00 } Re: PN7160 got TXLDO ripped output voltage Hello George,  I see you are getting -> 60 07 01 A1 (CORE_GENERIC_ERROR_NTF) Can you have a look here, please -> https://www.nxp.com/docs/en/application-note/AN13892.pdf Page 20. We can try to decrease the overall Rx gain to see if that will help or not.  BTW. about the RF Field detection, there are simple devices available (RF Field detectors) that might help you with NFC development. See e.g. here -> https://shop4nfc.com/products/rf-field-detector-for-nfc BR Tomas  Re: PN7160 got TXLDO ripped output voltage Any updates on this? I also attached the full log when run nfcDemoApp poll. Re: PN7160 got TXLDO ripped output voltage Hi Tomas, Thanks for the quick response. I have tried the NXP_EXT_TVDD_CFG_2, but I still got the rippled voltage, and still can not detect the card. how to check RF field?  Below are some errors when running nfcDemoApp poll 2023:03:02-15:12:14.678 nfa_dm_disc_notify_started 2023:03:02-15:12:14.678 nfaConnectionCallback: event= 30 2023:03:02-15:12:14.679 nfaConnectionCallback: NFA_RF_DISCOVERY_STARTED_EVT: status = 0 2023:03:02-15:12:14.679 PN54X - Read requested..... 2023:03:02-15:12:14.679 PN54X - Invoking I2C Read..... 2023:03:02-15:12:14.679 new state: DISCOVERY (1), disc_flags: 0x1 2023:03:02-15:12:14.680 nativeNfcTag_releaseRfInterfaceMutexLock: sRfInterfaceMutex unlock Waiting for a Tag/Device... 2023:03:02-15:12:39.671 PN54X - I2C Read successful..... 2023:03:02-15:12:39.672 len = 4 > 600701A1 2023:03:02-15:12:39.672 PN54X - Posting read message..... 2023:03:02-15:12:39.673 read successful status = 0x0 2023:03:02-15:12:39.674 NfcAdaptation::HalDeviceContextDataCallback: len=4 2023:03:02-15:12:39.675 NFC received ntf gid:0 2023:03:02-15:12:39.675 nci_proc_core_ntf opcode:0x7 2023:03:02-15:12:39.676 NFC_GEN_ERROR_REVT(0x500d) 2023:03:02-15:12:39.676 nfa_dm_disc_data_cback 2023:03:02-15:12:39.677 state: DISCOVERY (1), event: INTF_ERROR_NTF(10) disc_flags: 0x1 2023:03:02-15:12:39.677 new state: DISCOVERY (1), disc_flags: 0x1 2023:03:02-15:12:39.678 PN54X - Read requested..... 2023:03:02-15:12:39.678 PN54X - Invoking I2C Read..... 2023:03:02-15:12:44.453 PN54X - I2C Read successful..... 2023:03:02-15:12:44.454 len = 4 > 600701A1 2023:03:02-15:12:44.454 PN54X - Posting read message..... 2023:03:02-15:12:44.456 read successful status = 0x0 2023:03:02-15:12:44.456 NfcAdaptation::HalDeviceContextDataCallback: len=4 2023:03:02-15:12:44.457 NFC received ntf gid:0 2023:03:02-15:12:44.457 nci_proc_core_ntf opcode:0x7 2023:03:02-15:12:44.458 NFC_GEN_ERROR_REVT(0x500d) 2023:03:02-15:12:44.459 nfa_dm_disc_data_cback 2023:03:02-15:12:44.460 PN54X - Read requested..... 2023:03:02-15:12:44.460 PN54X - Invoking I2C Read..... 2023:03:02-15:12:44.461 state: DISCOVERY (1), event: INTF_ERROR_NTF(10) disc_flags: 0x1 2023:03:02-15:12:44.462 new state: DISCOVERY (1), disc_flags: 0x1 2023:03:02-15:12:52.215 PN54X - I2C Read successful..... 2023:03:02-15:12:52.216 len = 4 > 600701A1 2023:03:02-15:12:52.216 PN54X - Posting read message..... 2023:03:02-15:12:52.217 read successful status = 0x0 2023:03:02-15:12:52.218 NfcAdaptation::HalDeviceContextDataCallback: len=4 2023:03:02-15:12:52.218 NFC received ntf gid:0 2023:03:02-15:12:52.219 nci_proc_core_ntf opcode:0x7 2023:03:02-15:12:52.220 NFC_GEN_ERROR_REVT(0x500d) 2023:03:02-15:12:52.221 nfa_dm_disc_data_cback 2023:03:02-15:12:52.221 state: DISCOVERY (1), event: INTF_ERROR_NTF(10) disc_flags: 0x1 2023:03:02-15:12:52.222 new state: DISCOVERY (1), disc_flags: 0x1 2023:03:02-15:12:52.223 PN54X - Read requested..... 2023:03:02-15:12:52.223 PN54X - Invoking I2C Read..... Re: PN7160 got TXLDO ripped output voltage BTW. do you see some RF field ? Re: PN7160 got TXLDO ripped output voltage Hello George,  Please, check in libnfc-nxp.txt the PMU configuration.  Try the following  -> NXP_EXT_TVDD_CFG_2={20, 02, 0F, 01, A0, 0E, 0B, 11, 01, 02, B2, 00, B2, 1E, 11, 00, 10, 0C} # TVDD configurations settings # Allow NFCC to configure External TVDD # There are two possible configurations (0x01 or 0x02): # CFG1: Vbat is used to generate the VDD(TX) through TXLDO # CFG2: external 5V is used to generate the VDD(TX) through TXLDO NXP_EXT_TVDD_CFG=0x02 # CFG1: 3.3V for both Reader and Card modes #NXP_EXT_TVDD_CFG_1={20, 02, 0F, 01, A0, 0E, 0B, 31, 01, 01, 31, 00, 00, 00, 01, 00, D0, 0C} #NXP_EXT_TVDD_CFG_1={20, 02, 0F, 01, A0, 0E, 0B, 11, 01, 01, 01, 00, 00, 00, 00, 00, 10, 0C} NXP_EXT_TVDD_CFG_1={20, 02, 0F, 01, A0, 0E, 0B, 11, 01, 01, 01, 00, 00, 00, 29, 00, D0, 0C} # CFG2: VBAT2 to 5V and 4.7V for both Reader and Card modes NXP_EXT_TVDD_CFG_2={20, 02, 0F, 01, A0, 0E, 0B, 11, 01, 02, B2, 00, B2, 1E, 11, 00, 10, 0C}  BR Tomas 

NX5P3090 FAULTピン電圧(Vin=0V) こんにちは。NX5P3090 USB 電源スイッチを使用しており、オープンドレインの FAULT 出力を、スイッチへの入力がない場合でも存在できる 1.8V 電源 (Vin=0V) にプルアップしたいと思います。Vin=0VのときにFAULTピンに1.8Vが存在すると(47kΩのプルアップを介して)、スイッチに望ましくない動作が発生しますか?このピンには 6V の絶対制限があるように見えますが、これが Vin=0V のときに適用されるかどうかは私にはわかりません。ありがとうございます。-ジェイソン Re:NX5P3090 FAULTピン電圧(Vin=0V) わかりました。ありがとう。 -ジェイソン

VRSの不具合除去MC33814 MC33813、どのように機能しますか? 制御ビットVRSの不具合除去がありますが、説明があまり効果的ではないようです、それはどのように機能しますか? 小型エンジンドライバー

MC33814 MC33813 VRS 去毛刺如何工作？ 有控制位VRS De-glitch，但是没有描述好像很有效，它是如何工作的？ 小型发动机司机

MC33814 MC33813 VRS de-glitch how work? There is control bit VRS De-glitch, but no description seems very effective, How does it work? Small Engine Driver Re: MC33814 MC33813 VRS de-glitch how work? Issues searching for de-glitch. Is is there in datasheet. 5.7.2.5VRS deglitching filters The VRS input circuit has additional filters on the rising and falling edges of the input waveforms to reduce the effect of short transitions occurring during noise sensitive times. The deglitching filters are approximately 1 % of the last positive pulse period. The deglitch filters are enabled by setting the deglitch bit (bit 3) in the SPI VRS miscellaneous parameters configuration register. This bit is, by default, zero (0), meaning the deglitch filters are disabled. How can English become a world language, if is not spelled consistently, let alone phonetically?  Like Académie Française