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关于evkmimxrt1024_lpi2c_interrupt_b2b_transfer_master的问题 各位 想要尝试此示例,使用 RT1024 板作为主机,使用另一个 RT1064 板作为从机,连接方式如下:SCL:J18-12 至 Rt1064 J23 -6,SDA:J18-10 至 RT1064 J23-5,以及 GND:J19-14 - J23-7。 我把两个固件都下载到主板上,但是,它并没有像预期的那样运行,在下面的 RT1024 主传输函数行中 reVal = LPI2C_MasterTransferNonBlocking(示例_I2C_MASTER,&g_m_handle,&masterXfer); reVal = 900,而不是 kStatus_Success。所以它根本就无法转移。 我也同时使用 SDKv24.12 和 IDE24.12。 请帮忙! Ping
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evkmimxrt1024_lpi2c_interrupt_b2b_transfer_masterに関する質問 親愛なる皆様へ この例では、RT1024 ボードをマスターとして、別の RT1064 ボードをスレーブとして、SCL J18-12 から Rt1064 J23 -6、SDA: J18-10 から RT1064 J23-5、GND: J19-14 - J23-7 として接続して試してみたいと思います。 両方のファームウェアをボードにダウンロードしましたが、以下のRT1024マスター転送関数行で期待どおりに動作しません reVal = LPI2C_MasterTransferNonBlocking(EXAMPLE_I2C_MASTER, &g_m_handle, &masterXfer); reVal = 900 で、kStatus_Success ではありません。そのため、まったく転送されません。 SDKv24.12とIDE24.12の両方も使用しています。 助けてください! ピング
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iMX95 PDM信号の方向性 NXPコミュニティの皆さん、こんにちは。 i.MX95プロセッサを使用しており、PDM(パルス密度変調)信号について質問があります。i.MX95のPDM信号は双方向ですか、それとも入力専用ですか? 関連するドキュメントへの洞察や参照は大歓迎です。 ありがとうございます。
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LPC55S28 Schematic review request Greetings! I'm in the process of designing my first LPC55S28 board with fairly modest goals, as follows: Power the MCU with MCU-link pro debug probe Flash sample programs to MCU via debug probe Test blinking led, and button operations Test UART functionality thru VCOM facility of debug probe Here is the schematic, and I would appreciate your review comments - it would be great to have the board working "right in the first pass" as NXP doc says. I have two follow-up questions: Is ISP support needed for the board if flashing is done mainly with MCU-link pro? Is there a command line version of MCU-link pro to flash the device without having to invoke the IDE? Thanks much in advance! Re: LPC55S28 Schematic review request Hi @EdwinHz  Thank you. Re: LPC55S28 Schematic review request Hi @steve5528, I apologize for missing the schematic review. It looks OK! Re: LPC55S28 Schematic review request Hello @EdwinHz  Great. I will incorporate the ISP into schematics. Need to upgrade IDE so linkflash is installed. Hopefully you or someone at NXP can comment on the schematics as well. Re: LPC55S28 Schematic review request Hi @steve5528, 1. Technically you would not need ISP support, but it is highly recommended to include it for anything that might go wrong while programming the MCU. 2. You could use LinkFlash, which is a GUI based on LinkServer to flash NXP devices, which is based on command line. If you have the latest version of MCUXpresso installed (v24.12.148), you should also have LinkFlash v24.12.21 installed already. BR, Edwin.
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RT064 upnp 関数の例 こんにちは、NXPテクニカルサポート: MIMXRT1064DVL6Bチップを使用して、IARとAzure RTOS NetX Duoを使用してプロジェクトを構築しています。UPNP 機能を使用する必要があります。正常に実行できる適切な参照ルーチンを提供できますか? よろしくお願いいたします i.MXRT 106倍
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OV5640 working only on first MIPI CSI interface(CSI0) but not on another (CSI1) of i.MX 8M Plus evk Hello NXP community, issue : OV5640 working only on first MIPI CSI interface(CSI0) but not on another (CSI1) of i.MX 8M Plus evk. I'm using Yocto with LF6.6.3_1.0.0 bsp version. In imx8mp-evk.dts file i have seen some configuration for csi0 as below but not for csi1 ov5640_1: ov5640_mipi@3c { compatible = "ovti,ov5640"; reg = <0x3c>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>, <&pinctrl_csi_mclk>; clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; clock-names = "xclk"; assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; assigned-clock-parents = <&clk IMX8MP_CLK_24M>; assigned-clock-rates = <24000000>; csi_id = <0>; powerdown-gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>; reset-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; mclk = <24000000>; mclk_source = <0>; mipi_csi; status = "okay"; port { ov5640_mipi_1_ep: endpoint { remote-endpoint = <&mipi_csi1_ep>; data-lanes = <1 2>; clock-lanes = <0>; }; }; there is no similar configuration as above for csi1 so, I'm suspecting this is the reason why we are not able to use ov5640  on csi1(2nd csi) of imx8mp evk. Could anyone please let me know whether this reason is valid or not and also let me know the steps to update this dts file changes like how to compile and and add changes to image for verifying changes. Re: OV5640 working only on first MIPI CSI interface(CSI0) but not on another (CSI1) of i.MX 8M Plus you can try to use this dts file to enable ov5640 on the mipi csi2 https://github.com/nxp-imx/linux-imx/blob/lf-6.6.y/arch/arm64/boot/dts/freescale/imx8mp-evk-os08a20-ov5640.dts because the ov5640 in the mipi csi2 set the wrong powerdown pin and reset pin, for more detailed information, you also can refer the document as below "ov5640 support on imx8mp - NXP Community"
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IMXRT1171 - cannot Debug into RAM. Hi, I am using SDK ram linker. I defined the macro XIP_BOOT_HEADER_ENABLE=0. But I cannot debug. I created a new project from MCUxpresso, defined only the RAM memories, and checked the 'link application to RAM' option: With this created project, I can debug via RAM. I would replace the MEMORY definitions created by Xpresso with those of the SDK, but I still have not gotten any results. What are the differences between the SDK and the project created by mcuxpresso? Why can't I debug RAM in my own environment with the SDK? Re: IMXRT1171 - cannot Debug into RAM. Hello @Habib_MS, thank you for your interest. I found the solution to my problem. I added the following setting to the visual code launch configurations and now I can debug the ram. "overrideLaunchCommands": [ "monitor halt", "monitor reset", "load" ], Re: IMXRT1171 - cannot Debug into RAM. Hello @BrK_, In order to support you better, could you please provide me the next information when you presented the error? -SDK example that you cannot debug. -SDK version. -MCUXpresso version. -Debugger information.   BR Habib
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RT064 upnp功能示例 您好,NXP技术支持: 我正在使用 MIMXRT1064DVL6B 芯片通过 IAR 和 Azure RTOS NetX Duo 构建项目。我需要使用 UPNP 功能。能否提供相关可以正常运行的参考例程? 此致, i.MXRT 106x
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S32k314 GPIO setting inputbuffer and outputbuffer error S32DS version: S32DS3.5 RTD version: RTD 4.0.0 We are currently encountering some problems during the development of S32K314. When using "mex" to configure the GPIO output buffer, it is set to enable, but it seems to be disabled in the generated code. What could be the cause of this? This issue is not limited to one or two GPIOs. It seems that other communication pins are also experiencing similar problems. Are there any relevant solutions or information regarding this issue? mex pin setting: gen code: Re: S32k314 GPIO setting inputbuffer and outputbuffer error Hi @Alex_hsu, Please make sure either the Peripheral OSC or Peripheral PG groups are not declared either, as re-declaring already routed pins cause this issue. Best regards, Julián Re: S32k314 GPIO setting inputbuffer and outputbuffer error Hi after without setting the power and ground pins the other pins looks fine, but still 2 pins setting is error. This raises my concern about whether there might be other errors generated in the gen code by S32DS3.5 . Re: S32k314 GPIO setting inputbuffer and outputbuffer error It seems like that solved the problem, but why the error occurred? Re: S32k314 GPIO setting inputbuffer and outputbuffer error Hi @Alex_hsu, By default, all pins with Grey ticked in Pins tool is routed already, user don't need to add these pins to configuration pins list. I suggest removing all PowerAndGround out of pins list, as it already routed. Best regards, Julián Re: S32k314 GPIO setting inputbuffer and outputbuffer error I define all the 172 pins and here's the powerandground pin define setting Re: S32k314 GPIO setting inputbuffer and outputbuffer error Hi @Alex_hsu, Could you share your pin configuration? Are you enabling by chance the PowerAndGround dedicated group? How many pins are being configured?  Best regards, Julián 
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OV5640 は最初の MIPI CSI インターフェイス (CSI0) でのみ動作し、i.MX 8M Plus evk の別の (CSI1) では動作しません NXPコミュニティの皆さん、こんにちは。 問題 : OV5640 は最初の MIPI CSI インターフェイス (CSI0) でのみ動作し、i.MX 8M Plus evk の別の (CSI1) では動作しません。 私はLF6.6.3_1.0.0 bspバージョンのYoctoを使用しています。imx8mp-evk.dtsファイルでは、以下のようにcsi0の設定がいくつか見られますが、csi1の設定は見られません ov5640_1: ov5640_mipi@3c { compatible = "ovti,ov5640"; reg = <0x3c>; pinctrl-names = "デフォルト"; ピンctrl-0 = <&pinctrl_csi0_pwn>、<&pinctrl_csi0_rst>、<&pinctrl_csi_mclk>; クロック = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; クロック名 = "xclk"; 割り当てられたクロック = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; assigned-clock-parents = <&clk IMX8MP_CLK_24M>; 割り当てられたクロックレート = <24000000>; csi_id = <0>; パワーダウン-GPios = <&gpio4 1 GPIO_ACTIVE_HIGH>; リセット-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; MCLK = <24000000>; mclk_source = <0>; mipi_csi; status = "大丈夫"; ポート { ov5640_mipi_1_ep: エンドポイント { リモートエンドポイント = <&mipi_csi1_ep>; データレーン = <1 2>; クロックレーン= <0>; }; }; CSI1 には上記と同様の構成がないため、IMX8MP EVK の CSI1 (2nd CSI) で OV5640 を使用できないのは、これが原因ではないかと考えています。 どなたか、この理由が有効かどうか、また、このdtsファイルの変更を更新する手順を教えてください。また、コンパイル方法や変更を確認するためのイメージへの変更の追加方法などを教えてください。 Re:OV5640は最初のMIPI CSIインターフェイス(CSI0)でのみ動作し、i.MX 8M Plusの別の(CSI1)では動作しません このDTSファイルを使用して、MIPI CSI2でOV5640を有効にしてみてください https://github.com/nxp-imx/linux-imx/blob/lf-6.6.y/arch/arm64/boot/dts/freescale/imx8mp-evk-os08a20-ov5640.dts MIPI CSI2 の OV5640 は間違ったパワーダウン ピンとリセット ピンを設定しているため、詳細については、以下のドキュメントも参照してください 「imx8mpでのov5640のサポート - NXPコミュニティ」
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RT064 upnp function example Hello, NXP technical support: I am using a MIMXRT1064DVL6B chip to build a project using IAR and Azure RTOS NetX Duo. I need to use UPNP functionality. Can you provide relevant reference routines that can run normally? Best regards, i.MXRT 106x 回复: RT064 upnp function example OK! Thanks and Regards. 回复: RT064 upnp function example Hi @testmb1 , Thank you for your interest in the NXP MIMXRT product, I would like to provide service for you. I search internally, didn't find the related sample code. I also checked with our internal expert, and he also mentioned we don't have it. NXP SDK just provide the SDK lwip related demo, to other protocol, may need the customer to migrate by themselves. I found a segger reference resource online that you might consider if it would be helpful for your migratation. https://www.segger.cn/evaluate-our-software/nxp/nxp-lpcxpresso-om13098/ https://www.segger.cn/products/connectivity/emnet/add-ons/upnp/ Best regards, Gavin
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CAN TJA1145AT/FD/0Z Suffix differences The customer received the original material as shown below, and the label model is TJA1145AT/FD/0, This is inconsistent with the TJA1145AT/FD/0Z order item placed in the system.The customer wants to know the difference between the description of the suffix 0 and 0Z written documents,As well as the suffix about the different information reference of the packaging and testing plant,Thanks! Re: CAN TJA1145AT/FD/0Z Suffix differences Hello Louis, TJA1145AT/FD/0 that is visible on the label indicates the product type. TJA1145AT/FD/0Z is orderable part number of that product type in Z = 431 = Packing: REEL-Reel 13" Q1/T1 in Sulfur Barrier Bag https://www.nxp.com/docs/en/supporting-information/Packing_Letter_code.pdf Please refer to product page and the related datasheet: https://www.nxp.com/part/TJA1145AT#/ https://www.nxp.com/docs/en/data-sheet/TJA1145A.pdf Locations can be different. If any doubts please double check the locations details related to the particular customer's order with your CSR representative inside NXP. Have a nice day. Best regards Pavla 
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OV5640 仅在第一个 MIPI CSI 接口(CSI0)上工作,但不在 i.MX 8M Plus evk 的另一个(CSI1)上工作 大家好,恩智浦社区, 问题:OV5640 仅在第一个 MIPI CSI 接口(CSI0)上工作,但不在 i.MX 8M Plus evk 的另一个(CSI1)上工作。 我正在使用 LF6.6.3_1.0.0 bsp 版本的 Yocto。在 imx8mp-evk.dts 文件中,我看到了 csi0 的一些配置,如下所示,但没有看到 csi1 的配置 ov5640_1: ov5640_mipi@3c { 兼容=“ovti,ov5640”; reg =<0x3c> �; pinctrl 名称 = “默认”; pinctrl-0 = <&pinctrl_csi0_pwn>,<&pinctrl_csi0_rst>,<&pinctrl_csi_mclk>; 时钟=<&clk IMX8MP_CLK_IPP_DO_CLKO2>; 时钟名称=“xclk”; 分配时钟=<&clk IMX8MP_CLK_IPP_DO_CLKO2>; 分配的时钟父级=<&clk IMX8MP_CLK_24M>; 分配的时钟速率=<24000000> ; csi_id =<0> ; 断电 gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>; 重置gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; mclk =<24000000> ; mclk_source =;<0> mipi_csi; 状态 = “好的”; 港口 { ov5640_mipi_1_ep:端点{ 远程端点=<&mipi_csi1_ep>; 数据通道=<1 2>; 时钟通道=<0>; }; }; csi1 没有与上述类似的配置,因此,我怀疑这就是我们不能在 imx8mp evk 的 csi1(第二个 csi)上使用 ov5640 的原因。 有人可以让我知道这个原因是否有效,并让我知道更新此 dts 文件更改的步骤,例如如何编译以及如何将更改添加到图像以验证更改。 回复:OV5640 仅在 i.MX 8M Plus 的第一个 MIPI CSI 接口(CSI0)上工作,但不在 i.MX 8M Plus 的另一个(CSI1)上工作 您可以尝试使用此 dts 文件在 mipi csi2 上启用 ov5640 https://github.com/nxp-imx/linux-imx/blob/lf-6.6.y/arch/arm64/boot/dts/freescale/imx8mp-evk-os08a20-ov5640.dts 因为 mipi csi2 中的 ov5640 设置了错误的 powerdown 和 reset 引脚,有关更多详细信息,您还可以参考下面的文档 “ imx8mp 上的 ov5640 支持 - NXP 社区”
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Installation of latest SW32K1 LIN stack version 1.0.2 CD01 on S32DS v3.5 fails Hello, I have recently migrated to S32DS v3.5 and tried to integrate th e latest version of RTD, FreeRTOS and Linstack that is provided by NXP. I have attached a text file that covers the output provided under Help --> Installation Details in S32DS. The issue is that I try to install SW32K1 LIN stack version 1.0.2 CD01 but the installation is done just partially as in ticket. The installation window displays and after un-checking all ticks from the boxes the error message is displayed Cannot complete the install because one or more required items could not be found. Software being installed: LINSTACK S32K1 1.0.2.202209300724 (com.nxp.LINSTACK.S32K1.root.1.0.2.feature.feature.group 1.0.2.202209300724) Missing requirement: LINSTACK S32K1 1.0.2.202209300724 (com.nxp.LINSTACK.S32K1.root.1.0.2.feature.feature.group 1.0.2.202209300724) requires 'org.eclipse.equinox.p2.iu; com.nxp.RTD.S32K1XX.1.9.0.feature.feature.group 0.0.0' but it could not be found Does this mean, that this version of the Linstack is not compatible with the RTD version S32K1_S32M24X Real Time Drivers AUTOSAR R21-11 Version 2.0.0 P04 that is available online? Apparently version com.nxp.RTD.S32K1XX.1.9.0.feature.feature.group 0.0.0 is required but your download page offers not such version. Can you point out either how to fix this issue or which versions of RTD FreeRTOS Linstack  can be used with S32DS v3.5 together? Note, that the Linstack version 1.0.1 is also installed but  is still missing as shown in the image above. If you require more information let me know. Best regards M_SCH Re: Installation of latest SW32K1 LIN stack version 1.0.2 CD01 on S32DS v3.5 fails Hi @M_SCH  The SW32K1 SW32M24X LIN Stack version 1.0.2 with RTM qualification is already available and can be downloaded through S32K1 Reference Software > Automotive SW - S32K1_S32M24X - LIN Stacks > SW32K1 SW32M24X LIN Stack version 1.0.2.  This software version is compatible with the S32K1_S32M24X Real-Time Drivers ASR 4.4 & R21-11 Version 2.0.0 and S32 Design Studio for S32 Platform 3.5. B.R. VaneB
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FS26 RTD - FS0B pin release at start-up Dear all, in the function Sbc_fs26_ExitDebugMode(), defined in the file .\RTD\src\CDD_Sbc_fs26.c (S32K3XX FS26 AUTOSAR R21-11 Version 3.0.0), the function Sbc_fs26_ReleaseSequence() is called even if the device is not in Debug Mode. Since the call to the function Sbc_fs26_ExitDebugMode() cannot be excluded from execution, I get the FS0B pin released at the end of start-up. Thank you for your support. @pagdav Re: FS26 RTD - FS0B pin release at start-up I opened a ticket to NXP support and I received the response. The recognized issue has been resolved in the FS26 RTD driver version FS26 SBC AUTOSAR R21-11 Version 4.0.0 CD01. Re: FS26 RTD - FS0B pin release at start-up The function Sbc_fs26_InitDevice() is implemented in the RTD driver, auto-generated by NXP S32DS. I can't modify the RTD driver. Re: FS26 RTD - FS0B pin release at start-up Unfortunately I can't code to you about manual step to release FSXB then enter into normal mode,what I can do for you is provide the flow chart ,you have to do it by yourself,if don't fully understand the steps please let me know. Re: FS26 RTD - FS0B pin release at start-up I can't do it manually because it is done automatically by the function Sbc_fs26_InitDevice(). Please, check the code of the function Sbc_fs26_InitDevice() before to answer. Re: FS26 RTD - FS0B pin release at start-up You should refer to below flow chart whatever manually or automatically enter into normal mode from the Safety Outputs asserted state. Re: FS26 RTD - FS0B pin release at start-up Dear @guoweisun, my request is: I would like to switch manually from "Safety Outputs asserted" state to "Fail-Safe normal state" state using the function Sbc_fs26_ReleaseSequence(). In the actual RTD driver, the switch from "Safety Outputs asserted" state to "Fail-Safe normal state" state is automatic at the end of start-up. Functions call sequence: Sbc_fs26_InitDevice() -> Sbc_fs26_NormalFSSequence() -> Sbc_fs26_ExitDebugMode() -> Sbc_fs26_ReleaseSequence() Re: FS26 RTD - FS0B pin release at start-up Seems in that state can't enter normal mode by CAN message Re: FS26 RTD - FS0B pin release at start-up The SBC should be in the status "Safety Outputs asserted" (Figure 14 - Simplified functional state diagram). Re: FS26 RTD - FS0B pin release at start-up Hi   Could you please let me know which status the SBC in before receive CAN message? Re: FS26 RTD - FS0B pin release at start-up I would like to not enter automatically in NORMAL MODE at start-up. I need to enter in NORMAL mode when I receive i CAN message, using the function Sbc_fs26_ReleaseSequence() to release both pins. Re: FS26 RTD - FS0B pin release at start-up Before enter into normal mode you have to release FS0B/FS1B. Re: FS26 RTD - FS0B pin release at start-up Hi @guoweisun, I would like to not release the FS0B pin at start-up (NORMAL mode), but using the RTD drivers I always get FS0B released. This is due to the Sbc_fs26_ExitDebugMode() function which cannot be excluded from execution in the function Sbc_fs26_NormalFSSequence(). Thanks for your support. Re: FS26 RTD - FS0B pin release at start-up Hi  If I understand your questions correctly, you don't need enter into debug mode and exist into debug mode. You can see below flow chart of SBC,if you don't use emulation mode,you can skip this and after release RSTB directly enter into INIT mode.
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S32K344除了待机还有其他低功耗模式吗?比如睡眠模式? S32K344有睡眠模式吗? 回复:S32K344除了待机模式外,还有其他低功耗模式吗?比如睡眠模式? 你好@SCoder41 我们首先需要讨论S32K344和您的电源管理芯片之间的控制方法。如果这是IO口的控制方式,一般可以通过以下方法解决 1.Pad Keeping功能,S32K344的IO口支持Pad Keeping功能,该功能可以让S32K344的IO在Standby模式下保持RUN模式的状态,直到Pad Keeping功能关闭 2、可以通过一些外部开关电路来实现,比如根据你的电源管理芯片的特性设置一个常开或者常闭的开关电路,这样只有在RUN模式下才需要MCU控制。 回复:S32K344除了待机模式外,还有其他低功耗模式吗?比如睡眠模式? 我们的S32K344管理着给其他模块供电的电源管理芯片,需要S32K344来启用这些电源管理芯片。如果我从待机模式唤醒 S32K344,它将从重置处理程序执行系统重置以运行程序,并且我们主板上的其他模块将断电。我该如何解决这个问题? 回复:S32K344除了待机模式外,还有其他低功耗模式吗?比如睡眠模式? 我们的S32K344管理着给其他模块供电的电源管理芯片,需要S32K344来启用这些电源管理芯片。如果我从待机模式唤醒 S32K344,它将从重置处理程序执行系统重置以运行程序,并且我们主板上的其他模块将断电。我该如何解决这个问题?
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Is there any other low-power mode besides standby for S32K344, such as sleep mode? Does S32K344 have sleep mode? Re: Is there any other low-power mode besides standby for S32K344, such as sleep mode? Hi@SCoder41 We first need to discuss the control method between S32K344 and your power management chip. If this is a control method of an IO port, it can generally be solved by the following methods 1. Pad Keeping feature, the IO port of S32K344 supports Pad Keeping feature, which allows the IO of S32K344 to maintain the state in RUN mode in Standby mode until the Pad Keeping feature is turned off 2. It can be achieved through some external switch circuits, such as setting a normally open or normally closed switch circuit according to the characteristics of your power management chip, so that the MCU control is only required in RUN mode. Re: Is there any other low-power mode besides standby for S32K344, such as sleep mode? Our S32K344 manages the power management chips that supply power to other modules, and requires S32K344 to enable these power management chips. If I wake up S32K344 from standby mode, it will perform a system reset from the reset handler to run the program, and other modules on our board will lose power. How can I solve this problem? Re: Is there any other low-power mode besides standby for S32K344, such as sleep mode? Our S32K344 manages the power management chips that supply power to other modules, and requires S32K344 to enable these power management chips. If I wake up S32K344 from standby mode, it will perform a system reset from the reset handler to run the program, and other modules on our board will lose power. How can I solve this problem? Re: Is there any other low-power mode besides standby for S32K344, such as sleep mode? Hi@SCoder41 Actually there should be only RUN mode and Standby mode, but in RUN mode you can enter VLSRun by lowering the main frequency, but it is still RUN mode. https://community.nxp.com/t5/S32K-Knowledge-Base/S32K3-Low-Power-Management-AN-and-demos/ta-p/1527724
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Questions about the LPC51U68 USB Hi I want to use a software a approach to simulate the condition where USB VBus detects a connection, and modify it using the framework of the exmaple code 'dev_cdc_vcom_lite_bm'. The environment I'm working with is the LPC51U68 EVK. In the LPC51U68 Product data sheet, on page 85, there's a section that says:  'Remark: When a self-powered circuit is used without connecting VBUS, configure the USB_VBUS pin for GPIO (PIO1_6 or PIO1_11) and provide software that can detect the host presence through some other mechanism before enabling USB_CONNECT and the SoftConnect feature. Enabling the SoftConnect without host presence leads to USB compliance failure. ' Does this mean that other methods can be used to replace VBus detection of the host? For example, using a software flag to directly drive USB enumeration? I noticed in UM11071 that when both DCON (bit 16) and VBUSDEBOUNCED (bit 28) in DEVCMDSTAT are 1, the devices status changes to 'connected'. So, the code should include a condition that checks these two bits to ensure USB Initial or Run succeeds, leading to normal enumeration, right? Can you tell me the key word to focus on? LPC51Uxx USB Re: Questions about the LPC51U68 USB Hi @Harry_Zhang, Thank you for your response. Your method is feasible. However, I later noticed a pull-down resistor R75 near P1_6. Therefore, I performed an inverted operation on P1_6 and left JP10 open circuit, allowing the LPC51U68 to interpret 0 as 1. Re: Questions about the LPC51U68 USB Hi @hermus  On the LPC51U68 EVK, JP10 connects the USB VBUS signal to P1_6, which is the dedicated USB0_VBUS pin. When JP10 is shorted, the MCU can detect VBUS, set the VBUSDEBOUNCED bit, and proceed with USB enumeration. If JP10 is open, the MCU cannot detect VBUS, meaning the VBUSDEBOUNCED bit never gets set. Consequently, the internal pull-up on D+ will never be activated, causing enumeration failure. If you want to bypass the VBUS detection mechanism by simulating it in software. Since you’ve already tried configuring P1_6 as GPIO, you could manually set the VBUSDEBOUNCED bit using the DEVCMDSTAT register. However, the VBUSDEBOUNCED bit is read-only, meaning it’s not directly writable by software. you can try: Powering the Device Externally: Provide a constant VBUS signal through hardware to keep P1_6 high. Jumping Directly to Enumeration: Skip the VBUS check and directly set the DCON bit after USB initialization. For example, after calling USBD_API->hw->Init() and configuring endpoints, immediately call: USBD_API->hw->Connect(g_hUsb, 1); BR Harry Re: Questions about the LPC51U68 USB Hardware: OM40005 (LPC51U68 EVK) Software:     SDK Version: 2.15.00     Maifest Version: 3.14.0 In the example code under usb_examples > rom_dev_cdc_bm, I noticed the line USBD_API->hw->Connect(g_hUsb, 1) which seems to align with the SoftConnect functionality. To verify whether the Connect function works, I performed open-circuit and short-circuit tests on JP10 of the LPC51U68 EVK. When JP10 is shorted, enumeration works normally, but when it’s open, enumeration fails. Regardless of whether I configure P1_6 as USB0_VBUS or GPIO, after opening JP10 and monitoring D+ with a Logic Analyzer, I found that during operation, there’s no period where D+ goes high, meaning enumeration fails. What confuses me is that in UM11071, Chapter 22.4.3 SoftConnect, it states: 'The softConnect signal is implemented internally. An external pull-up resistor between USB_DP and VDD is not necessary. Software can control the pull-up by setting the DCON bit in the DEVCMDSTAT register. If the DCON bit is set to 1, the USB_DP line is pulled up to VDD through an internal 1.5 KOhm pull-up resistor.' So why does the pull-up only work when JP10 is shorted and P1_6 is set to USB0_VBUS? Additionally, the description in Section 22.4.3 seems inconsistent with the description of the DCON bit in Table 348 of the DEVCMDSTAT register. The DCON bit is described as: 'The connect bit must be set by SW to indicate that the device must signal a connect. The pull-up resistor on USB0_DP will be enabled when this bit is set and the VBUSDEBOUNCED bit is one.' It appears that the VBUSDEBOUNCED bit must also be set to 1, and since VBUSDEBOUNCED is tied to the VBus detection pin. Does this mean VBus detection is required for D+ to be pulled up? I’d like to ask: If I don’t connect JP10, what methods can I use in the LPC51U68 example code to ensure normal USB operation? Or is it absolutely necessary to short JP10 for VBus detection to enable USB to perform subsequent actions properly?
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スリープモードなど、S32K344のスタンバイ以外に低電力モードはありますか? S32K344にはスリープモードがありますか? Re:スリープモードなど、S32K344のスタンバイ以外の低電力モードはありますか? Hi@SCoder41 まず、S32K344と電源管理チップの間の制御方法について説明する必要があります。これがIOポートの制御方法である場合、一般的には次の方法で解決できます 1.パッドキーピング機能、S32K344のIOポートはパッドキーピング機能をサポートしており、パッドキーピング機能がオフになるまで、S32K344のIOはスタンバイモードのRUNモードの状態を維持できます 2.これは、電源管理チップの特性に応じてノーマルオープンまたはノーマルクローズスイッチ回路を設定するなど、一部の外部スイッチ回路を介して実現できるため、MCU制御はRUNモードでのみ必要になります。 Re:スリープモードなど、S32K344のスタンバイ以外の低電力モードはありますか? 当社のS32K344は、他のモジュールに電力を供給する電源管理チップを管理しており、これらの電源管理チップを有効にするにはS32K344が必要です。スタンバイモードからS32K344ウェイクアップすると、リセットハンドラからシステムリセットを実行してプログラムを実行し、ボード上の他のモジュールの電源が失われます。どうすればこの問題を解決できますか? Re:スリープモードなど、S32K344のスタンバイ以外の低電力モードはありますか? 当社のS32K344は、他のモジュールに電力を供給する電源管理チップを管理しており、これらの電源管理チップを有効にするにはS32K344が必要です。スタンバイモードからS32K344ウェイクアップすると、リセットハンドラからシステムリセットを実行してプログラムを実行し、ボード上の他のモジュールの電源が失われます。どうすればこの問題を解決できますか?
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i.MX 8M Plus Use 4G Internet function by the Quectel EM060K-GL M.2 module Hi I use i.Mx8mp motherboard The system uses Yocto bsp 5.15.71+g95448dd0dc9b Connect to Quectel EM060K-GL M.2 module The system correctly recognizes USB device by lsusb root@imx8mpevk:~# lsusb Bus 004 Device 002: ID 05e3:0620 Genesys Logic, Inc. GL3523 Hub Bus 004 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub Bus 003 Device 004: ID 0bda:b85b Realtek Semiconductor Corp. Bluetooth Radio Bus 003 Device 005: ID 2c7c:030b Quectel Wireless Solutions Co., Ltd. EM060K-GL Bus 003 Device 003: ID 3434:0a30 Keychron Keychron K3 Max Bus 003 Device 002: ID 05e3:0610 Genesys Logic, Inc. Hub Bus 003 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub Bus 002 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub Is there an App or GUI application that can implement 4G Internet access? Thanks i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Linux Yocto Project Re: i.MX 8M Plus Use 4G Internet function by the Quectel EM060K-GL M.2 module Hi, Thank you for your interest in NXP Semiconductor products, Currently there have not been tested LTE modules on our side, I quickly found this guide that can help you with the methodology to get to it. Regards
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