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为 PTN3222EUKZ 申请 IBIS 模型 Hi team, 请帮我获取 PTN3222EUKZUSB 接口 IC的 IBIS 模式。
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在 i.MX 8QuadMax 上使用私钥,同时保持私钥不可导出(不透明)? 您好, iMX8QM 是否支持使用 CAAM 的非对称密钥,同时保持私钥不可导出? 有了对称密钥,我就可以把它持久地存储在一个黑色 blob 中,作为黑钥匙导入系统,然后用 dm-crypt 来使用它。所有这一切,内核或用户空间都无法访问密钥的明文版本。 我希望能做类似的事情,但使用非对称私钥,并使用该密钥进行解密/签名。 这可能吗,有人可以推荐我参考应用笔记或类似的吗? i.MX 8 系列 | i.MX 8QuadMax (8QM) | 8QuadPlus 安全 Re: Use private key on an i.MX 8QuadMax while keeping it non-exportable (opaque)? 您好, 在内部网络安全团队确认后,仅限 PKCS #11 + OPTEE。 此致 哈维 Re: Use private key on an i.MX 8QuadMax while keeping it non-exportable (opaque)? 嗨, ,我忘了说,如果可能的话,我们希望不必使用 OPTEE。 Regard, Christian Re: Use private key on an i.MX 8QuadMax while keeping it non-exportable (opaque)? 您好, 你正在使用哪个版本的电路板支持包? 您可以使用 OPTEE + PKCS#11。 此致 哈维
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从 NXP GCC 10.2 迁移到 NXP GCC 11.4 的问题 你好 我在 S32 Design Studio(3.6.4 版)中创建一个新的 S32K3x 项目时遇到了问题。 我从 S32DS 扩展和更新中安装了恩智浦 GCC 10.2 和恩智浦 GCC 11.4 编译器。我还安装了 S32K3 PlatformSDK (RTD),版本为 6.0.0.202510100950。 当我按照新建项目向导(文件> 新建> S32DS 应用程序项目)进行操作时: 如果我选择 NXP GCC 10.2 作为编译器,PlatformSDK 就会如期出现在 SDK 选择窗口中。 如果我选择 NXP GCC 11.4 作为编译器,SDKs 选择列表则为空,我无法将 SDK 附加到我的项目。 我安装的 PlatformSDK (RTD) 版本是否与 NXP GCC 11.4 编译器不兼容?如果是,我需要下载并安装哪个特定版本的 S32K3 PlatformSDK (RTD),才能使其与恩智浦 GCC 11.4 编译器兼容? 感谢 Abhishek Re: Issue moving from NXP GCC 10.2 to NXP GCC 11.4 你好、 RTD 与 gcc v10.2 兼容-请查看 RTD 的安装手册/版本说明。 Re: Issue moving from NXP GCC 10.2 to NXP GCC 11.4 我使用的是 Ubuntu 24.04。
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i.MX 8QuadMax で秘密キーを使用しながら、それをエクスポート不可 (不透明) のままにできますか? こんにちは、 iMX8QM は、秘密鍵をエクスポート不可のまま、CAAM による非対称鍵の使用をサポートしていますか? 対称キーを使用すると、ブラック ブロブに永続的に保存し、それをブラック キーとしてシステムにインポートして、dm-crypt で使用CAN。カーネルやユーザー空間がキーのプレーンテキスト バージョンにアクセスすることはできません。 同様のことを、非対称の秘密鍵を使って行い、その鍵を復号化/署名に使用したいと考えています。 これは可能でしょうか?また、アプリケーションノートなどを参照できる方はいらっしゃいますか? i.MX 8ファミリ | i.MX 8QuadMax (8QM) | 8QuadPlus Security Re: Use private key on an i.MX 8QuadMax while keeping it non-exportable (opaque)? こんにちは、 内部セキュリティ チームの確認により、PKCS#11 + OPTEE のみ。 よろしくお願いします。 ハーヴェイ Re: Use private key on an i.MX 8QuadMax while keeping it non-exportable (opaque)? こんにちは、 可能であれば、OPTEE を使用する必要がないようにしたいということを言い忘れました。 尊重する、 キリスト教徒 Re: Use private key on an i.MX 8QuadMax while keeping it non-exportable (opaque)? こんにちは、 どのバージョンの BSP を使用していますか? OPTEE + PKCS#11 を使用できます。 よろしくお願いします。 Harvey
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Use private key on an i.MX 8QuadMax while keeping it non-exportable (opaque)? Hi, Does the iMX8QM support using asymmetric keys with CAAM, while keeping the private key non-exportable? With a symmetric key, I can persistently store the in a black blob, import it to the system as a black key and then use it with dm-crypt. All without the kernel or userspace being able to access the plaintext version of the key. I'd like to be able to do something similar, but with an asymmetric private key, and use that key for decryption/signing. Is this possible, and could someone perhaps refer me to an application note or similar? i.MX 8 Family | i.MX 8QuadMax (8QM) | 8QuadPlus Security Re: Use private key on an i.MX 8QuadMax while keeping it non-exportable (opaque)? Hi, With confirming internal security team, PKCS#11 + OPTEE only. Regards Harvey  Re: Use private key on an i.MX 8QuadMax while keeping it non-exportable (opaque)? Hi, I forgot to say that if possible we'd like to not have to use OPTEE. Regard, Christian Re: Use private key on an i.MX 8QuadMax while keeping it non-exportable (opaque)? Hi, Which version of BSP are you working with?  You may use OPTEE + PKCS#11. Regards Harvey
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eMMC 上の DTB とカーネル イメージを更新する簡単な方法はありますか? 開発中は、DTB とカーネル イメージを頻繁に更新する必要があります。 SD カードの使用は非常に便利です。カード リーダーは、FAT パーティション上の DTB とカーネル イメージを読み書きCAN。 しかし、eMMC の使用は非常に不便です。もっと簡単な方法はありますか? Re: Is there a simple way to update the DTB and kernel image on an eMMC? これがより良い方法だと私は信じています。 UUUを使わずにeMMC上のLinuxカーネルとdtbをアップグレードする方法 Re: Is there a simple way to update the DTB and kernel image on an eMMC? こんにちは、 fastboot モードに入るには次のものが必要です: 1. ボードの電源を入れ、任意のキーを押してブート フローを停止し、U-boot に入ります。 2. U-boot で次のコマンドを入力します。 fastboot 0 次のコマンドを使用して、UUU でファイルを送信します。 uuu -v -b fat_write mmc 0:1 例: uuu -v -b fat_write hello_world.elf mmc 0:1 hello_world.elf よろしくお願いいたします。 Re: Is there a simple way to update the DTB and kernel image on an eMMC? 前に述べたように、fastboot を使用してください。 ありがとうございます。 Re: Is there a simple way to update the DTB and kernel image on an eMMC? こんにちは、 何についておっしゃっていますか? DTB を fastboot でアップロードしますか、それとも SD カードから eMMC をフラッシュしますか、あるいはその両方ですか? よろしくお願いいたします。 Re: Is there a simple way to update the DTB and kernel image on an eMMC? 具体的にはどうすればいいのでしょうか? ガイダンス文書はありますか? ありがとうございます。 Re: Is there a simple way to update the DTB and kernel image on an eMMC? こんにちは、 U-boot から fastboot でボードを構成する DTB ファイルを更新し、UUU を使用してファイルを転送CAN。 イメージのフラッシュに関しては、UUU で再度フラッシュするか、SD カードから eMMC をフラッシュすることをお勧めしますが、このプロセスはより複雑だと思います。 よろしくお願いいたします。
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NXP GCC 10.2 から NXP GCC 11.4 への移行に関する問題 こんにちは、 S32 Design Studio バージョン 3.6.4 で新しい S32K3x プロジェクトを作成するときに問題が発生しています。 S32DS 拡張機能と更新から NXP GCC 10.2 と NXP GCC 11.4 の両方のコンパイラをインストールしました。また、S32K3 PlatformSDK (RTD) バージョン 6.0.0.202510100950 もインストールされています。 新しいプロジェクト ウィザード (ファイル > 新規 > S32DS アプリケーション プロジェクト) に従うと、次のようになります。 コンパイラとして NXP GCC 10.2 を選択すると、期待どおりに PlatformSDK が SDKs 選択ウィンドウに表示されます。 コンパイラとして NXP GCC 11.4 を選択すると、SDKs 選択リストが空になり、SDK をプロジェクトにアタッチできません。 インストールされている PlatformSDK (RTD) バージョンは、NXP GCC 11.4 コンパイラと互換性がありませんか?もしSOなら、NXP GCC 11.4 コンパイラと互換性を持たせるには、S32K3 PlatformSDK (RTD) のどのバージョンをダウンロードしてインストールする必要がありますか? ありがとう アビシェク Re: Issue moving from NXP GCC 10.2 to NXP GCC 11.4 こんにちは、 RTD は gcc v10.2 と互換性があります。RTD のインストール マニュアル/リリース ノートを確認してください。 Re: Issue moving from NXP GCC 10.2 to NXP GCC 11.4 私はUbuntu 24.04を使用しています。
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OpenSSL 3 和黑密钥? 你好, 我们希望能够使用 CAAM 支持 OpenSSL 的黑钥匙签名操作。 OpenSSL 3 建议使用名为"Provider" 的新接口。 如果不使用 OP-TEE 这样的工具,似乎就无法实现 CAAM"Provider" 。有人能证实或否认这一点吗? 如果还没有现成的实现,有什么建议,有没有官方支持将黑钥签名/验证操作内置到mbedTLS、OpenSSH、Open GPG等中。? 谢谢, Christian i.MX 8 系列 | i.MX 8QuadMax (8QM) | 8QuadPlus 安全 Re: OpenSSL 3 and black key? 还向内部网络安全团队进行了核实,如果没有 OPTEE,没有正面答案。 此致 哈维 Re: OpenSSL 3 and black key? 如果可能,我们希望不必使用 OPTEE。 你知道这可能吗? Regard, Christian Re: OpenSSL 3 and black key? 您好, 希望UG10163.pdf的 将 OpenSSL TLS 卸载到 OP-TEE PKCS#11 部分 有帮助。 此致 哈维
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Is there a simple way to update the DTB and kernel image on an eMMC? During development, we need to frequently update the DTB and kernel image. Using an SD card is very convenient; a card reader can read and write the DTB and kernel image on a FAT partition. However, using an eMMC is very inconvenient. Is there a simpler method? Re: Is there a simple way to update the DTB and kernel image on an eMMC? Here is the better way, I believe. How to upgrade Linux Kernel and dtb on eMMC without UUU  Re: Is there a simple way to update the DTB and kernel image on an eMMC? Hello, To enter on fastboot mode you need: 1. Turn on the board and stop boot flow pressing any key to enter in U-boot. 2. In U-boot enter next command: fastboot 0 Use the next command to send the file with UUU: uuu -v -b fat_write mmc 0:1 Example: uuu -v -b fat_write hello_world.elf mmc 0:1 hello_world.elf Best regards. Re: Is there a simple way to update the DTB and kernel image on an eMMC? Use fastboot, as you mentioned before. Thanks. Re: Is there a simple way to update the DTB and kernel image on an eMMC? Hello, What are you referring for? Upload DTB with fastboot or flash eMMC from SD card or both? Best regards. Re: Is there a simple way to update the DTB and kernel image on an eMMC? How to do this specifically? Is there any guidance document? Thanks. Re: Is there a simple way to update the DTB and kernel image on an eMMC? Hello, You can update the DTB file configuring your board in fastboot from U-boot and transfer the file with UUU. Regarding flash the image I suggest you re-flash with UUU or try to flash the eMMC from SD card but I think this process is more complicated.  Best regards.
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制限付きデータ パッケージ (SEC) の新しい場所 制限されたデータ パッケージは新しい場所に移動されます。詳細はこちらをご覧ください id:mcux-secure-tool [開始:2025年9月27日] [終了:2026年9月27日] 発表
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S32K144 FlexCAN 示例 RTD 3.0.0(DS 3.6.4首选) Lear 询问是否有关于使用 RTD 3.0.0 的 FkexCAN 的 S32K144EVB SW 示例。 首选 DS 3.6.4。 BR Stefano RTD 资料来源直接客户 Re: S32K144 FlexCAN example RTD 3.0.0 (DS 3.6.4 preferred) 你好,我是@StefanoGattazzo、 在此软件包版本中,有两个示例在 S32K144EVB 板上进行了测试。 打开 S32 Design Studio 后,进入"File -> New -> S32DS Project From Example" 并选择此示例。 顺祝商祺! 丹
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OpenSSL 3 とブラックキー? こんにちは、 私たちは、CAAM を使用して、署名操作用のブラック キーで OpenSSL をサポートできるようにすることに興味があります。 OpenSSL 3 では、「プロバイダ」と呼ばれる新しいインターフェースの使用が推奨されています。 OP-TEE のようなものを使用せずに CAAM「プロバイダー」を実装する準備はできていないようです。誰かこれを確認または否定できますか? すぐに実装できるものがない場合、何か提案はありますか。mbedTLS 、OpenSSH、OpenGPG などにブラック キー署名/検証操作を統合する公式サポートはありますか。 ありがとう、 キリスト教徒 i.MX 8ファミリ | i.MX 8QuadMax (8QM) | 8QuadPlus Security Re: OpenSSL 3 and black key? 社内のセキュリティ チームにも確認しましたが、OPTEE なしでは肯定的な回答は得られませんでした。 よろしくお願いします。 Harvey Re: OpenSSL 3 and black key? 可能であれば、OPTEE を使用する必要がないようにしたいと考えています。 それが可能かどうかご存知ですか? 尊重する、 キリスト教徒 Re: OpenSSL 3 and black key? こんにちは、 UG10163.pdfのセクション <10.4.8 OpenSSL TLS オフロードから OP-TEE PKCS#11 への pkcs11-プロバイダ 経由のオフロード> が参考になることを期待します。役に立つ。 よろしくお願いします。 Harvey
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LPC55S69 bricked after trying to enable SWO debug console I was trying to reconfigure a project to use SWO for the debug console on account of needing to reassign the FlexComm previously used for the debug UART (the manual could really use a more prominent warning about FlexComm3 not supporting I2S signal sharing) and after flashing my new firmware I lost all ability to debug and program the MCU. I tried my P&E Cyclone ACP with MCUX and in standalone mode, and I tried an MCU-Link and an LPC-Link2. None of them could establish a connection. I tested it out on my LPCxpresso55S69 board with its built-in LPC-Link and it did the same thing - bricked it with no ability to erase and try again. The solution for now is to pull the clock crystal, which halts execution before the code can get as far as the debug console init. How is this possible? Why are the debug interfaces not able to force the CPU into debug mode without letting them run first? Is there some workaround? I saved the 'poison' firmware image and I'm happy to share if you'd like to recreate the issue. Thanks, Scott Re: LPC55S69 bricked after trying to enable SWO debug console Hi @scottm  Thank you for identifying this issue and sharing your observations. We will review the documentation and IDE behavior to ensure better clarity and user experience going forward. BR Harry Re: LPC55S69 bricked after trying to enable SWO debug console Hi Harry, There are at least two different issues here. The blinky demo I shared illustrates the problem with the P&E driver. I've talked to P&E and they believe it's a problem with the erase function in their driver, which they're working on. The workaround for now is to set it to erase the whole chip rather than having it erased only the used areas. The other problem doesn't appear with a new project. I've found that the underlying problem is that the memory definition MCUX had for the LPC55S69 was wrong: It should be 0x9d800, not 0x98000. This is from a project created two years ago. The problem has been fixed in MCUX at some point since then, but the project was created with the incorrect setting and carried that over. If there was any mention of this in the MCUX release notes, I didn't see it. Now, what I see as an additional problem is the lack of any meaningful error message. This should generate some kind of warning that it's trying to program outside of the defined memory range. Instead we just get a generic failure: The original cause of all of this mess seems to have been bad documentation: The LPC55S69 uses 512-byte pages so 16 pages is 8 kB and the above cannot be correct. What's worse is that someone has looked at this and corrected the figure from 17 pages to 16 but didn't correct the size: If the memory map had simply stated the upper bound of the non-reserved flash area all of this could have been avoided. As it is, the datasheet still does not make the upper bound clear. If we subtract 16 pages from 0x9ffff we get 0x9dfff for the top of flash. If we subtract 10k we get 0x9d7ff for the top. The PFR documentation shows that the PFR starts at 0x9de00: Nothing in the datasheet would seem to account for the space between 0x9d800 and 0x9de00. The usable program memory range is one of the most basic parameters needed to program any MCU and the datasheet manages to obfuscate it so thoroughly that both NXP and P&E got the implementation wrong. To recap: P&E is fixing their driver. The workaround is to erase the whole device. Projects created with the wrong memory definition must be manually updated to reflect the correct range before the RedLink driver will work. As of rev 2.8, the UM11126 manual still contains incorrect information about the flash size. And there's a lot of room for improvement in how the IDE presents failures during the programming process. Scott Re: LPC55S69 bricked after trying to enable SWO debug console Hi @scottm  Thanks for your project. I have conducted multiple tests on my lpc55s69 EVK board. I can debug it successfully every time. I can mass erase  successfully every time. I am sorry i can not reproduce the issue you reported. How can i reproduce this issue? BR Harry Re: LPC55S69 bricked after trying to enable SWO debug console Here you go. Re: LPC55S69 bricked after trying to enable SWO debug console Hi @scottm  Sorry, Can you share  your project so that i can reproduce this issue? BR Harry Re: LPC55S69 bricked after trying to enable SWO debug console One more update before I give this a rest for the evening. I'm able to reproduce the problem, at least for P&E, by modifying the led_blinky demo. This not only fails the "Erasing ranges" operation, it also frequently crashes gdb. To reproduce, load up the led_blinky demo for the LPCxpresso55S69 board. Disable the managed linker script. Add some dummy data: __attribute__((used, section(".dummy"))) const char dummy_data[] = {1,2,3,4,5,6,7,8,10}; Edit the .ld files to add a high section: MEMORY { /* Define each memory region */ PROGRAM_FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x90000 /* 630K bytes (alias Flash) */ UPPER_FLASH (rx) : ORIGIN = 0x9d600, LENGTH = 0x20 SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x40000 /* 256K bytes (alias RAM) */ SRAMX (rwx) : ORIGIN = 0x4000000, LENGTH = 0x8000 /* 32K bytes (alias RAM2) */ USB_RAM (rwx) : ORIGIN = 0x40100000, LENGTH = 0x4000 /* 16K bytes (alias RAM3) */ SRAM4 (rwx) : ORIGIN = 0x20040000, LENGTH = 0x4000 /* 16K bytes (alias RAM4) */ } .dummy : ALIGN(4) { KEEP(*(.dummy)) . = ALIGN(4); } > UPPER_FLASH Build and upload. Twiddle dummy_data and one of the timer constants to make sure the code changes. Recompile and upload again and it fails. Scott Re: LPC55S69 bricked after trying to enable SWO debug console OK, I'm making some progress. I eliminated several things - tried a new board, another debug interface, a brand new cable, and tried using the LPCxpresso board as well. None of them would get past the "Range could not be erased" error. Now, when I said the erase range wasn't correct, or wasn't complete, that's because this project has a bootloader image included at 0x9b000 with some reserved space at 0x9a000 for bootloader commands. It wasn't showing the high range. So to check if it had something to do with that high range, I loaded the hello_world sample project and it erased and programmed just fine. It's not a hardware problem at all. Next, I switched over to the bootloader's own standalone project. This project has been untouched for a year or two. It links as a standalone application so that it can optionally be loaded on a blank device and will pick up its firmware update from external SPI flash, so it has a vector table of its own. I tried debugging it with the P&E debug configuration that hasn't been touched in ages. It failed with the same error: Erasing ranges ... Range 00000000-00001FFF Range could not be erased. Note that the 0000-1FFFF range only reflects the vector table and not the code. To test if this was a problem with non-contiguous memory areas, I created a new memory section called UNUSED_FLASH that occupies the rest of flash and used FILL(0x55) to give it some data. When it's linked, it shows it 100% full: Memory region Used Size Region Size %age Used VECTOR_FLASH: 304 B 1 KB 29.69% COMMAND_FLASH: 60 B 512 B 11.72% SVECT: 4 B 4 B 100.00% UNUSED_FLASH: 633344 B 633344 B 100.00% PROGRAM_FLASH: 9880 B 10236 B 96.52% SRAM: 9528 B 16 KB 58.15% USB_RAM: 0 B 16 KB 0.00% Finished building target: LPC55S69_Bootloader.axf I launched it again, with the same problem. It shows that it's erasing only the 0000-1FFF range, and it fails. So whatever's going on seems to be related to how it determines which ranges to erase and how it verifies the upload. This seems to be a recent thing (I'm running MCUX v25.6 build 136) and my hunch is that it feels like all of the other unreliable, quirky debug behavior I've encountered with MCUX because the IDE just has bad integration with gdb. Here's how the session ends: PEmicro GDB Launch Failure : Error during flash programming. Terminating debug session. PE-ERROR: Error downloading to the device. Terminating debug session. Disconnected from "127.0.0.1" via 127.0.0.1. Disconnection by port "52065" from 6225 Disconnected from "127.0.0.1" via 127.0.0.1. Disconnection by port "52070" from 7225 INFO: DAP IDCODE = 0x6BA02477 Target Disconnected. Except it doesn't actually end - I can hear the CPU fan kick on and arm-none-eabi-gdb.exe consumes 100% CPU time on one core. Here's gdb's output: 611,647 (gdb) 611,648 &"load B:\\\\home\\\\eb6\\\\bootloader\\\\Debug\\\\LPC55S69_Bootloader.axf\n" 611,648 ~"Loading section .text, size 0x130 lma 0x0\n" 611,648 26+download,{section=".text",section-size="304",total-size="1801748"} 611,648 26+download,{section=".text",section-sent="304",section-size="304",total-sent="304",total-si\ ze="1801748"} 611,648 ~"Loading section .commands, size 0x3c lma 0x9ae00\n" 611,648 26+download,{section=".commands",section-size="60",total-size="1801748"} 611,648 ~"Loading section .startvector, size 0x4 lma 0x9b000\n" 611,648 26+download,{section=".startvector",section-size="4",total-size="1801748"} 611,648 ~"Loading section .text, size 0x2690 lma 0x9b004\n" 611,648 26+download,{section=".text",section-size="9872",total-size="1801748"} 611,650 ~"Loading section .data, size 0x8 lma 0x9d694\n" 611,650 26+download,{section=".data",section-size="8",total-size="1801748"} 611,663 27interpreter-exec mi2 "-break-insert -t -f main" 611,788 28-list-thread-groups 615,695 &"Error finishing flash operation\n" 615,695 26^error,msg="Error finishing flash operation" 615,695 (gdb) 615,695 &"monitor selectcore 0\n" 615,695 @"Command Executed successfully: selectcore 0\r\n" 615,695 ^done 615,695 (gdb) 615,695 &"interpreter-exec mi2 \"-break-insert -t -f main\"\n" 615,702 &"warning: could not convert 'main' from the host encoding (CP1252) to UTF-32.\nThis normall\ y should not happen, please file a bug report." 615,702 &"\n" 615,705 ~"Note: automatically using hardware breakpoints for read-only addresses.\n" 615,705 ^done,bkpt={number="1",type="breakpoint",disp="del",enabled="y",addr="0x0009b138",func="main\ ",file="../source/LPC55S69_Bootloader.c",fullname="B:\\home\\eb6\\bootloader\\source\\LPC55S6\ 9_Bootloader.c",line="150",thread-groups=["i1"],times="0",original-location="main"} 615,705 27^done 615,705 (gdb) 615,705 29flushreg continue monitor refreshviews continue 615,705 28^done,groups=[{id="i1",type="process",pid="42000",executable="B:\\home\\eb6\\bootlo\ ader\\Debug\\LPC55S69_Bootloader.axf"}] 615,705 (gdb) 615,705 &"flushreg\n" 615,705 ~"Register cache flushed.\n" 615,707 30-list-thread-groups i1 615,721 29^done 615,721 (gdb) 615,721 &"continue\n" 615,721 ~"Continuing.\n" 615,721 ^running 615,721 *running,thread-id="all" 615,721 (gdb) 615,766 &"warning: Exception condition detected on fd 528\n" And if you'll recall from my last message, the GUI flash tool similarly doesn't properly register fault conditions. For now I'm up and running by excluding my bootloader from the .ld file. Let me know what you think about the non-contiguous memory erase/verify problem. And I would be happy to help your developers with testing fixes to the gdb integration because that's been a constant headache for years. Regards, Scott Re: LPC55S69 bricked after trying to enable SWO debug console There's definitely something more going on than pins getting reassigned. Debugging in MCUXpresso has always been very unreliable for me and I'd love to get to the bottom of it. It was working fine for the first half of the day. I made a minor change (enabling the FreeRTOS vApplicationMallocFailed() hook and defining a function with __BKPT(0)) and haven't been able to load and debug anything since, with either the Cyclone or LPC-Link2. The connection is fine. And in fact I'm able to connect with PROGACMP and erase the device, and verify that it's erased. It's coming back all 00 when on most devices I expect FF, so I don't know if that's right, but it's at least passing the blank check. Even with an erased device, I can't do anything with it. Here's what I get with the GUI flash tool. There are a few things going on here - first, the dialog indicates it completed when the log shows that it failed. And from the log you can see that it's got the wrong range, or at least not the complete range. I can also use the Cyclone to program a known-good image and the device runs, but I still can't do anything from MCUX. I'm going to reboot now and see if that makes any difference. Re: LPC55S69 bricked after trying to enable SWO debug console Hi @scottm  That might work for the LPCxpresso55S69 board, but it doesn't help with any of my own boards. With MON08 and BDM debuggers on older MCUs there was always a way to mass erase the flash no matter what was loaded - it'd go into debug mode right out of reset. Is SWD just not capable of that? This occurs because during the process of connecting the debugger to the chip, the chip is reset and then executes code from its flash memory. Since the customer's code modifies the SWD-related I/O functions during this process, it ultimately causes the debugger connection to fail. This is why erasing part of the flash at starting position resolves the issue. Regarding the size of the flash, it should be 631.5 KB, the last 17 pages(8.5 KB) are reserved, I am currently confirming this internally. BR Harry Re: LPC55S69 bricked after trying to enable SWO debug console Hi Harry, That might work for the LPCxpresso55S69 board, but it doesn't help with any of my own boards. With MON08 and BDM debuggers on older MCUs there was always a way to mass erase the flash no matter what was loaded - it'd go into debug mode right out of reset. Is SWD just not capable of that? In the course of troubleshooting this I've run into some other issues I'm following up on. When I wrote this bootloader back in 2023, I noticed that the LPC55S69 documentation was ambiguous about the top of usable flash memory - in one place it says 16 pages / 10 kB are reserved and in another it says 17 pages / 10 kB. 16 pages would be 8 kB and 17 pages is 8.5 kB, so obviously something's wrong there. As far as anyone can tell, the correct top of memory is 0x9d800. When I checked the debugger memory configuration files, the top was given as 0x98000, which is definitely wrong. I reported this in a thread back in 2023. Apparently those memory configurations were fixed at some point (though there's still no updated errata for the LPC55S69) but I discovered that my project file kept the old (incorrect) settings. While trying to sort it out, I ended up uninstalling all versions of MCUXpresso and Linkserver and deleted all of my launch configurations and then after reinstalling discovered that the project also seemed to be referencing an out-of-date Linkserver. P&E's drivers are harder to sort out because the Cyclone ACP isn't even listed on their site. Recreating the entire project with the latest IDE would take hours of work to manually document and recreate all of the settings and then do regression testing. Do you know of any other places that out of date debugger references could be hiding? Something's definitely still wrong. At one point the only way I could get it to program was by using the P&E standalone PROGACMP utility - which proved that the MCU was responding just fine with the same debugger and the same connections, but through gdb it simply wasn't working. At the moment the only interface I can get to work reliably with the project is an old LPC-Link2 I found in a drawer. To answer your question, this particular project is a multi-channel RoIP interface. Thanks, Scott Re: LPC55S69 bricked after trying to enable SWO debug console Hi @scottm  I think you  can put the chip into ISP mode and then use ISP commands to erase the first 1KB or 10KB of the flash to corrupt the firmware header, preventing the chip from jumping to the firmware, and then connect using a debugger. The isp pin is PIO0_5. And then use blhost command. By the way, what is your application? BR Harry Re: LPC55S69 bricked after trying to enable SWO debug console Hi Harry, That didn't seem to change anything. I tried with one of the boards I haven't pulled the crystal from yet, that I bricked with the bad firmware load, and it's still unable to connect. I've tried similar settings for the P&E interface. The only change from the firmware versions that have worked for years is this: SystemCoreClockUpdate(); DbgConsole_Init(DEBUG_CONSOLE_SWO_PORT, DEBUG_CONSOLE_SWO_BAUDRATE, kSerialPort_Swo, SystemCoreClock); Just to make sure we're on the same page, can you confirm that there should still be a way to erase and reload a device as long as flash protection isn't enabled? Thanks, Scott Re: LPC55S69 bricked after trying to enable SWO debug console Hi @scottm  The SWD debugging interface of LPC55S69 depends on the clock. Your code may have changed the debugging clock or PIN MUX when switching to an external crystal oscillator and enabling SWO in the later stage of main(), Causing the debugging port to lose clock, making it impossible for the debugger to reconnect or erase. So i think you can try to  Use your debug probe’s Connect under Reset on connection option.  In MCUXpresso IDE, BR Harry Re: LPC55S69 bricked after trying to enable SWO debug console Hi Harry, It's not enabling it early in the boot process. It happens in main(), after BOARD_InitBootPins() and BOARD_InitBootClocks(). That's the only way I was able to recover it - because it was after the switch to the external crystal, I could desolder the crystal and make sure it hung there forever. Shouldn't the debugger be able to at least perform a mass erase regardless of what the target is doing? How do I recover an MCU like this if I'm not able to stop it by pulling the crystal? Thanks, Scott Re: LPC55S69 bricked after trying to enable SWO debug console Hi @scottm  According to your description,  When you enabled SWO output  and reconfigured the debug console, you most likely modified the clock source or pin muxing in a way that unintentionally affected the SWD/SWO pins  or the  debug clock domain. When you reset and power up: If your firmware reconfigures clocks, pins, or secure settings very early (e.g. before SystemInit() finishes), the debugger never gets a chance to run before the MCU becomes unreachable. So i think you can disable swo in early boot. BR Harry
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S32K348 CAN FD Receive filter set Hello: I have studied this example( https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K358-FlexCAN-TXRX-ISR-S32DS35-RTD400-500...), receive can message: I want to set canid  filter, as sample i want to receive the message from  canid (0x123)  and I  write code as follow: but  now  I can not receive any message. Please take a moment to help answer, thank you! Re: S32K348 CAN FD Receive filter set thanks!resolve it Re: S32K348 CAN FD Receive filter set Hi@youngkin FlexCAN_Ip_SetRxIndividualMask_Privileged(INST_FLEXCAN_0, RX_MB_IDX, 0x7FF); // Exact match for standard ID   For standard ID (11-bit), use 0x7FF for full match. For extended ID (29-bit), use a 29-bit mask like 0x1FFFFFFF .
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How to enable dynamic debug messages during boot I have a kernel module (ti-sn65dsi83) that is built into the kernel. It seems to be loaded during boot, since I can get information about the module using "modinfo ti-sn65dsi83", however nothing happens on the I2C bus to initialize the lvds bridge. Therefor I need to get the kernel messages, however the messages are implemented as "dynamic debug messages" (See Dynamic Debug by Biyong Sun). I have enabled dynamic debug in the kernel configuration under "kernel hacking" -> "printk and dmesg options". What should be left in order to see the messages should be to write the following commands during u-boot: setenv DYNDBG "dyndbg =\\"file drivers/gpu/drm/bridge/ti-sn65dsi83.c +pfl\\"" setenv mmcargs 'setenv bootargs ${jh_clk} console=${console} root=${mmcroot} ${DYNDBG}' saveenv Setting the bootargs does change the messages printed in the console during boot. In the beginning there is a line saying "** 2128 printk messages dropped **" and it seems that some other dynamic messages get printed - but not related to ti-sn65dsi83. This leaves the questions: The kernel modules seems to be loaded during boot, but is there something more I should do to establish communication via I2C to the LVDS bridge? Can I expect that the kernel module automatically will initiate the communication and initialization of the LVDS bridge? When I don't see any messages related to ti-sn65dsi83, is it because there are no messages or am I still not seeing the dynamic debug messages? Regards Henrik Graphics & Display i.MX7ULP Linux Yocto Project Re: How to enable dynamic debug messages during boot Correct! then your module is build and is in the BSP, now you have to enable some modificacion in the dtb. Regards Re: How to enable dynamic debug messages during boot Hi Since I can see kernel module information when using "modinfo ti-sn65dsi83" I assume that is has been build and included in the kernel? If the kernel module is correctly build into the kernel, shouldn't the kernel module automatically pick the LVDS bridge from the Device Tree Source? From the source code I can that it expects "sn65dsi83", which is written in the dts. In the source code for the kernel module there is a function called "sn65dsi83_probe" which is responsible for toggling the enable pin as a part of the initialization procedure and parsing the device tree. And another function called "sn65dsi83_atomic_enable" that is setting the correct registers. I expected the probe function to be called and loaded together with module? But what about the "sn65dsi83_atomic_enable" when will that function be called and initialize the LVDS bridge? Regards Henrik Re: How to enable dynamic debug messages during boot Hello, If you don;t see any messages, then the module is not loaded. Check that the module is build with the kernel version you are working on. since you are trying to debug the GPU as well this is not going to be possible since gpu is binary and propietary. Regards
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PTN3222EUKZのIBISモデルのリクエスト こんにちは、チームの皆さん PTN3222EUKZ USBインターフェース IC の IBIS モードを取得する方法について教えてください。
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限制数据包 (SEC) 的新位置 受限代码包已移至新位置。详情请阅读此处 id:mcux-secure-tool [开始时间:2025年9月27日] [结束时间:2026年9月27日] 公告
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i can't detect RT1062 with MCU-Link Hello there, i am new to NXP products and i made a dev board using the RT1062 as its core componenet an i am having issues connecting to the it, i am using the MCU-link as a debbuger and i want to debug using SWD interface, i installed the drivers correctly and using LinkServer.exe in windows to try to probe the target. it detect the MCU link but not the RT1062 and i even tried with MCUXpresso IDE same result. i based my design on the MIMXRT1060-EVKB-DESIGNFILE-RevB1 schematics and i routed the swd pins directly to a connector. i am messing something out ?? and doest boot configuration matter in this case ? PS: all power rails are 3v3 besides USB which is 5V i.MXRT 106x Re: i can't detect RT1062 with MCU-Link Hi @yacineykr , Thanks for your updated information. Please kindly check the FlexSPI NOR Device Configuration setting. Especially you use the  second option pins.  Best Regards MayLiu Re: i can't detect RT1062 with MCU-Link Thanks for your reply, i did that and the power sequencing is respected.  i also tried to do a serial download by configuring the boot pins. i am using a NOR Flash from Winbond on FlexSPI second option pins (GPIO_AD_B1), the PC detects the MCU as an HID device using USB, but when i try to connect to boot ROM it tells me that the MCU has entered Flashloader but failed to configure external memory (i used MCU boot utility) Re: i can't detect RT1062 with MCU-Link Hi @yacineykr , Thank you so much for your interest in our products and for using our community. 1: I suggest you use an oscilloscope to check if the power-up sequence on the RT1060 board is correct. You can refer to MIMXRT105060HDUG for more detail information. 2: Please check whether you add PSWITCH RC delay. 3: Please compare the hardware design differences between your custom development board and the MIMXRT1060-EVKB development board. Wish it helps you. If you still have question about it, please kindly let me know. Best Regards MayLiu
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我无法通过 MCU-Link 检测到 RT1062 你好,我是恩智浦产品的新手,我用 RT1062 作为其核心组件制作了一个开发板,但在连接它时遇到了问题,我正在使用 MCU-Link 作为调试器,我想使用 SWD 接口进行调试,我正确安装了驱动程序,并在 Windows 中使用 LinkServer.exe 来尝试探测目标。它能检测到 MCU 链接,但检测不到 RT1062,我甚至用 MCUXpresso IDE 试过,结果都一样。 我的设计基于 MIMXRT1060-EVKB-DESIGNFILE-RevB1 原理图,并将 swd 引脚直接连接到连接器。我搞砸了??在这种情况下,启动配置重要吗? 注:除 USB 为 5V 外,所有电源轨均为 3V3 i.MX RT106x Re: i can't detect RT1062 with MCU-Link 你好@yacineykr、 感谢您提供的最新信息。 请查看 FlexSPI NOR 设备配置设置。 尤其是使用 第二个选项的插销。 顺祝商祺! MayLiu Re: i can't detect RT1062 with MCU-Link 感谢您的答复、 我照做了,电源排序得到了遵守。 我还尝试通过配置启动引脚进行串行下载。我在 FlexSPI 第二个选项引脚 (GPIO_AD_B1) 上使用 Winbond 的 NOR 闪存,电脑使用 USB 将 MCU 检测为 HID 设备,但是当我尝试连接启动 ROM 时,它告诉我 MCU 已进入闪存加载器但未能配置外部存储器(我使用了 MCU Boot Utility) Re: i can't detect RT1062 with MCU-Link 你好@yacineykr、 非常感谢您关注我们的产品并使用我们的社区。 1:我建议你使用示波器检查 RT1060 板上的开机顺序是否正确。更多详细信息,请参阅 MIMXRT105060HDUG。 2: 请检查是否添加了 PSWITCH RC 延迟。 3:请比较您的自定义开发板和 MIMXRT1060-EVKB 开发板之间的硬件设计差异。 希望它能帮到你。 如果您还有疑问,请告诉我。 敬上 MayLiu
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New location for Restricted Data Package (SEC) Restricted Data Package is moved to a new location.  For details:  read here  id:mcux-secure-tool [start:Sept 27 2025] [end:Sept 27 2026] announcement
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