PFE 未初始化 我们正在使用S32G_VNP_RDB3（S32G399A）。 我们使用分布式固件和驱动程序以及 Tresos 集成了该项目。 但是，在 Eth_43_PFE_PreInit 和 Eth_43_PFE_Init 函数中，我得到了 ETH_STATE_UNINIT，它没有初始化。 我不知道该修复什么，并且没有编译错误。 我正在分享代码，以便与遇到与我类似困难的人分享这个问题。 如果有人知道解决方案，请分享。

PFE not initialised We are using S32G_VNP_RDB3 (S32G399A). We integrated the project using the distributed firmware and drivers and Tresos. However, in the Eth_43_PFE_PreInit and Eth_43_PFE_Init functions, I get ETH_STATE_UNINIT, which does not initialize. I don't know what to fix, and there are no compilation errors. I'm sharing the code to share the problem with people who are having similar difficulties as me. If anyone knows of a solution, please share. Re: PFE not initialised_2 Hi, Thanks for your feedback. That is correct. There is a readme.txt file available under the example_application folder for the PFE-MCAL package which provides more information on regards of usage and compilation. Please, let us know. Re: PFE not initialised_2 Hi! among the PFE examples, PFE-DRV_S32G_M7_MCAL_1.2.0\example_application\MasterProject_RDB3 The examples in this folder will perform "Generate project" as normal in Tresos. However, I recently realized that I need to use a Makefile. Re: PFE not initialised Hi, For the information being provided, we understand that you are not using the NXP example itself, is this correct? Are you able to compile/run the NXP example without modifications? Please, let us know. Re: PFE not initialised Thank you so much for your response. I'm using the following version   PFE-FW_S32G_1.7.1   PFE_Firmware_1_7_1   PFE-DRV_S32G_M7_MCAL_1.2.0   SW32G_RTD_4.4_4.0.2 The project I posted was created by piecing together the header file from the PFE example program. Today, I realized I must compile the makefile to generate the S32G Studio project. However, I'm having trouble with the makefile. Could you please help me with this question? https://community.nxp.com/t5/S32G/makefile-error-in-PFE-example/m-p/1876417#M7056  Re: PFE not initialised Hi, Can you let us know which PFE-FW/PFE-MCAL/RTD version are you using? Are you using any NXP example? Please, let us know.

EVT0_B、EVT1_B、EVT2_B、EVT3_B、EVT4_BをLS1043の入力ピンとして構成 現在、LS1043で利用可能なすべてのインターフェースとピンを利用しており、ボードのバージョンを識別するために追加のGPIOが必要です。LS1043ARDBの回路図を見ると、EVT0からEVT4のピンは4.7Kレジスタでプルアップされており、どこにも使用されていないことがわかります。 LS1043のテクニカルリファレンスマニュアルでは、付録CはEPUレジスタの説明を表しています。ここで、EPU ベース アドレスは 2000_0000h。 EVT0_ADDR -> 2000_0000 + (50h + (0 x 4h)) = 2000_0050 (EPEVTCR0) EVT1_ADDR -> 2000_0000 + (50h + (1 x 4h)) = 2000_0054 (EPEVTCR1) EVT2_ADDR -> 2000_0000 + (50h + (2 x 4h)) = 2000_0058 (EPEVTCR2) EVT3_ADDR -> 2000_0000 + (50h + (3 x 4h)) = 2000_005C (EPEVTCR3) EVT4_ADDR -> 2000_0000 + (50h + (4 x 4h)) = 2000_0060 (EPEVTCR4) したがって、0 ビット DIR を 0b として設定すると、入力ピンとして設定され、EPRSRSVn からそのピンのステータスを読み取ることができます。 私の控えめな説明によるとENTn_Bピンが外部プルアップで構成されている場合、EPRSRSVnレジスタから値1を取得します。ENTn_Bピンが外部プルダウンで構成されている場合、EPRSRSVnレジスタから値0を取得します。 これを確認するように要求し、改善や変更があればお知らせください。 よろしくお願いします。 バールガブ・ジェイスワル Re:EVT0_B、EVT1_B、EVT2_B、EVT3_B、およびEVT4_BをLS1043の入力ピンとして構成します こんにちは@bhargavjayswal、 はい、このクエリでサポートします Re:EVT0_B、EVT1_B、EVT2_B、EVT3_B、およびEVT4_BをLS1043の入力ピンとして構成します ありがとうございました@SebastianG、 今日はもう1つのクエリを投稿しましたが、NXPコミュニティに反映されていません。クエリのタイトルは "LS1043A : EMMC GPT partitioning and boot process" です。これについても助けていただけませんか。 Re:EVT0_B、EVT1_B、EVT2_B、EVT3_B、およびEVT4_BをLS1043の入力ピンとして構成します こんにちは@bhargavjayswal、 ご回答が遅れてしまい申し訳ございません。 はい、このピンを入力として使用して、ピンの状態を検証できます Re:EVT0_B、EVT1_B、EVT2_B、EVT3_B、およびEVT4_BをLS1043の入力ピンとして構成します 更新していただきありがとうございます。 上記の構成に基づいて、このピンをu-boot中に入力gpioとして使用して、ピンの状態が高いか低いかを検証できますか? よろしくお願いします。 バールガブ・ジェイスワル Re:EVT0_B、EVT1_B、EVT2_B、EVT3_B、およびEVT4_BをLS1043の入力ピンとして構成します こんにちは@bhargavjayswal、 この構成は良さそうです

S32G-VNP-RDB2 Board network issues Problem description：Configure according to the 《S32G-VNP-RDB2 Ethernet Enablement Guide》，Set the IP and netmask for eth0 after entering LinuxBSP350：ifconfig eth0 192.168.1.20 netmask 255.255.255.0 ，And set the connected PC's IP to 192.168.1.10, with a netmask of 255.255.255.0 . Then Ping and find that can't connect, Please help me, what should I do next to enable Ethernet communication? #S32G-VNP-RDB2 Best wishes Re: S32G-VNP-RDB2 Board network issues Hello, @suda1684 Thanks for the feedback. Well, in order to avoid any uncertain settings, I suggest the following method to test the ethernet port of the board. Download the pre-built BSP images, for example, 35.0, you may reference the following method: - Sign in to your NXP account (link to NXP site: Automotive, IoT & Industrial Solutions | NXP Semiconductors) - Click on "My NXP Account" (top-right) and click on "Software Licensing and Support" under the "Licensing" section within the window it opens. - This will redirect you to another page. In this new page, select the option "View Accounts" under the "Software accounts" section. - This will again redirect you to another page. On this page, you should see an "Automotive SW - S32G - Linux BSP (Cortex-A53)" option, click on it. In there, you should see all the available BSP versions for your account. If you don't see the specific version you are looking for, help us contacting your local NXP FAE/representative, for them to start the required process to provide the access. While downloaded, unzip it and find the corresponding images for RDB2 SD boot: fsl-image-auto-s32g274ardb2.sdcard Use the following command to flash the binary to the SD card: sudo dd if=./fsl-image-auto-s32g274ardb2.sdcard of=/dev/sdh bs=1M && sync Insert the SD card to the board, and boot the board till Linux prompt, test it by setting corresponding Ips I ever tested it from my local board, no issue found on using the ethernet port you mentioned. Hope it helps.   Best Regards Chenyin Re: S32G-VNP-RDB2 Board network issues hello,Chenyin Thanks for your reply, The BSP uses the version that was already installed in the SD card at the time of receipt. The settings made in BSP are done according to the configuration in the file "S32G-VNP-RDB2 Ethernet Enablement Guide", and the corresponding configuration and pri parameters in U-BOOT are displayed in the figure below Re: S32G-VNP-RDB2 Board network issues Hello, @suda1684 Thanks for the questions. May I know if you were using the pre-built BSP35.0 images or not to boot the system? Besides, any other settings made from u-boot? I just tested the eth0 with default BSP35.0 images and found no issues on it. Best Regards Chenyin

About pin state after deinit Will the pin state change to default state that I configured in S32DS after the driver is deinitialized? For example, I configured a pin to PWM, output, initial value: low. And now my system is entering STR and I'm going to deinitializing PWM driver, will the pin be "output low" after deinitialization? Thanks. Re: About pin state after deinit If the peripheral gets disabled, the pins is routed to a disabled peripheral, so in general, yes. Regards, Daniel Re: About pin state after deinit Hi @danielmartynek, Thanks for the explanation. I get it. By the way, if I don't call Siul2_Port_Ip_Init() to initialize those pins, I just disable the drivers and use a multimeter to measure the voltages of those pins, does it mean the voltages are indeterminate? Re: About pin state after deinit Hi @jetty_1012, The Siul2_Port_Ip_Init() initializes the MSCR, IMCR and GPDO registers if the pins. The "initial value" applies to pins in the GPIO mode. The other drivers, such as the eMIOS, do not change the configuration, that means that even if the eMIOS is disabled, the pins are still routed to the eMIOS in the MSCR, IMCR registers. If you want to be sure the pins are set as GPIO with some defined values, you can call the Siul2_Port_Ip_Init() again with a different structure. The configuration tool can generate more structures. Regards, Daniel Re: About pin state after deinit Hi @danielmartynek , thanks for your reply. I'm using S32K312. My SW version is 3.0.0.  Thanks. Re: About pin state after deinit Hi @jetty_1012, What MCU part and driver version do you use? Can you share the code? How do you deinitialize the ports? Regards, Daniel

s32k 中 SPI 的 IB 与 EB（RTD 3.0.0.0） 我们正在使用 EBtresos 工具 autosar 包 RTD 3.0.0.0 配置 SPI。有两种类型的缓冲区可配置：内部缓冲区和外部缓冲区。 1.这个内部缓冲区是我们软件中Spi驱动文件定义的数组吗？就速度而言，它与用户定义的数组有何不同？ 2. 哪个更好/更高效？IB或EB 3. 对于 IB，我们必须首先使用 Spi_WriteIB 将用户定义数组写入 IB，然后执行 Spi_SyncTransmit....而在 EB 中，我们可以使用 Spi_SetupEB() 将此用户定义数组设置为缓冲区，然后执行 Spi_SyncTransmit 进行同步传输。哪个更快/更好，我认为只有 Eb。 4. 请说出两者的优缺点 回复：s32k 中 SPI 的 IB 与 EB（RTD 3.0.0.0） 但是在 IB 中，我们设置了数组之后，必须使用 Spi_WriteIB 将其写入 IB，我们不能直接访问 IB，对吗？我们可以设置与 EB 相同的数组并修改和传输数据？ 那么，从逻辑上来说 EB 更快，对吗？

Imx93 spi0 on imx93 with linux 6.1.22  ( imx93 rev A0) , I want to use spi1 to access custom component. I have declared it on dts, but no respond from component  with dtb without SPI1, using GPIO to emulate SPI no problem to access my compoent. Is something missing ?  I have with and without dma on SPI , but still no answer. // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright 2022 NXP */ #include "myboard.dts" &lpspi1 { fsl,spi-num-chipselects = <1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpspi1>; status = "okay"; spidev0: spi@0 { reg = <0>; compatible = "lwn,bk4"; spi-max-frequency = <1000000>; // spi-max-frequency = <20000000>; }; }; &iomuxc { pinctrl_lpspi1: lpspi1grp { fsl,pins = < MX93_PAD_SAI1_RXD0__LPSPI1_SOUT 0x0000051E MX93_PAD_SAI1_TXC__LPSPI1_SIN 0x0000051E MX93_PAD_SAI1_TXD0__LPSPI1_SCK 0x0000051E MX93_PAD_SAI1_TXFS__LPSPI1_PCS0 0x0000051E >; }; }; And add imx93.dtsi  lpspi1: spi@44360000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; reg = <0x44360000 0x10000>; interrupts = ; clocks = <&clk IMX93_CLK_LPSPI1_GATE>, <&clk IMX93_CLK_BUS_AON>; clock-names = "per", "ipg"; dmas = <&edma1 11 0 0>, <&edma1 12 0 1>; dma-names = "tx","rx"; status = "disabled"; }; ​ Re: Imx93 spi0 Don't use dedicated CS on device tree, but use IO   With dedicated CS function,  CS is released between each byte With IO use as CS,  CS is not released between each byte,  but at end of the frame. Re: Imx93 spi0 Could you try to set the value of pad ctrl register to 0x39e? i.e. Change all the below 0x51E to 0x39E MX93_PAD_SAI1_RXD0__LPSPI1_SOUT 0x0000051E MX93_PAD_SAI1_TXC__LPSPI1_SIN 0x0000051E MX93_PAD_SAI1_TXD0__LPSPI1_SCK 0x0000051E MX93_PAD_SAI1_TXFS__LPSPI1_PCS0 0x0000051E Re: Imx93 spi0 SPI1 is used on your custom board SPI3 was used on EVK connected to your SPI component   CS0  on SAI1_TXFS (G21) MOSI SAI1_TXC (G20) SCK SAI1_TXD0 (H21) MISO SAI1_RXD0 (H20) Hardware is on OK,  SPI component is ok using GPIOs  (slow but OK) Is there issue on iMX93 Rev A0 on this part ? Re: Imx93 spi0 How you connect your component to SPI3 and SPI1? Re: Imx93 spi0 Yes,  it's ok with SPI3 Re: Imx93 spi0 Do you add your driver in the kernel source code?

Configure EVT0_B, EVT1_B, EVT2_B, EVT3_B and EVT4_B as input pin on LS1043 Currently I have utilize all interface and pin available on LS1043 and I require to have an extra GPIO to identify my board version. By reviewing schematic of LS1043ARDB , I find that EVT0 to EVT4 pins are pull up with 4.7K register and not used at anywhere. In technical reference manual of LS1043, Appendix C represent EPU register descriptions. Where EPU base address is 2000_0000h.  EVT0_ADDR -> 2000_0000 + (50h + (0 x 4h)) = 2000_0050     (EPEVTCR0) EVT1_ADDR -> 2000_0000 + (50h + (1 x 4h)) = 2000_0054     (EPEVTCR1) EVT2_ADDR -> 2000_0000 + (50h + (2 x 4h)) = 2000_0058     (EPEVTCR2) EVT3_ADDR -> 2000_0000 + (50h + (3 x 4h)) = 2000_005C    (EPEVTCR3) EVT4_ADDR -> 2000_0000 + (50h + (4 x 4h)) = 2000_0060     (EPEVTCR4) So if I configure 0th bit DIR as 0b then it will configure as input pin then I can read status of that pin from EPRSRSVn. As per my understating if ENTn_B pin is configure with external pull-up then I will get value 1 from EPRSRSVn register.if ENTn_B pin configure with external pull-down then i will get value 0 from EPRSRSVn register. Request you to confirm this, please let me know for any improvement or changes. Regards, Bhargav Jayswal Re: Configure EVT0_B, EVT1_B, EVT2_B, EVT3_B and EVT4_B as input pin on LS1043 Hi @bhargavjayswal,  Yes, I will support in this query Re: Configure EVT0_B, EVT1_B, EVT2_B, EVT3_B and EVT4_B as input pin on LS1043 Thank you @SebastianG , I have posted one more query today but it is not reflecting in NXP community. Title for the query is "LS1043A : EMMC GPT partitioning and boot process". Could you please help for this as well. Re: Configure EVT0_B, EVT1_B, EVT2_B, EVT3_B and EVT4_B as input pin on LS1043 Hi @bhargavjayswal, Apologies for the delayed response, Yes, you can use this pin as an input in order to validate the pin state Re: Configure EVT0_B, EVT1_B, EVT2_B, EVT3_B and EVT4_B as input pin on LS1043 Thanks for  update. Now based  on above configuration, can we use this pin as an input gpio during u-boot to validate state of the pin whether is high or low?  Regards, Bhargav Jayswal Re: Configure EVT0_B, EVT1_B, EVT2_B, EVT3_B and EVT4_B as input pin on LS1043 Hi @bhargavjayswal, This configuration seems good 

MCXN236 eFuse / OTP information? Which document for the MCXN236 has information about the size, use, and addressing of the OTP bits? Thanks! Security(Edgelock | secure boot | OTP) Re: MCXN236 eFuse / OTP information? Thanks, Celeste! Very helpful info on accessing the MCXN236 security manual. Navigating NDAs can feel like playing Slope Game - constantly overcoming obstacles! Knowing it's through marketing is key. Perhaps a summary for non-NDA folks could be beneficial? Appreciate the direction! Re: MCXN236 eFuse / OTP information? Good to know, thank you Marek. Re: MCXN236 eFuse / OTP information? Hi @psmitty7373 , you can also use MCUXpresso Secure Provisioning tool (https://nxp.com/mcuxpresso/secure) to edit the fuses in GUI tool (see OTP configuration window). For full fuses description, you need to install restricted data package, that can be downloaded on the same page. Re: MCXN236 eFuse / OTP information? Thanks, Celeste. Re: MCXN236 eFuse / OTP information? Hello @psmitty7373 , Thanks for your post. According to the section "12.5 eFuse definitions " of MCXN236 reference manual, I believe it can be found in the MCX N23x Security Reference Manual.  The Security Reference Manual is confidential. You need to sign a NDA with our company and apply for the secure document on your own. The marketing department will decide whether to open it for your account.   Hope it can help you. BRs, Celeste  

GHS 构建错误控制台和问题页面 我正在使用GHS编译项目，报了好多错误，但是控制台和问题页面并没有显示具体的错误原因，不像GCC编译会提示错误原因。我可以在哪里配置它？

Guide AN13970 Incorrect This guide is incorrect and does not work for the i.MX 8ULP: AN13970: Running Zephyr RTOS on Cadence Tensilica HiFi 4 DSP | NXP Semiconductors Specifically, this line: For i.MX 8ULP (imx8ulp_evk/mimx8ud7/adsp board), the above command can be used. In fact, the command does not work for the i.MX 8ULP.  This command results in an error: > west build -p always -b imx8ulp_evk/mimx8ud7/adsp samples/subsys/ipc/openamp_rsc_table zephyrproject/zephyr/samples/subsys/ipc/openamp_rsc_table/src/main_remote.c:31:2: error: #error "Sample requires definition of shared memory for rpmsg" 31 | #error "Sample requires definition of shared memory for rpmsg" | ^~~~~ I'm not asking how to fix this error; I'm letting you know that the guide is incorrect.  Please correct the guide with any additional steps required for a successful build on the i.MX 8ULP, so it can aid future readers. Note that the steps in the guide work fine for the other three processors: i.MX 8M Plus, i.MX 8QuadMax and i.MX 8QuadXPlus.  So, it is just the i.MX 8ULP portion that needs correcting. i.MX8ULP Re: Guide AN13970 Incorrect Hello, According to the author, the following pull requests has not been fully merged at the moment: https://github.com/zephyrproject-rtos/zephyr/pull/83049 https://github.com/zephyrproject-rtos/zephyr/pull/84170 You may try these code themselves, or wait until they get merged. Note that for the sample to work on i.MX 8ULP, there's also a pending patch for Linux Kernel: https://patchwork.kernel.org/project/linux-remoteproc/patch/20250305123923.514386-1-iuliana.prodan@o... Best Regards, Zhiming Re: Guide AN13970 Incorrect Hello, Have reported this issue and i will update here once get the solution. Best Regards, Zhiming

Failed to test LWIP with TC8 Hi,NXP I used the TCP test items of TC8 to test the NXP lwip demo, and 80% of the TCP test items failed. What suggestions do you have for this problem? The chip we are using is S32K314. It may be that there are problems with our configuration, or it could be that lwip fails to pass the TC8 test. If it is a problem with LWIP, can you provide an explanation?   Best Regards, xianlong Re: Failed to test LWIP with TC8 Hello @wuxianlong , As it's been already replied in this thread S32K3 Lwip iperf test issue - NXP Community, LWIP is an open source and we do not have resources to support. However, let me share some hints for you: check your lwip settings/configuration vs. TC8 check if you use the latest version of TCPIP stack: TCPIP_STACK for S32K3XX version 2.0.0 Best regards, Pavel

The Flash Programmer feature in S32DS is not available. Dear Team, How should I configure the "Flash Programmer" in S32DS to use it? My S32DS can use the Debug function to flash the program to the MCU, but the "Flash Programmer" button in the UI is grayed out and cannot be used. How can I configure it to be functional? S32 Design Studio for S32 Platform Version: 3.6.0 Build id: 241128 S32 SDK for S32K1 Re: The Flash Programmer feature in S32DS is not available. Hi @johns_chuang, PEMicro is responsible for their scripts and SW for programming/debugging. Other than the S32DS IDE debug scripts, I am not familiar with other alternatives. Debuggers such as J-Link (SEGGER) provides the J-FLASH software which is free of charge. Best regards, Julián Re: The Flash Programmer feature in S32DS is not available. Hi Julián, We are using the Universal Multilink recommended on the S32K3 website, but when I inquired with PEmicro, they only offer the paid PROGACMP. Do you know of any free programming software that can be used with Universal Multilink? Thank you for your help. Best, Johns Re: The Flash Programmer feature in S32DS is not available. Hi @johns_chuang, If you are using an external debugger, you can use a flashing script instead of the Debug. For example, Lauterbach debugger comes with flashing script when installed: Lauterbach SW Flashing script(.Cmm) for the NXP-S32K322 Micro - NXP Community. Best regards, Julián Re: The Flash Programmer feature in S32DS is not available. Hi Julián, May I ask if there are any other methods or user interfaces available to program the S32K3xx, aside from just using Debug? Thank you for your assistance. Best, Johns Re: The Flash Programmer feature in S32DS is not available. Hi @johns_chuang, S32 Flash Tool does not completely support S32K3 family yet. You can find the supported devices under C:\NXP\S32DS.3.6.0\S32DS\tools\S32FlashTool\doc\S32_Flash_Tool_Release_Notes.pdf 1.2. Supported devices Flash Tool provides support for the following NXP devices: • S32R41 • S32R45 • S32G2xx • S32G3xx • S32Z2/E2 Best regards, Julián

How to program FS26 with KITFS26SKTEVM evaluation board Hi NXP Team, I was trying to program a MFS2630AMDA0AD using the KITFS26SKTEVM evaluation board. I've followed all the steps of the NXP GUI for FS26 Automotive PMIC Family user manual at chapter 7.4 "Device programming" and chapter 8.5" Programming the device with an OTP configuration"... When i click program the GUI pops me up this message:   I've noticed that the user manual in chaper 7.4 mentions the Jumper J13 that is not present on my evaluation board. Where do i have to focus on in order being able to program my device? Thanks a lot, Simon Re: How to program FS26 with KITFS26SKTEVM evaluation board Hello Please see following steps: It is recommended to set your power supply to an initial value of 12V and current limited to 0.5A. Make sure SW1 is OFF (middle position) Plug the USB cable into the “USB KL25Z” port Switch SW7 ON (DBG = 8V) Plug the power supply on J21 and switch SW1 on the left side You’re now in OTP Mode. LEDs status should be the same than the picture Open the graphic user interface Click on FS26-C0 and “OK” button Click on “Start” button to start the communication Verify FS_STATES is “4-Debug entry” Click on PROG tab on the left panel Click on « Apply test mode» button. Click on « Read » button to know the fuse box status Click on « Browse » button and the select the OTP script At this step, the product is ready to be programmed Hope this helps.

GHS Build Error Console&Problems Page I'm using the GHS compilation project and reported a lot of errors, but the console and problems pages do not show the specific cause of the error, unlike GCC compilation, which prompts the cause of the error. Where can I configure it? Re: GHS Build Error Console&Problems Page Hi,  from the output it looks that linker is not able find  NvM_Crc32CalculateCallout Ea_InitDoneNotification symbols. Please try to find out where are these symbols (variables or functions) defined and if are visible for  NvM_JobProc.c   and Ea.c Re: GHS Build Error Console&Problems Page S32DS version is 3.5,GHS is 202214:   full console： Re: GHS Build Error Console&Problems Page Hi,  which version of S32DS and GHS plugin are you using? Can you please share full output from build console? 

RT1170 Watchdog: WDOG1 Usage and WDOG3/4 Clock Sources Thank you for response about Solved: Re: Dual Core: RT1170 Watchdog Setup - NXP Community. However, I have a few more questions. Can WDOG1 internally reset the CPU if MCU pins WDOG_B and WDOG_RESET_B_DEB (aka WDOG_RST_B_DEB), are not connected to anything? If yes, what steps are required to achieve this? Next for WDOG3 and WDOG4, there appears to be up four clock source options available, but the chip-specific information does not appear to give a clear indication about what those clock sources are and what the order is for each clock source. Am I looking at the right table? Where in IMXRT1170RM can I find what the 4 clock sources are for WDOG3 and WDOG4, according to register CS[CLK]? Re: RT1170 Watchdog: WDOG1 Usage and WDOG3/4 Clock Sources Hi @lsrbigfoot , Thanks for your updated information. I check your question  with internal side, I will show you.   9:8: 2’b00 – bus clock for wdog3 and lpsr bus clock for wdog4 2’b01 – LPO clock (sourced from 32k clock) 2’b10 – INTCLK (sourced from 32k clock) 2’b11 – ERCLK (1m clock) As for Wdog3 demo , I suggest you can refer to "evkbmimxrt1170_rtwdog_cm7". Wish it helps you. If you still have question about it, please kindly let me know. Wish you a nice day! Best Regards MayLiu Re: RT1170 Watchdog: WDOG1 Usage and WDOG3/4 Clock Sources Fair enough, I see the list of WDOG3/4 sources in MIMXRT1170RM chapter 72.1.7. But how can I exactly identify each clock source from register bits CS[CLK]? I couldn't tell from the clock source definitions in fsl_rtwdog.h (see rtwdog_clock_source_t). Please advise. Re: RT1170 Watchdog: WDOG1 Usage and WDOG3/4 Clock Sources Hi @lsrbigfoot , Thank you for your interest in the NXP MIMXRT product, I would  like to provide service for you. Question1: Can WDOG1 internally reset the CPU if MCU pins WDOG_B and WDOG_RESET_B_DEB (aka WDOG_RST_B_DEB), are not connected to anything? If yes, what steps are required to achieve this? Answer: Yes, you can. I suggest you can refer to NXP SDK demo "evkbmimxrt1170_wdog01_cm7". Question2: WDOG3 and WDOG4  clock source Answer: Please check MIMXRT1170RM chapter 72.1.7 Watchdog Timer (WDOG3,4) Wish it helps you. If you still have question about it, please kindly let me know. Wish you a nice day! Best Regards MayLiu

MCXN236 eFuse/OTP 信息？ 哪个有关 MCXN236 的文档包含有关 OTP 位的大小、使用和寻址的信息？ 谢谢！ 安全（Edgelock | 安全启动 | OTP） 回复：MCXN236 eFuse/OTP 信息？ 谢谢，Celeste！有关访问 MCXN236 安全手册的非常有用的信息。处理保密协议就像玩游戏一样 斜坡游戏 - 不断克服障碍！了解这一点的关键在于通过营销。也许对非保密协议人员来说，总结一下会有帮助吗？感谢指导！ 回复：MCXN236 eFuse/OTP 信息？ 很高兴知道，谢谢你，马雷克。 回复：MCXN236 eFuse/OTP 信息？ 谢谢，塞莱斯特。

MCXN236 eFuse / OTP情報? OTP ビットのサイズ、使用、およびアドレス指定に関する情報が記載されているMCXN236のドキュメントはどれですか? ありがとうございます！ セキュリティ（EdgeLock | セキュアブート | OTP） Re:MCXN236 eFuse / OTP情報? ありがとう、セレステ!MCXN236セキュリティマニュアルへのアクセスに関する非常に役立つ情報です。NDAをナビゲートすることは、常に障害を克服する スロープゲーム をプレイしているように感じることができます!それがマーケティングを通じて行われることを知ることが鍵となります。おそらく、NDA以外の人々のための要約は有益かもしれませんか?方向性に感謝します! Re:MCXN236 eFuse / OTP情報? 知ってよかった、ありがとうマレック。 Re:MCXN236 eFuse / OTP情報? ありがとう、セレステ。

SS32K344 LPUART Timeout counter Hello all, I am trying to implement the Timeout counter from the LPUART module of an S32K344 microcontroller, but I have encountered some issues. I want to use them to monitor idle bits elapsed from the last received message so, my first question is, do they have the ability of generating a hardware interrupt? Looking at the table of LPUART registers as per the S32K3XX Reference Manual (section 77.6.1), the registers that I should modify to configure the timeout counters are TOCR, TOSR and TIMEOUTN. The first thing that I noticed is that these registers are not in the LPUART register layout typedef in the SDK (in the S32K344_LPUART.h)    Therefore, I have tried to access these registers manually, taking the IP_LPUART_0_BASE address from the SDK and adding the corresponding offset (0x58 in this case). When trying to read/write this region, I get a Hard Fault. I have tried to read other LPUART registers from the ones in the image above with this method to ensure that the method itself is not the problem, and it worked just fine. Right now I am supposing that this memory region is somehow protected, but I could not find many info on this in the Reference Manual, so my question is: Is this the case? Is this memory region protected? and, if so, is there any way that I can access it to configure the timeout counters? Thank you in advance!   Re: SS32K344 LPUART Timeout counter Hi@xianalbela I have double checked it , this register is not support in S32K344,S32k324,S32K314 and S32K312. For other S32K3's mcu, it does support. Re: SS32K344 LPUART Timeout counter Hello @Senlent, yes, I am aware that this register is not defined in the "S32K344_LPUART.h" file, but I wanted to know if there is any other way to use the LPUART Timeout counter feature since it is described in the reference manual. Maybe there is some mode that needs to be activated before trying to access those registers. Is it possible to use this feature in any way? Best regards. Re: SS32K344 LPUART Timeout counter Hi@xianalbela I checked your code and there is nothing wrong with your syntax. However, the register address you used is not defined. The registers that users can use and access are only in "S32K344_LPUART.h". Re: SS32K344 LPUART Timeout counter Hello @Senlent , sure, I am attaching the complete project. I am using the S32DS for ARM Version 3.4, and the RTS version that I am using is the 2.0.0 for the S32K3xx. Re: SS32K344 LPUART Timeout counter Hi@xianalbela You also need to tell me the RTD version you're using. It would be best if you can provide me with the complete project you tested Re: SS32K344 LPUART Timeout counter Sorry @Senlent , I am re-attaching the file.  Re: SS32K344 LPUART Timeout counter Hi@xianalbela Could you please double check it, cause i didn't see any attachments. Re: SS32K344 LPUART Timeout counter Hello @Senlent, I am using the LpuartFlexio_Uart_Ip_Example_S32K344 from the NXP repository. The only changes that I have made are in the main.c file (that I am attaching to this reply) to implement the timeout counter (changing the LPUART instance from 3 to 0) and to remove the Flexio UART instance. Thank you! Re: SS32K344 LPUART Timeout counter Hi@xianalbela Please provided your demo code so that i can reproduce your problem, it will be more easy for me to help you found the root cause.

GHSビルドエラーコンソール&問題点ページ GHSコンパイルプロジェクトを使用しており、多くのエラーを報告しましたが、エラーの原因をプロンプトするGCCコンパイルとは異なり、コンソールと問題のページにはエラーの具体的な原因が表示されません。どこで設定できますか?