S32k344 MBIST LBIST I'm in the process of implementing S32k344 BISTs in a green hills project. I'm using SW32K3_SPD_1.0.6_D2512 in the source code form since I don't use Tresos or NXP DS. I was able to import most of the bist functions, except few defines that I'm not sure about (can't find them anywhere). Can anybody answer below questions. 1. Can I run LBIST MBIST while S32k344 is in lock step mode? 2. Is the following defines correct, I guessed by examining the code? #define BIST_MBIST_0 1U #define BIST_MBIST_1 2U #define BIST_MBIST_2 3U #define BIST_MBIST_3 4U #define BIST_MBIST_4 5U #define BIST_MBIST_5 6U #define BIST_MBIST_6 7U #define BIST_MBIST_7 8U #define BIST_MBIST_8 9U #define BIST_MBIST_9 10U #define BIST_MBIST_10 11U #define BIST_LBIST_0 0U the config data I used are as follows: static const BIST_CHANNEL_CONFIG_TYPE BistConfig[BIST_SAFETYBOOTCFG_NB] = { { (BIST_CHANNEL_TYPE)BIST_MBIST_0, (BIST_CONTROL_TYPE)((0x80100000U) | BIST_MBIST_PTR_VAL(BIST_MBIST_1)) }, { (BIST_CHANNEL_TYPE)BIST_MBIST_1, (BIST_CONTROL_TYPE)((0x80100000U) | BIST_MBIST_PTR_VAL(BIST_MBIST_2)) }, { (BIST_CHANNEL_TYPE)BIST_MBIST_2, (BIST_CONTROL_TYPE)((0x80100000U) | BIST_MBIST_PTR_VAL(BIST_MBIST_3)) }, { (BIST_CHANNEL_TYPE)BIST_MBIST_3, (BIST_CONTROL_TYPE)((0x80100000U) | BIST_MBIST_PTR_VAL(BIST_MBIST_4)) }, { (BIST_CHANNEL_TYPE)BIST_MBIST_4, (BIST_CONTROL_TYPE)((0x80100000U) | BIST_MBIST_PTR_VAL(BIST_MBIST_5)) }, { (BIST_CHANNEL_TYPE)BIST_MBIST_5, (BIST_CONTROL_TYPE)((0x80100000U) | BIST_MBIST_PTR_VAL(BIST_MBIST_6)) }, { (BIST_CHANNEL_TYPE)BIST_MBIST_6, (BIST_CONTROL_TYPE)((0x80100000U) | BIST_MBIST_PTR_VAL(BIST_MBIST_7)) }, { (BIST_CHANNEL_TYPE)BIST_MBIST_7, (BIST_CONTROL_TYPE)((0x80100000U) | BIST_MBIST_PTR_VAL(BIST_MBIST_8)) }, { (BIST_CHANNEL_TYPE)BIST_MBIST_8, (BIST_CONTROL_TYPE)((0x80100000U) | BIST_MBIST_PTR_VAL(BIST_MBIST_9)) }, //#endif { (BIST_CHANNEL_TYPE)BIST_MBIST_9, (BIST_CONTROL_TYPE)((0x80100000U) | BIST_MBIST_PTR_VAL(BIST_MBIST_10)) }, { (BIST_CHANNEL_TYPE)BIST_MBIST_10, (BIST_CONTROL_TYPE)(0x00100000U) }, { (BIST_CHANNEL_TYPE)BIST_LBIST_0, (BIST_CONTROL_TYPE)((0x00001108U) | BIST_LBIST_PTR_VAL(BIST_NIL)) } }; Re: S32k344 MBIST LBIST Hello,
1. Can I run LBIST MBIST while S32k344 is in lock step mode?
Yes. The S32K344 lockstep architecture does not prevent execution of STCU2 LBIST/MBIST. The BIST mechanism is part of the device safety infrastructure and is designed to test logic and memories managed by STCU2. The S32K3 Safety Manual explicitly lists both lockstep and STCU2 LBIST/MBIST as safety mechanisms of the device.
2. Is the following defines correct, I guessed by examining the code?
The numerical values are essentially correct for S32K344, but including MBIST_10 (HSE_ROMs) in the Safety Boot configuration is not required from a safety perspective, and the recommended path is to use the validated SPD configurations directly.
Best regards,
Peter
Re: S32k344 MBIST LBIST Peter, Thank you very much for replying. I have been stuck with this BIST test issues for few days now. I'm testing with S32k344 White board, code is build with green hills multi IDE rev 8.1. The safety boot BIST is not passing. I'm sure the max clock requirement is met for core and peripherals. I have core_clk at 160Mhz from external crystal 16Mhz and PLL, AIPS_PLAT_CLK is 80Mhz, AIPS_SLOW_CLK is 40Mhz, DCM_CLK as 40 MHz, LBIST_CLK is 40Mhz, QSPI_MEM_CLK is 160Mhz. I have this error when unit reset from bist run, DES register has 0x00408175, few reserved bits get set, and FES register has 0x2000 (doesn't make sense). would you kindly answer following questions? 1. with all the clock signals mentioned above, should they be enabled through MC_CGM->MUX_0_DC_x registers? I'm getting conflicting information, currently they are enabled. 2. In the reference manual, STCU2 chapter, there is this "While running MBIST on EMAC time stamp memory, MC_CGM.MUX_9_DC_0[DIV] should be appropriately configured to ensure EMAC_CLK_TS should be at least 1.5 times the AIPS_SLOW_CLK frequency." does that mean I have to config configure the clock and enable it in the MC_CGM->MUX_9_DC_0 register? 3. If I want to see the example code S32_SPD_Demo in SW32K3_SPD_1.0.6_D2512 package, I guess I need to install latest NXP design studio, import the spd zip file as update site, and also the RTD package, is that right? 4. I believe MBIST 10 is HSE_RAMS, MBIST 11 is HSE_ROMS, please see the table below from SPD doc folder. MBIST BIST ID BIST Instance Name Reset Domain Safety Boot Safety Diagnostic 0 SYS0_RAMS Main ü ü 1 SYS1_RAMS Main ü ü 2 DMA_TCD_RAM Main ü ü 3 CM7_0_TOP Main ü ü 4 CM7_1_TOP Main ü ü 5 FLEX_CAN_RAMS Main ü ü 6 QSPI_PERI_RAMS Main ü ü 7 EMAC_TSN_RAM Main ü ü 8 EMAC_RAMS Main ü ü 9 b03_ETF_RAMS Main ü ü 10 HSE_RAMS Main ü ü 11 HSE_ROMS Main ü Re: S32k344 MBIST LBIST An update to my problem, after I enabled bit 8 and 9 in the STCU_RUNSW_REG to use PLL, I'm consistently seeing DES register 0x11 and FES register of 0x10. The bist_get_exec_status(BIST_SAFETYBOOT_CFG) return value is NOT RUN (0x03). There is nothing in the BIST ERR_STAT register, none of the END flag is set. In the FCCU NCF_S0 register, bit 2 is set. It seems BIST didn't start, but I do see the reset. I captured the register setting by writing to flash in the other bank. Re: S32k344 MBIST LBIST Hello,
the STCU self-test sequence is being entered and reaches the ST_DONE reset phase. However, the STCU also reports an unrecoverable fault (STCU_URF), which explains why the SAF BIST driver subsequently reports BIST_NORUN. The issue therefore appears to be an STCU execution/configuration failure rather than a case where BIST was never triggered.
On S32K3, seeing both a destructive and functional reset indication simultaneously is often a sign that you are looking at a reset history, not necessarily the immediate reset source
Since you are porting the SW, I would start with simply just MBIST only test to see if it pass sourced from PLL.
Also I would double check the clock settings for the tests.
Best regards,
Peter
Re: S32k344 MBIST LBIST I checked the all possible clocks, I believe they are correct. I also compared the config data in the register with values from NXP studio spd example project, they are also correct. One new information. After system come back from BIST reset, I see value 0x18 in DCMROD3 register. How do I resolve this error? Thanks. XRen_Parker_0-1788544110794.pngXRen_Parker_0-1788544110794.pngXRen_Parker_0-1788544110794.pngXRen_Parker_0-1788544110794.png Re: S32k344 MBIST LBIST Hello,
On S32K344, RCCU reports lockstep mismatches, and when connected with a debugger, it is not uncommon to get RCCU-related faults that would never occur in standalone execution.
In case you follow the setting from example, you are looking at full BIST.
Example is tested and it is fully working by default.
But your port reporting URF fault, which tells me not everything is identical.
Looking at STCU documentation user can set pointer to tests.
54.9.4 STCU2 Configuration (CFG)
petervlna_0-1788766597312.pngpetervlna_0-1788766597312.pngpetervlna_0-1788766597312.png
You can try shrinking tests first and the slowly add more tests.
In MBIST and LBIST control registers you can set which test will be last:
petervlna_1-1788766735386.pngpetervlna_1-1788766735386.pngpetervlna_1-1788766735386.png
By pointing to for example in CFG register you can execute single MBIST partition:
petervlna_2-1788766853581.pngpetervlna_2-1788766853581.pngpetervlna_2-1788766853581.png
petervlna_3-1788766973925.pngpetervlna_3-1788766973925.pngpetervlna_3-1788766973925.png
Best regards,
Peter
Re: S32k344 MBIST LBIST I tried to run mbist sequentially, and also tried individual mbist test ID. The outcome is the same, no new status observed. Can you confirm the following SCU2 register settings for safety boot right before trigger is set? Thanks. XRen_Parker_0-1788899133217.pngXRen_Parker_0-1788899133217.png Re: S32k344 MBIST LBIST This is for people in the community who are struggling with implementing LBIST/MBIST in the S32k344 microcontroller. After days of no progress made, I was able to see the test pass. I did with custom porting of the SPD driver 1.06. The driver code works except the fault need to be configured to unrecoverable fault. The following are the clocks that need to be configured, if any one of them is not set up correctly, the test will fail with BIST_NORUN(0x03) status because test sequence runs concurrently, no other status is seen, no completion bits set. 1. Config FXOSC module CTRL register to use external oscillator or crystal, this is the only way to get 160MHz, max for S32k344. 2. Config PLLDIG module for the PLL circuit, make sure max frequency is the output by configuring rdiv, mfi, and odiv2 bits in the PLLDV register. 3. Switch in the PLL clock for core_clk and emac_clk by following the reference manual steps, MC_CGM_MUX_x registers setting. 4. config MC_CGM->MUX_0 and MC_CGM->MUX_9 registers to get following clock signals. AIPS_PLAT_CLK as 80 MHz AIPS_SLOW_CLK as 40 MHz HSE_CLK as 80 MHz DCM_CLK as 40 MHz LBIST_CLK as 40MHz QSPI_MEM_CLK as 160MHz EMAC_CLK as 80MHz Note: DON'T SET BIT 8 AND 9 IN THE RUNSW REGISTER, THE TEST WILL FAIL IF THEY ARE SET. This is not done in the SPD driver code. I mention this because there is conflicting info in the reference manual.
記事全体を表示
