This document shows, how to use CodeWarrior 10.6 to program QSPI flash for Power Architecture microcontrollers.   1) Create new project for appropriate microcontroller. 2) Open Debug configuration and duplicate one of the target.   3) Rename duplicated target (optional) 4) Choose the duplicated (renamed) target and click Edit button in Target settings tab.   5) In new screen, click Advanced Programming Options.   6) Check Use Alternative Algorithm and choose the algorithm you want to use. Algorithms are place in CodeWarrior installation folder. Full path is CodeWarrior_installation_folder\MCU\bin\plugins\support\EPPC\gdi\P&E\   7) On the screen Debug configuration, choose the file you want to program to QSPI flash.   Click Apply and Debug.

Document describes possible reasons of result swap in eQADC's result FIFO and how to avoid it. Very preliminary version!

******************************************************************************** * Detailed Description: * Example configures Sigma_Delta ADC and periodically converts ANA0_SDA0 input * (EVB's potentiometer can be connected i.e. J53-1 --> PO15) and displays * results in the terminal window (USBtoUART bridge J21). Terminal settings is * 19200-8-no parity-1 stop bit-no flow control on eSCI_A. * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A *                  eSCI_A is USBtoUART bridge (connector J21) * EVB connection:  For ADC: J53-1 (EVB pot's wiper) --> PO15 (header P22) * ********************************************************************************

******************************************************************************** * Detailed Description: * DRUN mode with max core frequency(200MHz) generated from PPL0 * This example demonstrates ECC error injection to peripheral RAM *  and ECC error reporting to MEMU * --------------------------------------------------------------------------------------------- * Test HW:  MPC57xx * Maskset:  1N15P * Target :  internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference *           ******************************************************************************** Revision History: 1.0     Apr-04-2016     b21190(Vlna Peter)  Initial Version 1.1    Aug-15-2017     b21190(Vlna Peter)  EIM ECC RAM error injection to DMA added *******************************************************************************/

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, second LED by software * loop, initializes and display notice via UART terminal and then terminal ECHO. * The example configures the device for maximum performance (OPTIMIZATIONS_ON). * For XPC564AKIT324S it initializes EBI for mounted external SRAM. * Its intention is to offer advanced startup code additional to CW stationery. * * ------------------------------------------------------------------------------ * Test HW:        XPC564AKIT208S and XPC564AKIT324S * MCU:            SPC5644AMMG1,0M14X and SPC5644AMVZ1,0M14X * Fsys:           150/132/120/12 MHz * Debugger:       Lauterbach Trace32 *                 PeMicro USB-ML-PPCNEXUS * Target:         RAM, internal_FLASH * Terminal:       19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: default * ********************************************************************************

******************************************************************************** Detailed Description: Example shows configuration of SIUL External interrupts using SDK driver. EIRQ0 (PA3) and EIRQ11 (PE12) are configured for detecting rising edge. Those pins are connected to switches SW1 and SW2 on DEVKIT board. EIRQ1 (PA6) is configured for detecting falling edge. Within its interrupt routines a LEDs are toggled upon edge detecting. See PinSetting component for pins configuration within "Routing" and "Functionals Properties" tabs. To see falling edge on PA6 just connect pin (J2.1) to GND shortly. * ------------------------------------------------------------------------------ * Test HW:         DEVKIT-MPC5748G * MCU:             PPC5748GSMKU6 0N78S * Target:          Debug_FLASH * EVB connection: * Compiler:        S32DS.POWER.2017.R1 * SDK release:     S32_SDK_S32PA_BETA_2.9.0 * Debugger:        S32DS, Lauterbach Trace32 ******************************************************************************** Revision History: Ver Date        Author       Description of Changes 0.1 Jun-13-2019 Petr Stancik Initial version *******************************************************************************/

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * start both Z7 cores, interrupts initialization, blinking three LED by interrupts, * initializes and display notice via UART terminal and then terminal ECHO. * Each core serves one interrupt and one LED. * * The example configures the device for maximum performance by initialization of * instruction/data cache and enabling of branch prediction for each core * (startup.s files). * * ------------------------------------------------------------------------------ * Test HW:         MPC5775K-356DS, MPC57xx Motherboard * MCU:             PPC5775KMMY3A 0N38M * Terminal:        19200-8-no parity-1 stop bit-no flow control on LINFlexD_0 * Fsys:            PLL0 266MHz *                    Z4 Core 133MHz *                    Both Z7 Cores 266MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection:  USER LED1 connected to P19.0, LED2 connected to P19.5 *                  LED3 connected to P19.8 *                  For correct UART functionality connect: *                  J14.2 to P12.6 *                  J13.2 to P12.7 * ********************************************************************************

The device can be secured by adding a Non-Volatile System Censorship Information (NVSCI) record to the DCF record list in the UTEST Flash block. A value of 55AAh in the censorship control word of the NVSCI record determines that the device is unsecured, any other value determines that the device is secured.   Censoring the device (example for lauterbach script) 1. Program NVSCI DCF record to first available space in UTEST memory.    data.set 0x00400308 %QUAD 0x55AA12340100000C ;NVSCI - Censorship Control enabled 2. Program Censorship password (0x1234567812345678)    data.set 0x00400310 %QUAD 0x1234567801000004 ;NVPWDL                                                            data.set 0x00400318 %QUAD 0x1234567801000008 ;NVPWDH    3. Perform reset   Now the device is censored and JTAG PASSWORD must be inserted in order to work with JTAG. Lauterbach ->   sys.option.keycode 0x1234567812345678 sys.attach sys.break The device is now accessible trough JTAG.   " After every reset the JTAG PASSWORD key must be reentered on censored device "   Uncensoring device: data.set 0x004003018 %QUAD 0x55AA55AA0100000C ;NVSCI - Censorship Control disabled   NOTE:   Peter Original Attachment has been moved to: MPC5744P_DCF_Censorship.cmm.zip

******************************************************************************** * Detailed Description: * * Simple LINFlex UART mode transmit and receive without interrupts (polled UART) * TXFIFO and RXFIFO macro is used to select between buffer and FIFO mode * * PIT channel 0 is also used to generate 1sec interrupt where PA0 pin is toggled. * * EVB connection: * *   Motherboard *   J14 - SCI_RX OFF *   J13 - SCI_TX OFF *   J25 - SCI_PWR ON * * See results on PC terminal (19200, 8N1, None). * ------------------------------------------------------------------------------ * Test HW:  MPC5777M, MPC57xx Motherboard + MPC5777M_512DS minimodule * Maskset:  0N78H * Target :  RAM, internal_FLASH * Fsys:     600 MHz PLL1 with 40 MHz crystal reference, *        core2 at 200MHz generated from PPL1 * Terminal: 19200, 8N1 ********************************************************************************

******************************************************************************** * Detailed Description: * Purpose of the example is to show how to generate Multi-bit or Single-bit * ECC error in internal FLASH (user must choose it in the option at the end of * main function). * Flash over-programming is used to generate a non-correctable (or single-bit) * ECC error in FLASH. The bad data is accessed then, so the IVOR1 exception (or * ERM combined interrupt service routine) is generated and handled. * Example also offers useful macros for EIM and ERM modules. * The example displays notices in the terminal window (USBtoUART bridge J21) * (19200-8-no parity-1 stop bit-no flow control on eSCI_A). * No other external connection is required. * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection:  eSCI_A is USBtoUART bridge (connector J21) * ********************************************************************************

******************************************************************************** * Detailed Description: * Purpose of the example is to show how to simulate Multi-bit or Single-bit ECC * error in internal DMA TCD RAM (user must choose it in the option at the end of * main function). * EIM (Error Injection Module) is used to simulate a multi-bit or single-bit * ECC error in DMA TCD RAM (Peripheral RAM). * When corrupted data is accessed the IVOR1 exception handler is called in case * of multi-bit ECC error (IVOR1 exception occurs) and FCCU_Alarm_Interrupt * handler is called in case of single-bit ECC error (FCCU interrupt occurs). * Both function calls MEMU handler. * The example displays notices in the terminal window (connector J19 on * MPC57xx_Motherboard)(19200-8-no parity-1 stop bit-no flow control on eSCI_A). * No other external connection is required. * ------------------------------------------------------------------------------ * Test HW:         MPC57xx_Motherboard + MPC5744P-144DC * MCU:             PPC5744PFMLQ8,0N15P,QQAA1515N, Rev2.1B * Fsys:            200 MHz PLL with 40 MHz crystal reference * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH, RAM * Terminal:        19200-8-no parity-1 stop bit-no flow control * EVB connection:  default ********************************************************************************

******************************************************************************** * Detailed Description: * This example shows, how to use interrupt hardware vector mode. In the example * PIT0 interrupt and external interrupt source 1 are implemented. PIT interrupt * toggle LED every second, external interrupt causes IVOR1 exception. * * This example also shows, how to use exceptions, while HW vector mode is used. * After SW1 button is pressed, uninitialized RAM is read and IVOR1 exception is * reached. In IVOR1, only endless loop is implemented and micro has to be reset * externally if you want to get out from this loop. * * * For correct HW vector mode setup, following files was added to the project: * *  - exceptions.s *  - handlers_vle.s *  - HW_vector.c * * * Following files was modified (all changes are marked by comment): * *  - mem.ld *  - sections.ld *  - Vector.c *  - MPC57xx__Interrupt_Init.c * * *  Following files was removed from project (files are still place in project, but *  not compiled and linked) * *  - intc_sw_handlers.S *  - intc_SW_mode_isr_vectors_MPC5744P.c * * * * Test HW:         X-MPC5744P-144DC, MPC57xx motherboard * MCU:             PPC5744PFMLQ8 0N15P * Fsys:            200 MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection:  User LED 1 connected to A0 (P8.0), *                    User switch SW1 connected to A1 (P8.1) * * * ------------------------------------------------------------------------------ * ********************************************************************************

******************************************************************************** * Detailed Description: * This example demonstrates frequency modulation at 20kHz with 250 steps. * System frequency which is modulated is 40MHz. * ------------------------------------------------------------------------------ * Test HW:   MPC57xx EVB + MPC5748G minimodule * Maskset:   1N81M * Target :     SRAM * Fsys:        40 MHz PLL * ******************************************************************************** Revision History: 1.0     Oct-29-2014     b21190(Vlna Peter)  Initial Version 1.1    Nov-20-2014    b21190(Vlna Peter)  Modified for Cut2.0 1.2    Nov-20-2014    b21190(Vlna Peter)  Added SWT_0 dissabling in startup 1.3    Mar-10-2016    b21190(Vlna Peter)  Fixed clock configuraion for PLL 1.4    Jun-30-2017    b21190(Vlna Peter)  Added 20kHz frequency modulation *******************************************************************************/ Measure modulated system Frequency at PG[7] - SYSCLK0 pin.

This excel tool helps to configure MMU on e200z cores. It generates asm code and also command for Lauterbach debugger for selected configuration of TLB entry.

******************************************************************************** * Detailed Description: * This SW provides the example of clearing of FCCU faults. * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N65H * Target :  internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference + FCCU fault clearing example code. * ******************************************************************************** Revision History: 1.0     Jan-05-2016     nxa13250(Vlna Peter)  Initial Version *******************************************************************************/

This document shows, how to use CRC gen utility in CodeWarrior for MCU IDE.   1) Create new project in CodeWarrior. 2) Create a file calc_crc.crc in the Project/Project_Settings/Linker_File directory. 3) Open project settings, choose C/C++ Build ->Settings and add the following command to Post-build steps: "${MCU_TOOLS_HOME}/bin/crcgen.exe" "${BuildLocation}/${BuildArtifactFileName}" -crc "${ProjDirPath}/Project_Settings/Linker_Files/calc_crc.crc" -srec "${BuildLocation}/${BuildArtifactFileName}.crc.mot" 26   4) Open calc_crc.crc and configure required parameters. Meaning of single lines is described in CodeWarrior reference manual called Targeting_Microcontrollers I used following code (it is only example)   5) Build your project. 6) File MPC5604B-CRCTest.elf.crc.mot was created   Now you have s-record, which contains CRC and which could be loaded to microcontroller.

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed * frequency * * * Mode transition to LPU_STOP is executed. CAN_0 is configured to wake up from *  LPU_STOP to LPU_RUN using message with standard IDE = 0 as a wake up *  preselected matching criteria. After wake up from LPU_STOP, user *  LED1 is blinking.   * * Modified files: mem.ld, sections.ld, startup.s, added file z2_restart.s * * * ------------------------------------------------------------------------------ * Test HW:         MPC5748G-324DS, MPC574xG Motherboard * MCU:             PPC5748GMMN6A 1N81M * Fsys:            PLL0 160MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection:  Default * * * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, * initializes and display notice via UART terminal and then terminals ECHO. * * * Test HW:        X-MPC5744PE257DC, MPC57xx motherboard * MCU:              PPC5744PFMMM8 1N65H * Terminal:        19200-8-no parity-1 stop bit-no flow control on LINFlexD_0 * Fsys:             200 MHz * Debugger:      Lauterbach Trace32 *                       PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection:  User LED 1 connected to A0 (P8.0), * ********************************************************************************

******************************************************************************** * Detailed Description: * Initializes eQADC module for differnential single scan mode (with choosen GAIN * factor), converts specified command queue and displays results into terminal * window when EOQ is reached. * Differential analog input DAN0+:DAN0- needs to be connect externally between * pins ANA_0 and ANA_1 to see some valid numbers. * EVB potentiomenters can be used for the purpose. * As differential mode has been used, eQADC does not required to be calibrated.             * * ------------------------------------------------------------------------------ * Test HW:         XPC567XKIT516 - MPC5674ADAT516 Rev.C, MPC567XEVBFXMB Rev.B * MCU:             PPC5674FMVYA264 * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A * Fsys:            264/200/150/60 MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          RAM, internal_FLASH * EVB connection:  Potentiometers     --> ADC inputs *                  USER_DEV_RV2(J4-7) --> ANA_0 (J18-3) DAN0+ *                  USER_DEV_RV3(J4-8) --> ANA_1 (J18-4) DAN0- * *                    Buttons            --> ADC triggers *                    USER_DEV_1D(J4-2)  --> TPU_A0 (J22-1)                  ********************************************************************************