******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, second LED by software * loop, initializes and display notice via UART terminal and then terminal ECHO. * * ------------------------------------------------------------------------------ * Test HW:        XPC563MKIT * MCU:            PPC5633MMLQ80 * Fsys:           80/60/40/12 MHz * Debugger:       Lauterbach Trace32 *                 PeMicro USB-ML-PPCNEXUS * Target:         RAM, internal_FLASH * Terminal:       19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: default * ********************************************************************************

Detailed Description: Demo application measures analog voltage from externally connected humidity sensor HIH-5030. Obtained values and processed and displayed on MPC5606S-DEMO-V2 board’s TFT panel. Application uses standard Graphics Libraries for MPC5606S for simple graphic output that is managed in mc_base.c module only. ------------------------------------------------------------------------------ Test HW:            MPC5606S-DEMO-V2 + HIH-5030 MCU:             PPC5606SEF OMLU 0M25V DD68391 XOTAC1003 Fsys:            64MHz Debugger:        Lauterbach Trace32 Target:          internal_FLASH Terminal:        none EVB connection:   For complete project you may see following link: Demo application MPC5606S-DEMO + LM75B + HIH-5030 + PCA8565 + GUI

******************************************************************************** * Detailed Description: * Purpose of the example is to show how to generate Multi-bit or Single-bit ECC * error in internal RAM (user must choose it in the option at the end of main * function). * ECC fault is generated with using of core register E2EECSR. If error injection * is enabled (E2EECSR0[INVC]=1) and certain mask is set (E2EECSR0[CHKINVT]), * subsequent write to SRAM creates error in SRAM array. * When corrupted data is read the IVOR1 exception handler is called in case of * multi-bit ECC error (IVOR1 exception occurs) and FCCU_Alarm_Interrupt handler * is called in case of single-bit ECC error (FCCU interrupt occurs). * Both function calls MEMU handler. * The example displays notices in the terminal window (connector J19 on * MPC57xx_Motherboard)(19200-8-no parity-1 stop bit-no flow control on eSCI_A). * No other external connection is required. * ------------------------------------------------------------------------------ * Test HW:         MPC57xx_Motherboard + MPC5744P-144DC * MCU:             PPC5744PFMLQ8,0N15P,QQAA1515N, Rev2.1B * Fsys:            200 MHz PLL with 40 MHz crystal reference * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH, RAM * Terminal:        19200-8-no parity-1 stop bit-no flow control * EVB connection:  default ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, initializes interrupts and external * interrupt for IRQ0 pin (alternative function of ETPUC9 pin). * User needs to connect ETPUC9 pin to user switch and general purpose output * ETPUA30 to user LED 1: * ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) * ETPUC9  (PortV P30-8) --> USER_SWITCHES (P6-4) * * If rising edge is detected (i.e. button is pressed), interrupt is triggered * and LED1 on is toggled. * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection:  ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) *                  ETPUC9  (PortV P30-8) --> USER_SWITCHES (P6-4) ********************************************************************************

This document describes how to use Lauterbach FCCU (fault collection and control unit) periphery extension for MPC57xx devices. It is expected that user has deep knowledge on FCCU mechanisms in order to effectively use this extension. This scripting tool consist of 136 scripts for Lauterbach debugger. It helps user to quickly debug micro without need of reference manual. Here is and example of windows that user can use (detailed description can be found in user guide):

******************************************************************************** * Detailed Description: * In case user want GHS to initialize all cores it is necessary to define * preprocessor symbol: init_cores * However in this example the cores are initialized from function: Core_Boot(); * This example demonstrates how to initialize clock module and activate core0, core1 and core0 locksteped core. * ------------------------------------------------------------------------------ * Test HW:  MPC57xx EVB * Maskset:  0N78H * Target :  internal_FLASH * Fsys:     200 MHz PLL * ******************************************************************************** Revision History: 1.0     Feb-08-2016     b21190(Vlna Peter)  Initial Version 1.1    Feb-09-2016     b21190(Vlna Peter)  Added Core_Boot() function *******************************************************************************/

******************************************************************************** * Detailed Description: * * ECSM Error Generation Register EEGR is used to generate a non-correctable * or single bit ECC error in RAM. The bad data is accessed then, so the IVOR1 * exception is generated and handled. * This file shows also ECSM_combined_isr and how to correct the wrong data. * Use macro Induce_ECC_error_by_DMA_read to select whether ECC error will be * injected by DMA read or CPU read. * At the end of main file you can choose if single bit or multi bit is injected * and select particular ME/EE setup by comment/uncomment of particular function * calls. * * ------------------------------------------------------------------------------ * Test HW:   XPC567XKIT516 - MPC5674ADAT516 Rev.C, MPC567XEVBFXMB Rev.B * MCU:       PPC5674FMVYA264 * Terminal:  19200-8-no parity-1 stop bit-no flow control on eSCI_A * Fsys:      264/200/150/60 MHz * ********************************************************************************

With author's permission I am publishing presentation comparing e200 cores to each other and describing them in detail.   Document was created in year 2010, thus it does not deal with cores subsequently used with MPC57xx devices.   Thanks to Robert Moran for his great job.

Detailed Description: * This example shows, how to configure Mode entry module and enable required * peripherals only. RTC module is configured to create interrupt every 50ms. * Microcontroller is in in STOP mode most of the time and it is waken-up using RTC * interrupt. * * ------------------------------------------------------------------------------ * Test HW:         XPC560S 144LQFP, XPC56XX EVB MOTHEBOARD Rev.C * MCU:             PPC5606S 0M25V * Terminal:         * Fsys:            16MHz IRC * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          RAM, internal_FLASH * EVB connection:  Default * ********************************************************************************

******************************************************************************** * Detailed Description: * Preparation, configuration and execution of ONLINE(SHUTDOWN) build-in self-test. * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N65H * Target :  internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference * ******************************************************************************** Revision History: 1.0     Apr-04-2016     b21190(Vlna Peter)  Initial Version 1.1    Apr-28-2017     b21190(Vlna Peter)  Added cut 1N65H (2.1) *******************************************************************************/

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, * initializes and display notice via UART terminal and then terminal ECHO. * ------------------------------------------------------------------------------ * Test HW:        XPC5604B 100LQFP, XPC56XX EVB MOTHEBOARD Rev.C * MCU:             PPC5604BE MLL 1M27V * Fsys:             64/48 MHz * Debugger:      Lauterbach Trace32 *                      PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH, (not enough memory for RAM target) * Terminal:       19200-8-no parity-1 stop bit-no flow control on LINFLEX_0 * EVB connection: default * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * setup clock for peripherals, * * Initializes the MCU including the FlexCAN peripherals. * Configures the FlexCAN to transmit and receive a CAN message. * * In this config, CAN_0 transmits a message. CAN_2 receives the message. * CAN_0 MB0 is configured to send data. * * CAN_2 MB0 is configured to receive a message, interrupt is used. * * * ------------------------------------------------------------------------------ * Test HW:         MPC5746R-176LQFP, MPC57xx Motherboard * MCU:             PPC5743R 1N83M * Fsys:            PLL0 200MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, debug_ram mode) * EVB connection: * * Jumpers j37 and j38 on motherboard must be in position 2-3 * * Connect CAN P5.2 to CAN2 P4.2 on motherboard * Connect CAN P5.1 to CAN2 P4.1 on motherboard * * ******************************************************************************** Revision History: Version  Date         Author              Description of Changes 1.0      Jun-07-2017  Martin Kovar      Initial version

******************************************************************************** * Detailed Description: * Example shows MCU's temperature measurement using internal temperature sensor. * After basic initialization, the code initializes and calibrates eQADC, reads * test flash content and performs all necessary ADC measurement to calculate die * temperature. Results are then displayed in the terminal window. * ------------------------------------------------------------------------------ * Test HW:         XPC567XKIT516 - MPC5674ADAT516 Rev.C, MPC567XEVBFXMB Rev.B * MCU:             PPC5674FMVYA264 * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A * Fsys:            264/200/150/60 MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          RAM, internal_FLASH * EVB connection:  default * ********************************************************************************

******************************************************************************** * Detailed Description: * Example configures LinFlex and eDMA modules and then periodically sends notice * to the terminal window (19200-8-no parity-1 stop bit-no flow control). * * ------------------------------------------------------------------------------ * Test HW:         MPC5607BEVB * Target :         internal_FLASH, RAM * Terminal:        19200-8-no parity-1 stop bit-no flow control * Fsys:            40 MHz PLL with 8 MHz crystal reference * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Terminal:        19200-8-no parity-1 stop bit-no flow control via LINFlex0 * EVB connection:  default * ********************************************************************************

******************************************************************************** * Detailed Description: * Purpose of the example is to show how to generate Multi bit ECC error in * internal SRAM or FLASH (user can choose it in the option at the end of main * function) and how to handle this error with respect to constraints given by * MPC5675K architecture (ECSM/RGM/FCCU relation and ECC error handling through * reset). The example is only possible to run in internal_FLASH target. Power- * -on-reset is required after downloading the code into MCU's flash. The example * displays notices in the terminal window (setting specified below). No other * external connection is required. * Example also shows impact of enabled cache (macro OPTIMIZATIONS_ON). * * ------------------------------------------------------------------------------ * Test HW:        MPC5675KEVB * MCU:            PPC5675KFMMSJ in Lock-Step mode * Fsys:           180/150 MHz CORE_CLK * Debugger:       Lauterbach Trace32 *                 PeMicro USB-ML-PPCNEXUS * Target:         RAM, internal_FLASH * Terminal:       19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: default * ********************************************************************************

******************************************************************************** * Detailed Description: * * * This example demonstrate functionality of XBIC_1 error injection *  capability. The fault is generated on DMA transfer to SRAM. *  After fault generation it is propagated to FCCU unit as NCF[59]. * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N65H * Target :  internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference * ********************************************************************************

******************************************************************************** * Detailed Description: * A simple example configures eTPU engine B channels 0/1 for GPO/GPI. It is * needed to connect these pins by wire. Output wave is generated by eTPU GPIO * output function and inputs are read by fs_etpu_gpio_input_immed function * latching just current pin state. Pin history is displayed in ISR. * * Note: It is needed to configure IGF module, otherwise inputs does not pass * to eTPU module. * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection:  ETPUB0 (PortR P25-1) --> ETPUB1 (PortR P25-0) by wire * ********************************************************************************

******************************************************************************** * Detailed Description: * * This example shows usage of FlexPWM to generate independent * PWM signals from Submodule0. The PWMX output is set for 50% duty. * PWMA/PWMB outputs vary its duty cycles. * The DMA module is used to reload VAL2-5 registers. * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N65H * Target :  RAM, internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference * * EVB connection: * P8.12    - A[11] .. FlexPWM A[0] output * P8.11    - A[10] .. FlexPWM B[0] output * P11.10 - D[9] .. FlexPWM X[0] output * ********************************************************************************

******************************************************************************** * Detailed Description: * Example demostrates MCU behaviour when single bit RAM ECC error occurs by * intentional ECC error injection. * * ------------------------------------------------------------------------------ * Test HW:         xPC564xLKIT, PPC5643L Cut3 silicon * Target :         internal_FLASH * Fsys:            120 MHz PLL0 * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Terminal:        19200-8-no parity-1 stop bit-no flow control via LINFlex0 * EVB connection:  default * ********************************************************************************

******************************************************************************** * Detailed Description: * * Configures the MCANs to transmit and receive a CAN FD message with or without * bit rate switching for data phase. This is defined by BRS macro. * Baudrate during arbitration phase is set to 500kbps, during data phase 1Mpbs * because of PHY used on the EVB. * * In this config, MCAN_0 transmits a message. MCAN_1 receives the message. * * MCAN_0 sends message each 1sec. This interval is generated by PIT. * Single TX buffer is used to send n bytes. The message ID is changed for each * transmission. Two standard and 2 extended IDs are sent. * * MCAN_1 is configured to receive a message, ISR is used to read new message. * There are 2 standard and 2 extended ID filter tables defined. Classic filter * configuration is set, means filter ID & mask. * Messages with matched standard ID are received into RXFIFO_0, messages with matched * extended ID then stored in RXFIFO_1. *   * EVB connection: * * J37 and J38 to position 2-3 to connect MCAN1 TX/RX to transceiver * * CAN0-CANH on P15-1 to CAN1-CANH on P14-1 * CAN0-CANL on P15-2 to CAN1-CANL on P14-2 * * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A *           use USB connector (J21) on minimodule * * EVB connection:  ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) *                  ETPUA31 (PortP P23-14) --> USER_LED_2 (P7-2) * ********************************************************************************