The documentation points out that the Figure 32-1. Multipurpose Clock Generator (MCG) block diagram in KV5xP144M240RM.pdf is incorrect, the  /2 divider is NOT included in the feedback loop. It gives the formula to compute the VCO and MCGPLLCLK clock frequency and corresponding code.

As most of people familiar with FRDM-K64F which is a bit old but it is still a hot device in the market. This document focused on the ADC measurement to verify the deviation. In general, the sample code were modified /come with MCUXpresso SDK, which is an ADC polling example. ADC reading was done by two ways: 1) Polling the status register of ADC conversion complete flag until ADC conversion is done. 2) CPU core is in sleep right after ADC conversion is started by software trigger. Interrupt is generated when ADC conversion is done and CPU core wakes up by this interrupt. The value of ADC reading is measured 5000 times. And, it is averaged, also calculate max/min value. Finally, the standard deviation is calculated based on the 5000 measured value. PRINTF is a terminal console and print out by semi-hosting. Interrupt method or polling method can been selected by the define of INTERRUPT or POLLING. #define INTERRUPT 0   //ADC conversion wait for “INTERRUPT” should be defined to 1 #define POLLING 1 　　//ADC conversion wait for “POLLING” should be defined to 1

Hi: Kinetis's ADC have no multi channels sequence sampling function, compared with LPC's ADC. But we could use DMA for such case, attached are two demos: 1.multi_channels_edma_ADC_DMA_SW_TRIG Description: use SW trigger DMA transfer for 6 ADC channels, DMA ch0 is for ADC channels transfer, DMA ch1 is for ADC sample result transfer in DMA ch1 ISR, report ADC sample are done; 2.multi_channels_edma_ADC_DMA_LPIT_HW_TRIG Description: use LPIT timely trigger DMA transfer for 6 ADC channels, DMA ch0 is for ADC channels transfer, DMA ch1 is for ADC sample result transfer in DMA ch1 ISR, report ADC sample are done; but LPIT could trigger continuously without SW engage.

       FreeRTOS is a high quality, risk free, supported, free RTOS, and now it is already successful to porting more 35 architectures. As a popular RTOS, more and more embedded engineers considering it for their next project.        Next, I’m going to show you the steps of creating a MAPS-K22 FreeRTOS demo by IAR and I’ve also attached a template demo and FreeRTOS source code (Fig 1). Fig 1 FreeRTOS source code directories and files     1. Copy the FreeRTOS source code to ~\MAPSK22_SC\Libraries     2. Create FreeRTOS_Source group in the workspace, then add the source code (Fig 2) Fig 2 3. Add an application code in the main.c This is a very simple configuration. It creates two tasks, one software timer, and also uses a button interrupt. The two tasks communicate via a queue. The receiving task toggles the LED3 each time a value is received. Pressing user button K5 generates an interrupt. The interrupt service routine for which resets a software timer, then turn the LED1 on. The software timer has a five second period. The timer will expire when K5 has not been pressed again for a full five seconds. The callback function that executes when the timer expires simply turn the LED1 on again. Therefore, pressing K5 will turn the LED1 on, and the LED1 will remain on until a full five seconds pass without the button being pressed again. 4. Modify the Include Directories 5. Run the FreeRTOS demo After build the modified application code, then run it on MAPS-K22 board (Fig 3) Fig 3 IMPORTANT! Cortex-M FreeRTOS port specific configuration Configuration items specific to this demo are contained in ~\MAPSK22_SC\Libraries\RTOS\config\K22F51212\iar. The constants defined in this file can be edited to suit your application. In particular configTICK_RATE_HZ This sets the frequency of the RTOS tick interrupt. The supplied value of 1000Hz is useful for testing the RTOS kernel functionality but is faster than most applications require. Lowering this value will improve efficiency. configKERNEL_INTERRUPT_PRIORITY and configMAX_SYSCALL_INTERRUPT_PRIORITY See the RTOS kernel configuration documentation for full information on these configuration constants. configLIBRARY_LOWEST_INTERRUPT_PRIORITY and configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY These are equivalents to configKERNEL_INTERRUPT_PRIORITY and configMAX_SYSCALL_INTERRUPT_PRIORITY, but presented in a form suitable for passing into the Freescale NVIC_SetPriority() library function. The NVIC_SetPriority() function expects priorities to be in the range of 0 to 15 - 0 being the highest priority and 15 being the lowest priority.

This is a presentation used to explain the Low Power Timer adapted by Vicente Gómez, Freescale TIC. LPTMR Module Explanation. Connection Diagram. Operation Modes Hands-On Configure a timer so that it generates an interruption every x time.  Explicación del Low Power Timer presentado por Vicente Gómez, Freescale TIC.- Explicación de los Modulos LPTMR . Diagrama de conexiones. Modos de operación Hands-on Configurar un timer para que genere una interrupción cada X tiempo.

1. 飞思卡尔常用调试工具 2. 使用OpenSDA平台作为J-Link调试Kinetis 3. 使用OpenSDA平台作为USBDM调试Kinetis 4. 使用MTB模块快速跟踪定位Cortex-M0+指令执行状态（Use MTB in Cortex-M0+ to trace instructions） 5. KL25被加密，芯片锁死问题？ 6. 对比几款流行的Kinetis调试器速度 7. 修复Jlink固件损坏的方法 8. Jlink调试Kinetis L系列的使用方法 9. CMSIS-DAP调试器在IAR v7.1中问题（Probe not Found）修复 10. FRDM_KL26 虚拟串口安装失败的解决方法 11. 使用J-Link TCP-IP Server通过以太网远程下载程序到Kinetis 12.Kinetis LOCK的原因及解决方案​

I need to connect multi phy device with a single cpu. I want realize a follow hardware (see picture MultiPhys.jpg ). My dubt is if this schematic is correct. I need to send frame either PHY1 or PHY2. My application is like a gateway, it sends messages to network in selective way ( and it receives from every PHYs device ). Is it possible connect many PHY device with one RMII bus? what is the correct way to connect many PHY device on RMII bus? Anyone knowns documents that describe multi Phy configurations ?

Kinetis KV10 chip is the entry point of the V Series product, which are designed for a wide range of BLDC, PMSM and ACIM motor control and digital power conversion applications. KV10 is using ARM Cortex-M0+ core, the core frequency could up to 75MHz. And KV10 provides various feature powerful modules, such as ADC modules (2x 16-bit ADCs with two capture and hold circuits and up to 1.2 MS/s samples rate in 12-bit mode — simultaneous measurement of current and voltage phase, reduced jitter on input values improving system accuracy 12-bit mode) and DMA modules (4-channel DMA — reduced CPU loading for improved application performance). The demo is using PDB hardware trigger two ADC modules conversion (12-bit single-ended mode) at the same time; the two ADC modules will trigger each related DMA channels to transfer ADC result to ADC buffer located at SRAM (start from 0x2000_0000) when finish each conversion. The ADC DMA channel 0 will link to trigger DMA channel 2 to transfer ADC result from ADC result buffer to SPI FIFO. When DMA channel 2 transfer done, in related interrupt service routine will software trigger PDB to start the next round of ADC conversion. Below is the processing chart: For the customer requires to transfer 9 ADC conversion results out (5 of ADC0 and 4 of ADC1) , the ADC buffer need interleaved storage result from two ADC modules. Below diagram shows the detailed info: Below is the test result and test environment. It will take almost 15.4us to get and transfer all 9 12-bit ADC conversion results. The demo code is attached. The project is based on TWR-KV10Z32 Sample Code Package could be downloaded from here. Wish it helps.

I recently developed a Visual Studio .NET application that uses an OpenSDA virtual serial port to communicate with a FRDM-K64F. My serial protocol is a binary command-response protocol, which means that every time the .NET application sends a command packet to the serial port, it should always receive a response packet back. You can find more details about the protocol in the Freescale Intelligent Sensing Framework, but for the purposes of this document, all that matters is that every command should receive a response. My Visual Studio .NET application uses the SerialPort class, and worked beautifully...until I changed the OpenSDA firmware. Originally I used OpenSDA firmware from P&E; this time I had tried out Segger. In theory, this change should not have made a difference, however with the Segger firmware my .NET application never received response packets. I knew that the command packets were transmitting correctly from PC to board because they would turn a board LED on and off as expected. I tried using a binary terminal, RealTerm, to send commands to see if it would receive responses, and it did. So the problem had to be in my .NET application. After a lot of googling and some trial-and-error, I ultimately found that enabling the Data Terminal Ready (DTR) signal did the trick. Strangely, I didn't need to enable DTR in RealTerm. The moral of the story is that if you want to use Segger OpenSDA with a .NET SerialPort, then you must enable DTR. Fortunately this configuration also works with P&E and mbed OpenSDA.

The DOC focuses on how to access SDRAM based on K65 SDRAM controller, it describes the hardware connection especially the address connection, the SDRAM controller initialization,the code to access SDRAM.

Hello,      Is your clock correctly configured, what is its frequency?   You can monitor some of clocks in K0 MCU by routing it to  PTC3/CLKOUT pin. you can get it easily by selecting desired clock on  SIM_SOPT2[CLKOUTSEL] register and configuring PTC3 for CLKOUT function.   For example to monitor  1 KHz 1 low power osillator   LPO, ---------------------------------------------------------------------------------------------------------------------------- /*  ClockOutput options */ #define CLOCKOUT_FLASH_CLOCK    2 #define CLOCKOUT_LPO                       3 #define CLOCKOUT_MCGIRC                4 #define CLOCKOUT_RTC32KHZ            5 #define CLOCKOUT_OSCERCLK0       6 /* Configure clock output option according to  */               SIM_SOPT2 = SIM_SOPT2_CLKOUTSEL(CLOCKOUT_LPO); /* Configure PTC3 as clock output) */              PORTC_PCR3 = PORT_PCR_MUX(5);   //CLKOUT function selected on PTC3 ------------------------------------------------------------------------------------------------------------------------------------                 In attached document you can find captures of all clock options,  and notes on what need to be configured to get the clock output.                        Note:       Please note that Clock out (CLKOUT) on PTC3 is not currently shown in Signal Multiplexing and Signal Descriptions of RM.  It is already reported and will be fixed on next release of Reference Manual/Data sheet.

       RSA is a major cryptosystem in the public key cryptography. It is wildly used nowadays.  But why are we interested in elliptic    curve cryptography?   1. The smaller parameters can be used in elliptic curve cryptography (ECC) than with  RSA systems at a given security level.       2. In particular, private-key operations (such as signature generation and decryption) for ECC are many times more efficient        than RSA private-key operations.     3. Public-key operations (such as signature verification and encryption) for ECC are more efficient than RSA if a  bigger       encryption exponent e is selected for RSA.           The advantages offered by ECC can be important in environments where processing     power, storage, bandwidth, or power consumption is constrained.              KL26Z MCU is 48 MHz ARM Cortex-M0+ core, there are only 128K ROM and 16K RAM on chip. When you want to use the    public key cryptography, the elliptic curve cryptography may be a good choice for this low cost MCU.        This example implements a simple ECC certification from PC to USB.  After certification,     USB can get encrypted data from PC and decrypt these data to plain text.   KL26-Freedom : 1.   Open the porject file at folder kecc/build/cw/KECC/kl26_ecc/test   2.  Build the image and flush it with OpenSDA.   3. Open the Tera Term and start running image on KL26Z     PC running environment:     1. Install  these packets on PC:         python-2.7.3.msi, pycrypto-2.6.win32-py2.7.exe, pyserial-2.7.win32.exe and pywin32-219.win32-py2.7         2. Connect USB cable to KL26Z Freedom and install the CDC driver with       Freescale_CDC_Driver_Kinetis.inf driver     3. Open the application folder and run the usbkey.py.                 4. If USB admits  PC certification message, then PC can put encrypted data to USB.               This  demo only tested on WIN7 64bit. IF you can't open the CDC port, you need reset the KL26Z freedom board and restart the usbkey.py.     This ECC demo uses a library including some security toolkits for ECC certification.     1. Signature and verify : ECDSA     2. Key exchanging         :ECCRYPT    3.  Digest                         : SHA1    4. Symmetric   cipher     : AES and base64      All tools and codes are in following KECC.zip. Original Attachment has been moved to: kecc.zip

The Kinetis family has abundant low power mode. Customers may confused to figure out the different way to wake up from the low power mode. 1)  In VLPR, VLPW:  the NVIC remains sensitive to interrupts, so any interrupt will be serviced. 2)  In Stop, VLPS:  the device can be waked up by USB wake up interrupt only. 3)  In LLS, VLLSx:  the device won't be able to wake up from any USB source. 4)  LLWU is used to wake up, so customer would able to wake up from any of the available LLWU wake up sources. As for the USB module, there has two different interrupts for a USB resume event. One asynchronous to be able to wake from a low power mode, which is triggered by change in the state of the USB lines. The other is synchronous and is triggered only after 2.5 us of detecting a K state (D+ = 0, D- = 1, for Full Speed). The application is responsible to transition to the low power mode whenever it requires it, and for this purpose it must check the device state as reported by the USB stack. When a suspend condition is detected in the bus, the SLEEP interrupt triggers and the stack changes its state to suspend; then the application will transition to the low power mode. When this SLEEP interrupt occurs, the asynchronous wake interrupt is enabled, and is disabled when it is triggered (this is required by the module to clear the interrupt). In normal conditions, the synchronous resume interrupt or the reset interrupt will be triggered afterwards, causing the stack to transition its state to other than suspend. The application can then know that communication is active again and will avoid entering the low power mode again.

Hi All, attached bootloader is a short program that allows possibility to update existing firmware in Kinetis-M microcontroller device. It consist of Master PC application and a tiny slave application that runs on target device. It uses UART communication.

My customer wanted to use K60 in his design but he only has the Keil IDE, so I helped to port some examples in KINETIS_SC for him as a starting point. The attachment is my porting work, which also includes a exe file to create new keil project. You may refer to "keil\build\uv4\make_new_project_keil.exe" for details. Hope that helps, B.R Kan

The following file contains codewarrior code that was migrated from the IAR example code in the sample code package at the freescale webpage. It contains the following examples: adc_demo freedom_greem_led freedom_red_led lcd_rtc_lowpower PIT_basic sLCD_freedom uart_low_power_wu_dut Regards

Hello. I am trying to use a PIT interrupt. I had never used Kinetis so there are certain things which with I am not familiarized yet. once i have created de PE code, cleaned and then I build the proyect, the following error pops up 'undefined reference to int_disp'. What it is about? Where should I write my ISR fuction? Does the ISR pit function has to have an specific name so as to be recognised by PIT.c?

   CodeWarrior v10.6 and KDS are integrated development tools which are based on Eclipse, these two IDEs provide easy way to build project when using the GUI, but some engineers still want to build their projects from command line to do automated builds. This document provides examples on how to do it! Build project in CodeWarrior from command line: For a CW v10.6 created project, CW provides the “Make” tool and can also generate the needed “MakeFile” to build this project out of eclipse GUI. The below are the steps: Create and new project “k22_makefile” in CW v10.6, you will see there are two build configurations: RAM & FLASH Launch “cmd prompt” in Windows and go to “eclipse” folder of CW installation Now, you can generate the makefile for configuration FLASH by executing the below command ecd.exe –generateMakefiles –project “C:\workspace_cmd\k22_makefile” –config FLASH Now, checking the “FLASH” subfolder in project location, you will see “makefile” is generated. 4.To use “make” tool convenient, we can define an environment variable pointing to {CW}\gnu\bin where “make” is located. See command as below: 5. Go to the configuration folder “FLASH” where the project’s makefiles are located and run the follow commands to build the project. %MCU_BIN%\make.exe PS: to get more information of make and ecd, please just run the below command: Ecd.exe –help Make.exe –help Build project in KDS from command line: Compare with CodeWarrior, it is much easier to build an application in command mode. KDS provides a command “eclipse.exe” with which you can build a project with only two steps. In this example, I have created an application with name “cmd_ke02”, and the workspace path is “C:\wks_kdscmd”. To build the application in cmd, please first launch command mode in Windows system and then go to {KDS}\eclipse. Then, you need import the application into current workspace in the below command: eclipsec.exe -nosplash -application org.eclipse.cdt.managedbuilder.core.headlessbuild -data "C:\wks_kdscmd" -import "C:\wks_kdscmd\cmd_ke02" then, build the project with the below command: eclipsec.exe -nosplash -application org.eclipse.cdt.managedbuilder.core.headlessbuild -data "C:\wks_kdscmd" -build "cmd_ke02" For more details of building project from command line in KDS, please refer: http://mcuoneclipse.com/2014/09/12/building-projects-with-eclipse-from-the-command-line/

From K61/K64/K66 reference manual/ datasheet, it is mentioned that the SDHC clock can be set up to 50MHz. But from the SDHC timing spec, SDHC output timing violate SD specification if SDHC clock is 50MHz, because output delay (SD6 tOD) is max 6.5ns.  SD specification require setup time at SD card 6ns, then output delay should less than 4 ns if SDHC clock is 50MHz. In other word, according to the SD card specification, input set-up time is minimum 6ns, then maximum of SD6 should be 4ns in order to support 50 MHz clock frequency. So we recommend customer to drop the SDHC clock frequency to 40MHz, then the 6.5ns output valid time will allow them to meet the 6ns setup requirement for the card.