The FlexIO module was first introduced in the Freescale Kinetis KL43 family. It is capable of emulating various serial communication protocols including: UART, SPI and I2C. The FlexIO module is very flexible and you can configure it according to your communication needs. The main components of the FlexIO module are the shifters, timers, and pins. Data is loaded onto a shifter and a timer is assigned to generate the shifter clock and use a pin to output the data from the shifter. The KL43 FlexIO module has 4 32-bit shifters, 4 16-bit timers and 8 bidirectional I/O pins. Each shifter and timer has its own configuration registers. The most important registers that configure the whole FlexIO behavior are the SHIFTCFG, SHIFTCTL, TIMCFG, TIMCTL and TIMCMP registers. There are other registers that contain status flags, interrupt enabling bits and the buffers for the shifters. Shifters have a timer assigned to them to generate the shift clock and it can be configured to shift data in or out. When the shifter is configured to transmit mode, the data from the SHIFTBUF register will be loaded to the shifter and the shifter status flag will be set meaning that the shifter is ready to start the transmission. In receive mode, the shifter status flag is set when SHIFTBUF has been loaded with the data from the shifter, and the status flag is cleared when the SHITBUF register is read. The timers are highly configurable, they can use external or internal triggers to generate certain conditions to reset, enable and disable the timer. The triggers can be a timer output, shifter status flag, pin input or an external trigger input. They can be configured to enable in response to a trigger, pin or shifter condition. Each shifter or timer can be configured to use any FlexIO pin with either polarity. The pins can be used as an input or output. A pin configured as an input for a timer can be used to receive a clock and use it as the shifter clock that is assigned to this timer. Once everything is configured you need to read/write the shifter buffers and the shifter and timer status flags to start a transmission or to read the contents of the shifter buffer when receiving data. The following diagram gives a high-level overview of the configuration of FlexIO timers and shifters. Figure 1. FlexIO block diagram In the following example configuration, the FlexIO module will be configured as a transmitter. It will use one shifter, two timers, and three pins. The pins will be used for the outputs of the shifter and the two timers. One timer will be used as the shifter clock and the other timer will be used as a chip select to show when a transmission is being made. The FlexIO will be configured to have a baud rate of FlexIO clock/4 and will do an 8-bit transmission. Figure 2. Example transmission Timer 0 Timer Configuration 0 Register (FLEXIO_TIMCFG0) = 0x00002200 TIMOUT = 0    Timer output is logic one when enabled and is not affected by timer reset. TIMDEC = 0    Decrement counter on FlexIO clock, Shift clock equals Timer output. TIMRST = 0    Timer never reset. TIMDIS = 2    Timer disabled on Timer compare. TIMENA = 2    Timer enabled on Trigger high. TSTOP  = 0    Stop bit is disabled. TSTART = 0    Start bit disabled. Timer Control 0 Register (FLEXIO_TIMCTL0) = 0x01C30101 TRGSEL = 1    Trigger select. Shifter 0 status flag. TRGPOL = 1    Trigger active low. TRGSRC = 1    Internal trigger selected. PINCFG = 3    Timer pin output. PINSEL = 1    Timer pin 1 select. PINPOL = 0    Pin is active high. TIMOD  = 1    Dual 8-bit counters baud/bit mode. Timer Compare 0 Register (FLEXIO_TIMCMP0) = 0x00000F01 TIMCMP = 0x00000F01        Configure 8-bit transfer with a baud rate of FlexIO clock/4. Set TIMCMP[15:8] = (number of bits x 2) - 1. Set TIMCMP[7:0] = (baud rate divider / 2) - 1. In our case we want an 8-bit transfer so TIMCMP[15:8] = 0xF and a baud rate divider of 4 so TIMCMP[7:0] = 0x1. Timer 1 Timer Configuration 1 Register (FLEXIO_TIMCFG1) = 0x00001100 TIMOUT = 0    Timer output is logic one when enabled and is not affected by timer reset. TIMDEC = 0    Decrement counter on FlexIO clock, Shift clock equals Timer output. TIMRST = 0    Timer never reset. TIMDIS = 1    Timer disabled on Timer N-1 disable. TIMENA = 1    Timer enabled on Timer N-1 enable. TSTOP  = 0    Stop bit is disabled. TSTART = 0    Start bit disabled. Timer Control 1 Register (FLEXIO_TIMCTL1) = 0x00030283 TRGSEL = 0    Trigger select. Doesn’t matter because we won’t use a trigger. TRGPOL = 0    Trigger active high. TRGSRC = 0    External trigger selected. PINCFG = 3    Timer pin output. PINSEL = 2    Timer pin 2 select. PINPOL = 1    Pin is active low. TIMOD  = 3    Single 16-bit counter mode. Timer Compare 1 Register (FLEXIO_TIMCMP1) = 0x0000FFFF TIMCMP = 0x0000FFFF Never compare. Shifter 0 Shifter Control 0 Register (FLEXIO_SHIFTCTL0) TIMSEL = 0    Timer 0 select. TIMPOL = 0    Shift on posedge of Shift clock. PINCFG = 3    Shifter pin output. PINSEL = 0    Shifter pin 0 select. PINPOL = 0    Pin is active high. SMOD   = 2    Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. Shifter Configuration 0 Register (FLEXIO_SHIFTCFG0) INSRC  = 0    The input source of the shifter is from a pin. In our cause this doesn’t matter because our shifter is set as transmit mode. SSTOP  = 0    Stop bit disabled. SSTART = 0    Start bit disabled. Once all the FlexIO components are configured you have to enable the FlexIO instance by setting the FLEXEN bit in the FLEX_CTRL register. Initially, the shifter status flag is set and is cleared each time the SHIFTBUF register is written. This flag is set each time the SHIFTBUF data has been transferred to the Shifter (SHIFTBUF is empty).  The shifter status flag 0 is configured to be the trigger of the timer 0, so as soon as the status flag is cleared, the timer 0 will be enabled because TIMENA = 2 (Timer enabled on Trigger high)and TRGPOL = 1 (Trigger active low). The shifter will begin to shift out the data on the positive edge of the clock (TIMPOL = 0) until the timer is disabled. The timer will disable when the timer counter reaches 0 (TIMDIS = 2). The timer 1 is configured to be active (low) when the timer 0 is enabled. This is because TIMDIS = 1 and TIMENA = 1. The compare register is configured to 16-bit counter and set to 0xFFFF. With this value the timer will never compare and always be active when the timer is enabled. To send data, you have to make sure that the previous transaction was completed and you can check this by reading the TIMSTAT flag. This flag sets each time the timer counter reaches 0. Once the TIMSTAT flag is set, you clear it and write your new data to the SHITBUF register to start the transaction. The KSDK 1.2.0 has drivers and a HAL to facilitate the configuration of the FlexIO module. Some of the important functions are: FLEXIO_DRV_Init(uint32_t instance, const flexio_user_config_t *userConfigPtr); Use this function to initialize the FlexIO module before using it. In this configuration you can change the settings in the FLEXIO_CTRL register such as: Doze Enable, Debug Enable, Fast Access and software reset. FLEXIO_HAL_ConfigureTimer(FLEXIO_Type * base, uint32_t timerIdx, const flexio_timer_config_t *timerConfigPtr); Use this function to configure a timer in the FlexIO. This function uses a configuration structure that can change the TIMCFG, TIMCTL and TIMCPM registers. FLEXIO_HAL_ConfigureShifter(FLEXIO_Type * base, uint32_t shifterIdx, const flexio_shifter_config_t *shifterConfigPtr); Use this function to configure a shifter in the FlexIO. This function uses a configuration structure that can change the SHIFTCFG and SHIFTCTL registers. FLEXIO_HAL_SetShifterBuffer(FLEXIO_Type * base, uint32_t shifterIdx, uint32_t value); Use this function to start a transmission. When writing to the SHIFTBUF register, the Shifter Status Flag is cleared. FLEXIO_DRV_Start(uint32_t instance); Use this function to enable the FlexIO module by setting the FLEXEN bit in the FLEX_CTRL register. FLEXIO_HAL_GetTimerStatusFlags(FLEXIO_Type * base); This function returns the contents of the TIMSTAT register. You can use this function to check when a transmission is finished. FLEXIO_HAL_ClearTimerStatusFlags(FLEXIO_Type * base, uint32_t mask); This function clears a specific Timer Status Flag. You can use this function to clear a flag after you read that the flag was set. To change the frequency of the transmission you have to change the value of the TIMCMP register. In dual 8-bit counters baud/bit mode, the lower 8-bits configures the baud rate divider equal to (CMP[7:0] + 1) * 2 and the upper 8-bits configure the number of bits in each word equal to (CMP[15:8] + 1) / 2. In our example the baud rate divider is set to 4, this means CMP[7:0] has the value 1. The number of bits transmitted is set to 8, this means CMP[15:8] has the value 0xF. Let’s change the baud rate divider to 32. To obtain the CMP[7:0] value, we will have to solve the simple equation: 32 = (CMP[7:0]+1)*2 CMP[7:0] = 15=0xF Now let’s change the number of bits to 16. The CMP[15:8] value is defined by: 16 = ((CMP[15:8]+1))/2 CMP[15:8] = 31=0x1F The value for the TIMCMP for the timer 0 has to be 0x00001F0F to get a baud rate divider of 32 and a word length of 16 bits. The waveform will look as follows. Figure 3. 16-bit transmission By default the shifter in the FlexIO transmits the LSB first. To change the transmission order, you have to write to the SHIFTBUFBIS (Bit swapped) register instead of the SHIFTBUF register. There are also other buffer registers: SHIFTBUFBYS and SHIFTBUFBBS. The first register swaps the bytes and the second register swaps the bytes and bits at the same time. When using one of these registers you have to be careful to consider that the length of the SHIFTBUF registers is of 32 bits, so if you choose to use the SHIFTBUFBIS for a transmission and your transmission length is not of 32 bits, you have to start writing your data starting from the most significant bit. The following image shows a MSB transmission. The value 0x6AED0000 was written to the SHIFTBUFBIS register. Figure 4. MSB 16-bit transmission The FlexIO module supports automatic start and stop bit handling. All you have to do is change the SHIFTCFG and the TIMCFG configuration bits. In the SHIFTCFG register set SSTOP to 11 if you want the stop bit to have the value 1, and set the SSTART to 10 if you want the stop bit to have the value 0. In the TIMCFG register set the TSART to 1 and the TSOP to 10. The transmission will look as the following image. Data transmitted 0x0F. Figure 5. Transmission with start and stop bit Changing the phase of the clock is very easy, you just have to set the TIMPOL bit to 1 in the SHIFTCTL register. Figure 6. Shift on negedge of Shift clock The conditions to disable and enable the timers can be configured by changing the TIMENA and TIMDIS values in the TIMCFG register. In our example the timer is enabled by the trigger high. The trigger can be set to be an external pin, a shifter status flag, or a timer output. In our case the trigger was set to the shifter status flag, but you can change this configuration to your communication needs. The timer can also be enabled when the previous timer is enabled, on a certain pin edge, or with a combination of pins and triggers. The timer in the example above disables on the timer compare. This means that when the timer counter reaches zero, the timer will disable automatically. The timer counter is loaded with the timer compare value every time it reaches zero or when it is first enabled.  The timer can also be disabled by other conditions such as: when the previous timer is disabled, on a trigger falling edge, on a pin edge, or on a combination of these. Each pin can be configured to be active high or low. When a pin polarity is changed it only affects the output of the pin, for example, if a timer is set to be the shifter clock and you change the pin polarity, the shifter clock will not change its polarity, only the output to the pin from the timer will change. The configuration for the polarity of the pins is located in the TIMCTL and SHIFTCTL. When the PINPOL value is changed to 1, the pin is active low. In the following image the polarity of the timer pin and the shifter pin was changed to 1, so they are active low. Figure 7. Timer and Shifter active low The FlexIO module can generate an interrupt from 3 sources: Shifter error, Shifter status flag and Timer status flag. To enable the interrupts you need to set the bits in the SHIFTSIEN,SHIFTEIEN and TIMIEN. If you are using KSDK you can enable the interrupt in NVIC by setting true .useInt in the FlexIO user config that the function FLEXIO_DRV_Init utilizes. The default handler for the interruption is named UART2_FLEXIO_IRQHandler. The following example configuration will configure the FlexIO module as a receiver. This configuration works with the first example configuration shown. Both tower boards (TWR-KL43Z48M) have to be connected as shown further below in the Table 1 Hardware connnections. The FlexIO module will use one Shifter, one timer, and three pins. The pins will be used for the input of the shifter, the input clock for the timer and the trigger for the timer. The timer will use pin 1 as an input and its output will be the same as the input clock. The trigger for the timer will be the transmitter chip select pin and it will be used to enable or disable the timer. The FlexIO will be configured to do an 8-bit transmission. Shifter 0 Shifter Control 0 Register (FLEXIO_SHIFTCTL0) = 0x00800001 TIMSEL = 0    Timer 0 select. TIMPOL = 1    Shift on negedge of Shift clock. PINCFG = 0    Shifter pin output disabled. PINSEL = 0    Shifter pin 0 select. PINPOL = 0    Pin is active high. SMOD   = 1    Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. Shifter Configuration 0 Register (FLEXIO_SHIFTCFG0) = 0x00000000 INSRC  = 0    The input source of the shifter is from a pin. In our cause this doesn’t matter because our shifter is set as transmit mode. SSTOP  = 0    Stop bit disabled. SSTART = 0    Start bit disabled. Timer 0 Timer Configuration 0 Register (FLEXIO_TIMCFG0) = 0x01206602 TIMOUT = 1    Timer output is logic zero when enabled and is not affected by timer reset. TIMDEC = 2    Decrement counter on Pin input (both edges), Shift clock equals Pin input. TIMRST = 0    Timer never reset. TIMDIS = 6    Timer disabled on Trigger rising edge. TIMENA = 6    Timer enabled on Trigger falling edge. TSTOP  = 0    Stop bit is disabled. TSTART = 1    Start bit enabled. Timer Control 0 Register (FLEXIO_TIMCTL0) = 0x04C00103 TRGSEL = 4    Trigger select. Pin 2 input. TRGPOL = 1    Trigger active low. TRGSRC = 1    Internal trigger selected. PINCFG = 0    Timer pin output disabled. PINSEL = 1    Timer pin 1 select. PINPOL = 0    Pin is active high. TIMOD  = 3    Single 16-bit counter mode. Timer Compare 0 Register (FLEXIO_TIMCMP0) = 0x0000000F TIMCMP = 0x0000000F Configure 8-bit transfer. Set TIMCMP = (number of bits x 2) - 1. The shifter status flag is set every time the SHIFTBUF register has been loaded with data from the shifter. This occurs every time that the transmitter sends 8 bits of data. You can read the shifter status flag by polling or by enabling an interrupt based on your needs. This flag clears automatically when you read the SHITBUF register. During the transmission, the first thing that happens is that timer from the receiver will be enabled because the chip select signal from the transmitter is configured as a trigger. Once the timer is enabled, the timer will begin to decrement on the pin input, this means that the shifter clock of the receiver will be equal to the pin input. The transmitter shifter is configured to shift data out on the positive edge of the clock and the receiver shifter is configured to shift data in on the negative edge of the clock. After 8 bits have been transmitted, the compare register from the receiver will reach 0 and this generates an event to store the data from the shifter to the SHITBUF register and the Shifter Status Flag will be set. Finally the timer will be disabled by the chip select signal and keep waiting for another transaction. The hardware connections are shown in the following table. Signal name TWR-KL43Z48M transmitter TWR-KL43Z48M receiver Pin name Board Location Pin name Board Location Serial Data PTD0/FXIO0_D0 B46 PTD0/FXIO0_D0 B46 Clock PTD1/FXIO0_D1 B48 PTD1/FXIO0_D1 B48 Chip Select PTD2/FXIO0_D2 B45 PTD2/FXIO0_D2 B45 GND GND B2 GND B2 Table 1. Hardware connections Figure 8. Hardware connections The example projects for the FlexIO transmitter and receiver are developed in KDS 3.0.0 with KSDK 1.2.0. The application lets the user communicate with the transmitter via a serial terminal and the transmitter sends each character to the receiver via FlexIO and the receiver displays the received character on another serial terminal. To be able to compile the project, first you need to compile the library located in C:\Freescale\KSDK_1.2.0\lib\ksdk_platform_lib\kds\KL43Z4. Once the two TWR-KL43Z48M are connected as described above, import both projects into KDS, compile the platform library, and both projects. Open two serial terminals configured to 115200 bauds and run each project on a different tower. On the transmitter terminal you can write anything and it will be displayed and transmitted to the receiver tower via FlexIO and will be shown on the other terminal. Figure 9. FlexIO example application. Transmitter (left terminal). Receiver (Right terminal). The FlexIO module is also capable of generating a PWM signal by configuring one of its timers to the Dual 8-bit counters PWM mode. This mode is configured by writing 01 to TIMOD in the TIMCTL register. In this mode, the lower 8-bits of the counter and compare register are used to configure the high period of the timer output and the upper 8-bits are used to configure the low period of the timer output. The shifter bit count is configured using another timer or external signal. To calculate the frequency of the PWM signal you have to add the lower 8-bits of the counter and the upper 8-bits and divide it by the FlexIO clock*2 (Only if the timer is configured to decrement on the FlexIO clock.) The frequency of the PWM signal is given by: f = (FlexIO clock)/(TIMCMP[15:8]+TIMCPM[7:0]+2) To calculate the TIMCMP values to get a certain frequency you can solve the equation for TIMCMP TIMCMP[15:8]+TIMCPM[7:0] = (FlexIO clock)/f-2 For example, let’s say we want a 200kHz PWM signal, by using the formula above and using the FlexIO clock of 48MHz, we get that the sum of the TIMCMP values must be 238. If we want a 50% duty cycle we need to write the value 238/2 to the lower and upper 8 bits of the TIMCMP register. The waveform generated by these settings is shown in the figure below. Figure 10. 200kHz 50% duty cycle PWM signal To change the duty cycle you need to change the values of TIMCPM[15:8] and TIMCPM[7:0] but without changing the sum of both values, otherwise the frequency will also be altered. For example, if we need a 20% duty cycle we multiply 0.20*238 and 0.8*238. We round up the results and get TIMCPM[7:0] = 48 and TIMCPM[15:8] = 190. The waveform generated will look as shown in the figure below. Figure 11. 200kHz 20% duty cycle PWM signal

Reference Solution being developed with Kinetis V (also can be done with a Kinetis K device) of a Class-D audio amplifier. 16-bit ADC sampling the audio input FlexTimer doing the PWM's for the Class-D amplifier DC/DC switched power supply with input of 12V and output of 130V to 180V (generates the power you need for making some good noise - 1kW) being controlled by the Kinetis MCU also. Capabiltiy of Audio processing/filtering using the Cortex-M4 DSP capabilities. Solution originally designed for cost-effective Automotive aftermarket sound systems. But can be adapted for implementing other audio amplifier applications also in the consumer space! Can you thing of cool applications/markets that this solution can be also quickly adapted? Soon, plan to make the reference solution design files available in the community. Stay tunned. Cheers! PK

http://dorkbotpdx.org/blog/paul/teensy_audio_library_gets_spdif_support Digital optical audio output from kinetis based teensy 3.1

The mbed Compiler delivers full online editor. it provides a lightweight online C/C++ IDE that is pre-configured to let you quickly write programs, compile and download them to run on your mbed Microcontroller. The only weakness is that it doesn’t have debug feature. In fact, you don't have to install or set up anything to get running with mbed. Because it is a web app, you can log in from anywhere and carry on where you left off, and you are free to work on Windows, Mac, iOS, Android, Linux, or all of them. Currently, mbed Compiler support: FRDM-KL25Z FRDM-KL46Z FRDM-KL05Z FRDM-K20D50M FRDM-K22F Ethernet IoT Starter Kit This article will introduce how to use mbed Compiler to develop code on Freescale FRDM board. Summary:  we can use mbed Online Compiler edit, build, generate binary file. But CAN’T debug. With mbed FRDM KL25z Upgrade pakage, we can burn binary file to board with drag and drop. Its really simple, and it's free, because it is a web based compiler, multi-platforms are supported. so lets get started!

BSDL file for the MK20DN512VLL10.

Kinetis E series MCUs target to applications where require high performance on EMC/ESD. With 5V power supply and robust IO design, Kinetis E series MCUs can help customer for a robust design. Here take a Microwave Oven demo as example, shares how to make a robust design with Kinetis E Series MCU, from hardware, software perspective.

KBOOT learning diary Overview      FSL’s already released the KBOOT v1.1.0 in Dec, 2014 and the v1.2.0 will be released in Jun, 2015. KBOOT is an innovation bootloader solution instead of former and it just seems like a platform for quick and easy programming the Kinetis MCUs. KBOOT will make the developers to save the effort for design the bootloader, even it support the developers to customize the bootloader.        KBOOT provides two ways for implementing, ROM bootloader and Flash bootloader, ROM bootloader is only applicable to the Kinetis MCUs which already integrate the ROM and the KBOOT application reside in it. So the ROM bootloader is available during the entire product life cycle.  The opposite side, the Kinetis MCUs without ROM can be programmed through the Flash bootloader. For the Flash bootloader, it runs into RAM and receive the application image, after it program the image into the Flash completely, then it Flash bootloader will go to die, in another word, it will no longer be available again. Table 1 shows supported Kinetis MCUs. Table 1 Support Kinetis Devices        KBOOT’s supported to program the target through the UART, SPI, I2C, USB HID communication and it will also support the MSD Device and MSD HOST mode, Ethernet, etc in future. And developers can use blhost application or GUI tool as the host tool to communicate with the bootloader, then program the application code in flash via the bootloader. Implementing        In these user guides as follow: Getting Started with the Kinetis ROM Bootloader, Getting Started with the Kinetis Flashloader, Kinetis blhost User's Guide, Kinetis Updater User's Guide, you can find a completely procedure to program the application code via bootloader. Exception However I’ve encountered an issue when I tried to use the blhost application to communicate the FRDM-KL03Z (Fig1), it still couldn’t establish a connection, as Fig 2 shows. Fig 1 Fig 2 Workaround       The issue will disappear after choose a lower baud rate when blhost application communicate with the FRDM-KL03Z board after I validated. And the whole procedure to program application code as follow.       1. Establishes the connection        2. Erases the entire flash array       3. Programs the application code       4. Application code runs

Latest published errata for ISF 2.1

   1.  K60 eDMA 16-channel implementation Local memory containing transfer control descriptors for each of the 16 channels 32-byte TCD stored in local memory for each channel    2.  DMA memory to memory performance In the traditional M2M data movement, performance is best expressed as the peak data transfer rates In most implementations, this transfer rate is limited by the speed of the source and destination address spaces.     3.  eDMA peak transfer rate   4. Performance test         With K60 100MHz (TWR-K60D100M), implement internal SRAM-SRAM eDMA data transfer. If  transfer size setting as 32-bit in TCD Transfer Attributes (DMA_TCD_ATTR), there will has one wait state during each read/write. That's why the DMA performance doesn't up to 200MB/s as the manual stated.       We highly recommend setting DMA transfer size to 16-byte at DMA_TCD_ATTR register, it will much increase the DMA performance.(Get 162MB/s transfer rate with TWR-K60D100M board.) 5.  Testing code attached.

       RSA is a major cryptosystem in the public key cryptography. It is wildly used nowadays.  But why are we interested in elliptic    curve cryptography?   1. The smaller parameters can be used in elliptic curve cryptography (ECC) than with  RSA systems at a given security level.       2. In particular, private-key operations (such as signature generation and decryption) for ECC are many times more efficient        than RSA private-key operations.     3. Public-key operations (such as signature verification and encryption) for ECC are more efficient than RSA if a  bigger       encryption exponent e is selected for RSA.           The advantages offered by ECC can be important in environments where processing     power, storage, bandwidth, or power consumption is constrained.              KL26Z MCU is 48 MHz ARM Cortex-M0+ core, there are only 128K ROM and 16K RAM on chip. When you want to use the    public key cryptography, the elliptic curve cryptography may be a good choice for this low cost MCU.        This example implements a simple ECC certification from PC to USB.  After certification,     USB can get encrypted data from PC and decrypt these data to plain text.   KL26-Freedom : 1.   Open the porject file at folder kecc/build/cw/KECC/kl26_ecc/test   2.  Build the image and flush it with OpenSDA.   3. Open the Tera Term and start running image on KL26Z     PC running environment:     1. Install  these packets on PC:         python-2.7.3.msi, pycrypto-2.6.win32-py2.7.exe, pyserial-2.7.win32.exe and pywin32-219.win32-py2.7         2. Connect USB cable to KL26Z Freedom and install the CDC driver with       Freescale_CDC_Driver_Kinetis.inf driver     3. Open the application folder and run the usbkey.py.                 4. If USB admits  PC certification message, then PC can put encrypted data to USB.               This  demo only tested on WIN7 64bit. IF you can't open the CDC port, you need reset the KL26Z freedom board and restart the usbkey.py.     This ECC demo uses a library including some security toolkits for ECC certification.     1. Signature and verify : ECDSA     2. Key exchanging         :ECCRYPT    3.  Digest                         : SHA1    4. Symmetric   cipher     : AES and base64      All tools and codes are in following KECC.zip. Original Attachment has been moved to: kecc.zip

ROM Bootloader KL43 chip with Kinetis Bootloader residing in the on on-chip read-only memory (ROM), can interface with USB, I2C, SPI, and LPUART peripherals in slave mode and respond to the commands sent by a master (or host) communicating on one of those ports. When KL43 chip with a blank flash, the Kinetis bootloader will execute automatically. Once the flash is programmed, the value of the FOPT field at Flash address0x40D will determine if the device boots the ROM bootloader or the user application in flash. The FTFA_FOPT [BOOTSRC_SEL] will select if boot from customer application (Flash) or boot from ROM bootloader. For example:       When Flash address 0x40D value is 0xFF, boot source is ROM bootloader;       When Flash address 0x40D value is 0x3D, boot source is Flash (Customer application). There with hardware pin(/BOOTCFG0) to control if boot from user application or ROM bootloader with FTFA_FOPT[BOOTPIN_OPT] bit . When FTFA_FOPT[BOOTPIN_OPT]  = 0, it forces boot from ROM if /BOOTCFG0 pin set to 0. blhost utility application The blhost utility is an example host program used to interface with devices running the Kinetis bootloader. The blhost application is released as part of Kinetis bootloader release package available on www.freescale.com/KBOOT . The blhost application default located at C:\Freescale\FSL_Kinetis_Bootloader_1_1_0\bin\win folder. About how to use blhost application, please check KBLHOSTUG document for more detailed info. Call Rom Bootloader from customer application In general, if customer application was programmed, the boot option should be change to Boot from Flash. If customer want to call the ROM bootloader during the application running, customer can refer below example. Set a signal for application code to call the ROM bootloader, such as press a button. In this demo, we use FRDM-KL43Z board SW3 (PTC3) to call the ROM bootloader. //Initalize PTEC3 as GPIO button PORT_Init (PORTC, PORT_MODULE_BUTTON_MODE, PIN_3, 0, NULL); GPIO_Init (GPIOC, GPIO_PIN_INPUT, PIN_3); The bootloader entry point for customer application to call the ROM bootloader.  //prototype of the entry point definition void run_bootloader(void * arg); //Variables uint32_t runBootloaderAddress; void (*runBootloader)(void * arg);   // Read the function address from the ROM API tree. runBootloaderAddress = **(uint32_t **)(0x1c00001c); runBootloader = (void (*)(void * arg))runBootloaderAddress; in <main.c> routine to call the ROM bootloader:   while (1)   {     if ((GPIOC_PDIR & (1 << 3)) == 0)     {       // Start the bootloader. runBootloader(NULL);     }   } Press SW3 button of FRDM-KL43Z board will call ROM bootloader.  Customer could continue to debug the code until the ROM bootloader be called. If customer debug into the runBootloader(NULL) function, there will stop at fixed address: 0x1C00_00C0. In fact, during call the ROM bootloader function , there will setting some parameters and then reset the KL43. When KL43 back from reset, it will boot from ROM bootloader. That reset will cause debugger disconnect with the KL43 product. More detailed info, please check attached demo code. BTW: The demo project is [frdm_led_test] inside of KL43 baremetal sample code, which could be downloaded from here.

Actually the latest FSL USB stack has become part of KSDK , so it is recommended customer design USB application based on KSDK, while there are some old parts like K70, K60F and KL25 are still not supported in KSDK yet, so USB stack ver 4.1.1 is somewhat of help for those who still develop application based on those parts. USB stack ver 4.1.1 supports K70 instead of K60F, but since they are both Kinetis 120MHz parts, so the porting is very easy, here I provide a porting guide for this part. The porting is based on K70 USB examples, either Host or Device. 1. Replace the device header file. Use MK60F12.h instead, which may be extracted from KINETIS_120MHz_SC(Kinetis 120MHz bare metal sample code) , and put this header file in the folder of "C:\Freescale\Freescale USB Stack v4.1.1\Source\Host\source\bsp\P3" for Host or "C:\Freescale\Freescale USB Stack v4.1.1\Source\Device\app\common\kinetis" for device, and modify derivative.h as  below: 2. Macro definition changes in MK60F12.h, MCU_MK60F12 is defined instead of MCU_MK70F12, so in this step we will have to change some code snippet related with MCU_MK70F12. Firstly search MCU_MK70F12 in the project, for example ， in the Host demo USB_MSD project based on IAR, you may do that as below: and you may find some macro like "#ifdef MCU_MK70F12" or "#ifndef MCU_MK70F12", and change them as below: #ifdef MCU_MK70F12 ----> #if (defined MCU_MK60F12) || (defined MCU_MK70F12) #ifndef MCU_MK70F12 ----> #if (!defined MCU_MK60F12) && (!defined MCU_MK70F12) 3. IO driver modification. Since TWR-K70F120 has almost the same hardware as TWR-K60F120, there is no need to change the driver code after replacing the header file, except the serial port driver, referring to USB_MSD demo, the serial driver is in sci_kinetis.c, TWR-K70F120M uses PTE16 and PTE17(UART2) as the console, while TWR-K60F120M use PTE8 and PTE9(UART5) instead, so you have to change the driver as below to make printf work properly. void sci2_init(){ #if (defined MCU_MK60F12) || (defined MCU_MK70F12)     register uint_16 sbr, brfa;     uint_8 temp; #ifdef MCU_MK70F12     /* Enable the UART2_TXD function on PTD3 */     PORTE_PCR16 = PORT_PCR_MUX(0x3); // UART is alt3 function for this pin     /* Enable the UART2_RXD function on PTD2 */     PORTE_PCR17 = PORT_PCR_MUX(0x3); // UART is alt3 function for this pin     /* Enable the clock  */     SIM_SCGC4 |= SIM_SCGC4_UART2_MASK;     /* Make sure that the transmitter and receiver are disabled while we      * change settings.      */     UART_C2_REG(UART2_BASE_PTR) &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK);     /* Configure the UART for 8-bit mode, no parity */     UART_C1_REG(UART2_BASE_PTR) = 0;    /* We need all default settings, so entire register is cleared */     /* Calculate baud settings */     sbr = (uint_16)((SYSCLK*1000)/(UART_BAUDRATE * 16));     /* Save off the current value of the UARTx_BDH except for the SBR field */     temp = UART_BDH_REG(UART2_BASE_PTR) & ~(UART_BDH_SBR(0x1F));     UART_BDH_REG(UART2_BASE_PTR) = temp |  UART_BDH_SBR(((sbr & 0x1F00) >> 8));     UART_BDL_REG(UART2_BASE_PTR) = (uint_8)(sbr & UART_BDL_SBR_MASK);     /* Determine if a fractional divider is needed to get closer to the baud rate */     brfa = (((SYSCLK*32000)/(UART_BAUDRATE * 16)) - (sbr * 32));     /* Save off the current value of the UARTx_C4 register except for the BRFA field */     temp = UART_C4_REG(UART2_BASE_PTR) & ~(UART_C4_BRFA(0x1F));     UART_C4_REG(UART2_BASE_PTR) = temp |  UART_C4_BRFA(brfa);       /* Enable receiver and transmitter */     UART_C2_REG(UART2_BASE_PTR) |= (UART_C2_TE_MASK    | UART_C2_RE_MASK); #else   //MCU_MK60F12         /* Enable the UART2_TXD function on PTE8 */     PORTE_PCR8 = PORT_PCR_MUX(0x3); // UART is alt3 function for this pin     /* Enable the UART2_RXD function on PTE9 */     PORTE_PCR9 = PORT_PCR_MUX(0x3); // UART is alt3 function for this pin                /* Enable the clock  */     SIM_SCGC1 |= SIM_SCGC1_UART5_MASK;     /* Make sure that the transmitter and receiver are disabled while we      * change settings.      */     UART_C2_REG(UART5_BASE_PTR) &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK);     /* Configure the UART for 8-bit mode, no parity */     UART_C1_REG(UART5_BASE_PTR) = 0;    /* We need all default settings, so entire register is cleared */     /* Calculate baud settings */     sbr = (uint_16)((SYSCLK*1000)/(UART_BAUDRATE * 16));     /* Save off the current value of the UARTx_BDH except for the SBR field */     temp = UART_BDH_REG(UART5_BASE_PTR) & ~(UART_BDH_SBR(0x1F));     UART_BDH_REG(UART5_BASE_PTR) = temp |  UART_BDH_SBR(((sbr & 0x1F00) >> 8));     UART_BDL_REG(UART5_BASE_PTR) = (uint_8)(sbr & UART_BDL_SBR_MASK);     /* Determine if a fractional divider is needed to get closer to the baud rate */     brfa = (((SYSCLK*32000)/(UART_BAUDRATE * 16)) - (sbr * 32));     /* Save off the current value of the UARTx_C4 register except for the BRFA field */     temp = UART_C4_REG(UART5_BASE_PTR) & ~(UART_C4_BRFA(0x1F));     UART_C4_REG(UART5_BASE_PTR) = temp |  UART_C4_BRFA(brfa);        /* Enable receiver and transmitter */     UART_C2_REG(UART5_BASE_PTR) |= (UART_C2_TE_MASK    | UART_C2_RE_MASK); #endif        #endif } #ifdef __CC_ARM int sendchar (int ch) #else void TERMIO_PutChar (char ch) #endif { #if (!defined MCU_MK60F12) && (!defined MCU_MK70F12)     #if (defined MCU_MK20D5) || (defined MCU_MK20D7) || (defined MCU_MK40D7)         /* Wait until space is available in the FIFO */         while(!(UART1_S1 & UART_S1_TDRE_MASK)){};                /* Send the character */         UART1_D = (uint_8)ch;       #elif(defined MCU_MK21D5)         while(!(UART2_S1 & UART_S1_TDRE_MASK)){};                /* Send the character */         UART2_D = (uint_8)ch;       #elif(defined MCU_MKL25Z4) || (defined MCU_MKL46Z4)         /* Wait until space is available in the FIFO */         while(!(UART0_S1 & UART_S1_TDRE_MASK)){};        /* Send the character */        UART0_D = (uint_8)ch;       #else         /* Wait until space is available in the FIFO */         while(!(UART3_S1 & UART_S1_TDRE_MASK)){};                /* Send the character */         UART3_D = (uint_8)ch;     #endif   #else #ifdef MCU_MK70F12     /* Wait until space is available in the FIFO */     while(!(UART2_S1 & UART_S1_TDRE_MASK)){};     /* Send the character */     UART2_D = (uint_8)ch; #else      /* Wait until space is available in the FIFO */     while(!(UART5_S1 & UART_S1_TDRE_MASK)){};     /* Send the character */     UART5_D = (uint_8)ch; #endif #endif } 4. Set the correct device type in IDE settings. For IAR, change the device family in view of project options. Now, you can start to run the USB demos on TWR-K60F120M, please note the above steps is ok for USB device stack, but USB Host stack has some code issue , as mentioned in [USB stack ver 4.1.1] a code issue in msd_mfs_generic host demo , so please fix the issue before going further. Hope that helps, Best Regards, Kan

When using ADCs it is not enough to just configure the module, add a clock signal, apply the Nyquist criteria and hope for the best, because normally that is just not enough. Even if we use the best software configuration, sampling rate, conversion time, etc; we might end up with noisy conversions, and worst of all a low ENOB figure which sums up in a lousy, low resolution ADC application. To complement the software end you need to follow some basic hardware design rules, some of them might seem logical, other might even weird or excessive however they are the key to a successful conversion, I took the time to compile a short list of effective design best practices trying to cover the basics of ADC design. If you think I missed something feel free to comment and ask for more information. Ground Isolation Because ground is the power return for all digital circuits and analog circuits, one of the most basic design philosophies is to isolate digital and analog grounds. If the grounds are not isolated, the return from the analog circuitry will flow through the analog ground impedance and the digital ground current will flow through the analog ground, usually the digital ground current is typically much greater than the analog ground current.  As the frequency of digital circuits increases, the noise generated on the ground increases dramatically. CMOS logic families are of the saturating type; this means the logic transitions cause large transient currents on the power supply and ground. CMOS outputs connect the power to ground through a low impedance channel during the logic transitions. Digital logic waveforms are rectangular waves which imply many higher frequency harmonic components are induced by high speed transmission lines and clock signals.                              Figure 1: Typical mixed signal circuit grounding                              Figure 2: Isolated mixed signal circuit grounding Inductive decoupling Another potential problem is the coupling of signal from one circuit to another via mutual inductance and it does not matter if you think the signals are too weak to have a real effect, the amount of coupling will depend on the strength of the interference, the mutual inductance, the area enclosed by the signal loop (which is basically an antenna), and the frequency. It will also depend primarily on the physical proximity of the loops, as well as the permeability of the material. This inductive coupling is also known as crosstalk in data lines.                               Figure 3: Coupling induced noise It may seem logical to use a single trace as the return path for the two sources (dotted lines). However, this would cause the return currents for both signals to flow through the same impedance, in addition; it will maximize the area of the interference loops and increase the mutual inductance by moving the loops close together. This will increase the mutual noise inductance and the coupling between the circuits. Routing the traces in the manner shown below minimizes the area enclosed by the loops and separates the return paths, thus separating the circuits and, in turn, minimizing the mutual noise inductance.                               Figure 4: Inductance decoupling layout Power supply decoupling The idea after power decoupling is to create a low noise environment for the analog circuitry to operate. In any given circuit the power supply pin is really in series with the output, therefore, any high frequency energy on the power line will couple to the output directly, which makes it necessary to keep this high frequency energy from entering the analog circuitry. This is done by using a small capacitor to short the high frequency signals away from the chip to the circuit’s ground line. A disadvantage of high frequency decoupling is it makes a circuit more prone to low frequency noise however it is easily solved by adding a larger capacitor. Optimal power supply decoupling A large electrolytic capacitor (10 μF – 100 μF) no more than 2 in. away from the chip. A small capacitor (0.01 μF – 0.1 μF) as close to the power pins of the chip as possible. A small ferrite bead in series with the supply pin (Optional).                               Figure 5: Power supply decoupling layout Treat signal lines as transmission lines Although signal coupling can be minimized it cannot be avoided, the best approach to effectively counteract its effects on signal lines is to channel it into a conductor of our choice, in this case the circuit’s ground is the best choice to channel the effects of inductive coupling; we can accomplish this by routing ground lines along signal lines as close as manufacturing capabilities allow. An very effective way to accomplish this is routing signals in triplets, these works for both digital and analog signals.The advantages of doing so are an improved immunity not only to inductive coupling but also immunity to external noise. Optimal routing: Routing in “triplets” (S-G-S) provide good signal coupling with relatively low impact on routing density Ground trace needs to be connected to the ground pins on the source and destination devices for the signal traces Spacing should be as close as manufacturing will allow                               Figure 6: Transmission line routing Signal acquisition circuit To improve noise immunity an external RC acquisition circuit can be added to the ADC input, it consists of a resistor in series with the ADC input and a capacitor going from the input to the circuit’s ground as the figure below shows:                                                             Figure 7: ADC with an external acquisition circuit The external RC circuit values depend on the internal characteristics and configuration of the ADC you use, such as the availability of an internal gain amplifier or the ADC’s architecture; the equation and circuit shown here represents a simplified form of ADC used in Freescale devices. The equivalent sampling resistance RSH is represented by total serial resistance connected between sampling capacitance and analog input pin (sampling switch, multiplexor switches etc.). The sampling capacitance CSH is represented by total parallel capacitance. For example in a case of Freescale SAR ADC equivalent sampling capacitance contains bank of capacitances. The equation shown how to calculate the value of the input resistor based on the values of both the input and sample and hold circuit. It must be noted the mentioned figures could have an alternate designation in any given datasheet; the ones mentioned here are specific to Kinetis devices: TAQ=      Acquisition time (.5/ADC clock) CIN=       Input capacitance (33pF min) CSH=      Sample & Hold circuit capacitance ( CDAIN in datasheet) VIN=       Input voltage level VCSH0= Initial voltage across S&H circuit (0V) VSFR=    Full scale voltage (VDDA) N=           bit resolution Note:  Special care must be taken when performing the calculation since a deviation from the correct values will result in a significant conversion error due to signal distortion.

VREF module provide one input pin VREF, this pin can provide reference voltage for both external circuit but also for internal Sigma Delta ADCs, AFE and DAC.  Also it includes trim function in it. In this document, I would like to use my testing to do a linearity analysis. From figure1 and 2, you can find how to make VREF as reference voltage of different analog module. For example, you can find when S1 switches down, S0 closes and S2 select VREF, VREF will be voltage resource of SAR ADC.                                               Figure 1: Voltage reference function configuration                                   Figure 2: Voltage reference module diagramming I do a testing for VREF trim value linear analysis. The process is connecting the voltmeter to VREFH pin, then record measure result for each setting of VREF trim. There will be 64 records for every different setting. Testing chip is MKM34Z256. Please find my testing result from testing data table. From testing result, you can get the formula that y = kx + x0, where k is about 0.005 (5mV) and x0 is about 1.1881, x is trim value.  You can find there is only a little offset from offset curve.                                         Table 1: Trim voltage testing date                                                                 Figure 3: Offset curve

Recently I have received a report which said the customers met compiling issue when they imported the an2295sw CW project file and started to build it, the error message is like the following: When I looked into this issue, I found it was mainly due to some asm source file which was dedicated for Keil wrongly included in the CW project , so there would syntax error during compiling, and the linker issue was due to the path of linker file was wrongly defined, fix them would solve most of the compiling. 1. Fix source file issue: deselect the bootloader.asm file. 2. Fix linker file issue: redefine the correct path for linker file There is also an exception when you try to compile with the configuration for K70 120MHz part, it is due to some files can not be opened because the including path are missing: so besides the above changes, you have to add the paths below to solve this issue for Kinetis 120MHz part.    BTW, during debugging, I also found it is not convenient to switch between different configurations because users have to choose the proper header file for different platforms manually, so I add the following changes to support automatic switching platform according to the configuration but just with an exception for Kinetis K-1M 100MHz part, which still have to choose the proper platform manually. Customers who have downloaded an2295sw may directly replace the following files with that I attached in this document, which have included all above changes mentioned. an2295sw\src\Kinetis\CW_10.3\AN2295_Kinetis\.project an2295sw\src\Kinetis\CW_10.3\AN2295_Kinetis\.cproject an2295sw\src\Kinetis\CommonSource\bootloader_cfg.h Hope that helps, Kan

Although most of us have a basic understanding of how an ADC works and how to understand some of the basic figures that define an ADC performance, that is far from really understanding how to fully interpret and use the figures depicted in a datasheet ADC section. With all those numbers it is easy to get lost on which ones to look at when we want to know how it will react to conditions such as frequency, signal amplitude, temperature, etc; having such knowledge would allow us to better fit a specific ADC to your application and take full advantage of its features. Having this in mind I took the time to compile some information related to what the most common figures that describe an ADC performance depicted in a datasheet mean, most of the material can be found in any Analog to Digital Conversion theory book; as I mentioned before this is just a general compilation of knowledge I hope will help you better understand those specifications. It assumes those of us who use datasheets are somehow familiar with the basic working of ADCs, so I will spare the basic concepts. Now down to business, this is a extract of a typical ADC section from a microcontroller's datasheet: I am almost certain not a lot of people who use microcontrollers, and more specifically ADCs; have a clear idea of what Total Unadjusted Error, Integral Non-Linearity or Differential Non-Linearity describe in the behavior of an ADC. Even though I will try to describe in detail the most common parameters I might miss some others and there is the possibility some of the information might not be as accurate as I would like it to be, if any of you reading this brief document have specific questions regarding any parameter I describe or miss by all means comment. Common ADC electrical characteristics depicted in datasheets EQ          Quantization error      Since the analog input to an ADC can take any value, but the digital output is quantized, there may be a difference of up to ½ Less Significant Bit between the actual analog input and the exact value of the digital output. This is known as the quantization error or quantization uncertainty as shown below. In ac (sampling) applications this quantization error gives rise to quantization noise. SINAD, SNR and ENOB (Signal to Noise plus Distortion, SIgnal to Noise Ratio and Effective Number of Bits)      Signal-to-Noise-and Distortion (SINAD, or S/(N + D) is the ratio of the rms signal amplitude to the mean value of the root-sum square (rss) of all other spectral components, including harmonics, but excluding dc. SINAD is a good indication of the overall dynamic performance of an ADC      as a function of input frequency because it includes all components which make up noise (including thermal noise) and distortion. It is often plotted for various input amplitudes. SINAD is equal to THD + N if the bandwidth for the noise measurement is the same. SINAD is often converted      to effective-number-of-bits (ENOB) using the relationship for the theoretical SNR of an ideal N-bit ADC: SNR = 6.02N + 1.76 dB, the equation is solved for N, and the value of SINAD is substituted for SNR.      Effective number of bits (ENOB) is a measure of the dynamic performance of an analog to digital converter and its associated circuitry. The resolution of an ADC is specified by the number of bits used to represent the analog value, in principle giving 2 N signal levels for an N-bit signal. However, all real ADC circuits introduce noise and distortion. ENOB specifies the resolution of an ideal ADC circuit that would have the same resolution as the circuit under consideration. Often ENOB is calculated using the relationship for the theoretical SNR of an ideal N-bit ADC: SNR =      6.02N + 1.76 dB, the equation is solved for N, and the value of SINAD is substituted for SNR. SFDR      Spurious Free Dynamic Range     One of the most significant specification for an ADC used in a communications application is its spurious free dynamic range (SFDR). SFDR of an ADC is defined as the ratio of the rms signal amplitude to the rms value of the peak spurious spectral content measured over the bandwidth      of interest. SFDR is generally plotted as a function of signal amplitude and may be expressed relative to the signal amplitude (dBc) or the ADC full-scale (dBFS) as shown in Figure n. For a signal near full-scale, the peak spectral spur is generally determined by one of the first few harmonics of the fundamental. However, as the signal falls several dB below full-scale, other spurs generally occur which are not direct harmonics of the input signal. This is because of the differential nonlinearity of the ADC transfer function as discussed earlier. Therefore, SFDR      considers all sources of distortion, regardless of their origin. INL      Integral Non-Linearity     Integral nonlinearity (acronym INL) is the maximum deviation between the ideal output of an ADC and the actual output level (after offset and gain errors have been removed). The transfer function of an ADC should ideally be a line and the INL measurement depends on the ideal line selected. Two often used lines are the best fit line, which is the line that minimizes the INL result and the endpoint line which is a line that passes through the points on the transfer function corresponding to the lowest and highest input code. In all cases, the INL is the maximum distance between the ideal line selected and the actual transfer function. DNL        Differential Non-Linearity      Differnetial NonLinearity relates to the linearity of the code transitions of the converter. In the ideal case, a change of 1 LSB in digital code corresponds to a change of exactly 1 LSB of analog signal. In an ADC there should be exactly 1 LSB change of analog input to move from one           digital transition to the next. Differential linearity error is defined as the maximum amount of deviation of any quantum (or LSB change) in the entire transfer function from its ideal size of 1 LSB. Where the change in analog signal corresponding to 1 LSB digital change is more or less than 1 LSB, there is said to be a DNL error. The DNL error of a converter is normally defined as the maximum value of DNL to be found at any transition across the range of the converter. The following figure shows the non-ideal transfer functions for an ADC and shows the effects of the DNL error.      A common result of excess DNL in ADCs is missing codes resulting from DNL < –1 LSB. THD      Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the rms value of the fundamental signal to the mean value of the root-sum-square of its harmonics (generally, only the first 5 are significant). THD of an ADC is also generally specified with the input signal close to full-scale, the harmonics of the input signal can be distinguished from other distortion by their location in the frequency spectrum. The second and third harmonics are generally the only ones specified on a data sheet because they tend to be the largest. EFS     Full Scale Error Full-scale error can be defined as the difference between the actual value triggering the transition to full-scale and the ideal analog full-scale transition value. Full-scale error is equal to the offset error + gain error Offset error The transfer characteristics of both DACs and ADCs may be expressed as a straight line given by D = K + GA, where D is the digital code, A is the analog signal, and K and G are constants. In a unipolar converter, the ideal value of K is zero. The offset error is the amount by which the actual value of K differs from its ideal value. Gain error The gain error is the amount by which G differs from its ideal value, and is generally expressed as the percentage difference between the two, although it may be defined as the gain error contribution (in mV or LSB) to the total error at full-scale. TUE      Total Unadjusted Error This is the result of performing conversions without having calibrated the ADC, it is dominated by the uncalibrated gain and uncalibrated offset terms in the data sheet. Although most devices will be well within the data sheet limits, it should be noted that they are not centered around zero and full range of the incoming analog signal is not guaranteed. Therefore, an uncalibrated ADC will always show unknown levels of gain and offset error, thus reflecting the worst case of conversion error the module can provide.

    MMA9553L是飞思卡尔的一款计步传感器，本文就如何快速使用该传感器做一个简单介绍。    你可能还见到过MMA955xL， 它与MMA9553L是什么关系呢？简单的来说MMA955xL是一个统称，它包括MMA9550L、MMA9551L、MMA9553L和MMA9559L这几个具体型号，其实这四种传感器在硬件上都是一样的。其内部主要由ColdFire 内核、模拟前端、Flash、IIC和SPI接口等部分组成，原理框图如下图所示：    它们的不同之处在于内部的Firmware不同，Firmware在芯片出厂时就已经固化在芯片里面了，不同的Firmware对于不同的功能。这里介绍的MMA9553L主要就用作计步器功能。        MMA9553L和MCU之间可以通过IIC接口或者SPI接口通讯，所以使用MMA9553L的首要前提是把MCU的IIC或者SPI调通。接口调通之后就可以来操作此传感器了。这里以IIC为例来说明。附件为参考代码。 测试平台：IAR7.2 + FRDM_KL25Z+FRDM-FXS-MULTI FRDM-FXS-MULTI开发板上带有MMA9553L，将FRDM-FXS-MULTI开发板和FRDM_KL25Z连接在一起就可以使用了。     下面分析一下源代码：        首先是调用初始化函数pedometer_init()，此函数主要调用以下几个函数：      pedometer_write_config();       // config     pedometer_enable();         // enable pedometer     pedometer_int0_enable();    // enable INT_O pin     pedometer_active();         // active MMA9553 pedometer_wakeup();   // wakeup 在此重点分析前两个函数。第一个函数 pedometer_write_config()，该函数的具体实现如下： void pedometer_write_config(void) {     unsigned char Buf[]={0x15,0x20,0x00,0x10,                            0x0C,0xE0,                            0x13,0x20,                            0x00,0x96,                            0x60,0x50,                            0xAF,0x50,                            0x04,0x03,                            0x05,0x01,                            0x00,0x00};     dvMMA9553_Write(MMA9553_Slave_Addr, MMA9553_Sub_Addr, Buf, 20); } 此函数很简单，就是通过IIC给9553发送一条命令，命令的内容Buf数组中的20个字节    的数据。 dvMMA9553_Write()函数的第一个参数代表MMA9553L的地址，为0x4C。datasheet中有说明。 #define MMA9553_Slave_Addr  0x4C dvMMA9553_Write()函数的第二个参数代表寄存器地址，为0x00。 #define MMA9553_Sub_Addr    0x00 发送的这一串命令：0x15,0x20,0x00,0x10,0x0C,0xE0,0x13,0x20,0x00,0x96,0x60,0x50,0xAF,0x50,0x04,0x03,0x05,0x01,0x00,0x00 具体是什么含义呢？ 0x15：表示Application ID，计步器的Application ID就是0x15 0x20：表示这条命令是Write Config command，即这条命令是用来写Configuration 寄存器的。 0x00：表示配置寄存器的偏移地址。 0x10：表示要写16字节的内容。 0x0C,0xE0,0x13,0x20,0x00,0x96,0x60,0x50,0xAF,0x50,0x04,0x03,0x05,0x01,0x00,0x00 这16字节就是写入配置寄存器中的具体内容。 配置寄存器共用8个，分别是Sleep Minimum register，Sleep Maximum register，Sleep Count Threshold register，Configuration/Step Length register，Height/Weight register，Filter register，Speed Period/Step Coalesce register，Activity Count Threshold register，每个寄存器为16 bit（2 字节），所以总共16字节。 第二个函数 pedometer_enable()，该函数的具体实现如下： void pedometer_enable(void) {     unsigned char Buf[]={0x17,0x20,0x05,0x01,0x00};     dvMMA9553_Write(MMA9553_Slave_Addr, MMA9553_Sub_Addr, Buf, 5); } 这次写入的命令是0x17,0x20,0x05,0x01,0x00 0x17：表示Application ID 0x20：表示这条命令是Write Config command 0x05,0x01,0x00 这三个表示在偏移地址0x5处，写入一个字节的数据0x00 其他几个函数也类似，都是写入一条命令，对某种Application的配置寄存进行设置。 初始化完了，现在就可以读取步数了。 通过调用pedometer_main() 函数就可以读取到步数。 该函数的实现如下： void pedometer_main(void) {     unsigned char Buf[20];     pedometer_cmd_readstatus(); // read  status      while(1)         {            dvMMA9553_Read(MMA9553_Slave_Addr, MMA9553_Sub_Addr, Buf, 2);            if(Buf[1]==0x80)            {               dvMMA9553_Read(MMA9553_Slave_Addr, MMA9553_Sub_Addr, Buf, 16);               break;             }         }         m_status.StepCount = Buf[6] * 256 + Buf[7];         m_status.Distance  = Buf[8] * 256 + Buf[9];         m_status.Calories  = Buf[12] * 256 + Buf[13]; } 主要调用了两个函数，一是pedometer_cmd_readstatus()，这个函数的实现如下： void pedometer_cmd_readstatus(void) {     unsigned char Buf[]={0x15,0x30,0x00,0x0C};     dvMMA9553_Write(MMA9553_Slave_Addr, MMA9553_Sub_Addr, Buf, 4 ); } 它是发送了0x15,0x30,0x00,0x0C这条命令 0x15：表示Application ID 0x30：表示Read Status command 0x00：表示偏移地址 0x0C：表示需要读的字节数为12 之后调用dvMMA9553_Read()函数，通过IIC读取16字节的数据（4字节起始信息+12字节status register内容），读到的16字节数据如下： Step count register寄存器如下，通过其值可以算出步数来。    另外还可以读取三轴加速度的值，过程与读取步数是类似的，也是先写配置寄存器，然后再读取状态寄存器。   总的来说操作MMA955L的关键搞清楚有两个重要的寄存器：配置寄存器和状态寄存器。配置寄存器可读可写，状态寄存器只可读。 写配置寄存器，格式是： APP_ID+0x20+offset+number+number字节的内容 读配置寄存器，格式为： 先发送：APP_ID+0x10+offset+number， 再通过IIC读number+4字节的内容，前4字节为起始信息。 读状态寄存器,格式为： 先发送：APP_ID+0x30+offset+number，再通过IIC读number+4字节的内容，前4字节为起始信息。 读Command 回的内容如下：

Hello. I am trying to use a PIT interrupt. I had never used Kinetis so there are certain things which with I am not familiarized yet. once i have created de PE code, cleaned and then I build the proyect, the following error pops up 'undefined reference to int_disp'. What it is about? Where should I write my ISR fuction? Does the ISR pit function has to have an specific name so as to be recognised by PIT.c?

This document was created in collaboration with Dragos Musoiu Trying to debug a hard fault on MKW24D512, ARM Cortex M4 based microcontroller, we did not find too much documentation on working with IMPRECISE hard faults.  We started our investigation from the post of Erich Styger Debugging Hard Faults on ARM Cortex-M. Based on this, we used Erich’s code to find the hard fault source, but it was impossible to find the instruction that caused the hard fault, because the executed instructions around the saved PC looked to be correct.  After, we checked the Hard Fault Status Register, from the System Control Block of the ARM Cortex M4 processor, we found the FORCED bit set. The ARM Cortex M4 documentation mentions that this bit indicates a forced hard fault, generated by escalation of a fault with configurable priority that cannot be handled, either because of priority or because it is disabled. When this bit is set to 1, the HardFault handler must read the other fault status registers to find the cause of the fault. We checked the other fault registers and we found, in the Configurable Fault Status Register (Bus Fault Status Register) from the System Control Block of the ARM Cortex M4 processor, the IMPRECISERR bit set. According to the ARM Cortex M4 documentation, if this bit is set a data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error. When the processor sets this bit to 1, it does not write a fault address to the BFAR. So that explained why we did not find the instruction that caused the hard fault using Erich’s indications. Also, this is an asynchronous fault. Therefore, if it is detected when the priority of the current process is higher than the BusFault priority, the BusFault becomes pending and becomes active only when the processor returns from all higher priority processes. The Cortex M4 processors have a write buffer feature that when a write is carried out to a bufferable memory region, the processor can proceed to the next instruction before the transfer is completed. This is great for performance, but can cause some complexity in debugging imprecise bus faults. Studying better the documentation, we found in the ARM Cortex M4 Auxiliary Control Register the DISDEFWBUF bit that when set to 1, disables write buffer use during default memory map accesses. This causes all BusFaults to be precise BusFaults but decreases performance because any store to memory must complete before the processor can execute the next instruction. In this way the processor will not continue executing the next instruction until the write operation is completed, and so enabling this bit and using Erich’s code the saved PC pointed to the instruction which caused the hard fault. In other case, if the Bus Fault is triggered by an instruction executed in an interrupt handler, with higher priority than the BusFault handler, setting the DISDEFWBUF can be useful in the debugging process because the BFAR register value remains valid in case of precise error.

Hi everyone,      I have got customer queries on unavailability of complementary mode PWM on KL25Z . So, I thought let me experiment something and post it onto the community.      The timer module on KL25 is TPM, not FTM!. There are 3 TPMs, TPM0 with 6 channels, TPM1 and TPM2 with 2 channels each. To generate a PWM signal, PWM component can be used. But the PWM bean doesnot provide option to generate complementary PWM. So, we need to configure different channels to get the complementary PWM. Again, there is a limitation for this. PWM component doesn't allow to generate initial polarity high. It says "the inherited component doesnot support this feature". But in run time can set or clear value on the PWM output pin using the SetValue() and ClrValue(). But again the inherited component"TimerUnit_LDD" doesn't support generating SetValue() and ClrValue().      So, I came to a conclusion 'not to use PWM component' and started using Init_TPM. Using this component, 2 channels are configured to have opposite polarity during initialization. They are configured to have the same period. Deadtime is also inserted by configuring different duty cycle on each channel. But methods are not available since the component only provides the initialization function which is good enough to start . Dynamically if dutycycle needs to be changed, methods have to be written explicitly     Project and oscilloscope captures are attached for reference. Hi Note that this is also supported in the uTasker project - see http://www.utasker.com/docs/uTasker/uTaskerHWTimers.PDF See specifically the final page - this is compatible for K and KL processors. Regards Mark http://www.utasker.com/kinetis.html This document was generated from the following discussion: Complementary PWM on FRDM-KL25Z using processor expert