Well. I would like to update for this issue.
As pgo said, 125KHz output is normal in new sample. I visited FSL Shanghai this morning and met Mr. Peng Wang in the office. Up to now, we can draw some conclusions and some speculates so far.
Fact 1: None of these boards can be connected to most of the debugger. (Speculate: They may have been damaged during POR, due to improper PCB layout, like long and narrow GND and long trace for reset which may introduces too much noise )
Fact 2: By adding more decoupling capacitor and replacing with a new KL25Z, it talks to JLINK (clone) in command mode (The new KL25Z can be detected with following info with a script from Mr. Wang:
Reset delay: 0 ms
Reset type RESETPIN: Resets core & peripherals using RESET pin.
Info: Found SWD-DP with ID 0x0BC11477
Info: FPUnit: 2 code (BP) slots and 0 literal slots
Info: Found Cortex-M0 r0p0, Little endian.
R0 = 00000023, R1 = 1FFFF410, R2 = 00000000, R3 = 00000000
R4 = 00000000, R5 = 00000000, R6 = 00000000, R7 = 00000000
R8 = 002001B0, R9 = 01489800, R10= 886084A0, R11= 04420B2C
R12= 840982DF, R13= FFFFFFFC, MSP= FFFFFFFC, PSP= 33012A20
R14(LR) = 00000A1D, R15(PC) = FFFFFFFE
XPSR 81000000, APSR 80000000, EPSR 01000000, IPSR 00000000
CFBP 00000000, CONTROL 00, FAULTMASK 00, BASEPRI 00, PRIMASK 00
Fact 3: However, it still can not talk to other debugger, including OpenSDA/CMSIS-DAP/CoLinkEx in SWD mode. As a cross checking, these debugger can program on board KL25Z of FRDM-KL25Z.
Fact 4: Although JLINK is the only one which can talk with KL25Z, but it refused to work because it is a clone.
We don't have enough time to arrange an inspection over the circuit with oscilloscope.
From viewpoint of schematics, it is working. But I have to revise the PCB with proper GND, shorter SWD connections.
However, I still have no idea how to debug it, or even download the code. Does JLINK commander support code programming?