Bursting supported on SEMC SRAM mode?

[mgarrison]

I have set up an RT1064 with SEMC bus connected to an FPGA using the SRAM mode. It is configured for 8-bit, ADMUX, ASYNC mode. When I turn on bursting (at any length) and perform a read, there is no difference in the bus signals. Four independent 8-bit transactions take place, including address phase.  Is this meant to work? It would be a nice way to increase performance since most of our data transfers are 512 bytes.

I did try SYNC mode and can see the difference there on the bus. Is it possible it's not supported in ASYNC mode?

Thanks.

[jingpan · Accepted solution]

Hi @mgarrison ,

ASYNC mode doesn't support burst.

Regards,

Jing

[mgarrison]

Thanks for the quick reply. Please update your documentation. There is no mention of that anywhere.