IMX6Q: Maximum IPU clock frequency

[kristofferglemb]

Hi there,

What is the maximum clock frequency for the IPU clock in IMX6Q? According to reference manual it is 264 MHz.

But in this answer: Q&A: What are the maximum HSP_CLK frequency values? it says "IPU1_HSP_CLK_ROOT is 270 MHz for DQ" but then writes max for DQ is 264 MHz.

The only way to achieve 264 MHz is to divide MMDC_CH0_AXI_CLK_ROOT. But I'm using LPDDR2 memory rated at 400 MHz and I'm running MMDC at 396 MHz so that is not an option.

270 MHz is achievable by selecting PLL3_PFD1 at 540 MHz and dividing by 2. I have tested this and it seems to work fine but it's unclear if this is a supported frequency.

If 270 MHz is not guaranteed to work, the clock options for the IPUs seems quite strange. I can only get 270 MHz, 198 MHz or lower if I'm running the memory at 400 MHz.

[art · Accepted solution]

Yes, it is possible to use 270MHz clock, derived from the PLL3 PFD1, as the IPU main clock.

Have a great day,
Artur

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[kristofferglemb]

That's great, but it really begs the question why the reference manual and QA claims 264 MHz?