where is ssi's sys clock from?

[剑明廖]

In this figure we can see that ssi's bit clock comes from ssi's sys clock,but where is ssi's sys clock from?

What is the relationship between ssi's sys clock and ssi_clk_root?

We can found the ssi_clk_root in the following figure.(ssi1_clk_root、ssi2_clk_root、ssi3_clk_root).

[art]

Actually, the SSI sys clock and ssix_clk_root are the different wordings for the same thing. This sys clock comes from the clock controller module, it is ssi1_clk_root for the SSI1 module, ssi2_clk_root for the SSI2 module and ssi3_clk_root for the SSI3 module.

Have a great day,
Artur

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[剑明廖]

Thank you for your answer,it is helpful to me.
But I have some other problem,can you help me ?

I configure ssi1 as network mode,bit  clock and frame sync generated internally,and route ssi1 to AUD3.

But the bit clock and frame clock don't generate on AUD3!!! Why?

I output source of SSI1_CLK_ROOT on CLKO2 pin and sure it has started. The bit TXDIR also set 1 to output the clock.And the audmux configure as:

port 3 ptcr = 0x84000800

port 3 pdcr = 0x0

port 1 ptcr = 0x800

port 1 pdcr = 0x4000

Where did I go wrong?

Best regards to you!