Hello,
There is a point I'm not sure about DDR3 routing. I'm following "Hardware Development Guide for
i.MX 6Quad" and this document says that the address signals must match 25 mils. When calculating the length of each signal, must we add the vias' length in the z direction to the total length? In my design, each address signal has the same number of vias but I drew some of the signals on different intermediate layers. When I add the depth of the via to the total length, there is a difference of about 150 mils. What do you suggest about it, what is the correct calculation in DDR3 routing?
Thanks, regards,
Celile
