The i.MX6UL/LL/LZ processor supports 2 USB OTG interfaces, USB OTG1 and USB OTG2, and each USB interface can be configured as a device, host or dual role mode. On the EVK board of i.MX6UL/LL, USB OTG1 is designed as dual role mode, and USB OTG2 is designed as HOST mode. This is sufficient for most customers.       However, in actual applications, we may need 2 USB HOSTs, and at the same time, we don’t want to use MicroUSB to USB TYPE-AF cable for Host-Device mode conversion. Therefore, the design of the USB circuit needs to meet such requirements: 1. USB device mode We need a USB device to download the linux image to the flash or SD card on the board. 2. 2 USB HOSTs When the system is working normally, we need the board to support 2 USB HOST. i.MX6UL/LL/LZ has only 2 USB ports. How to design to meet this requirement without increasing the USB HUB? The following scheme is used as a reference, and I hope it will be helpful to customers with similar requirement:        The logic and application description of this Diagram:: Default—device mode In the process of debugging the software, we need to use the USB OTG interface to download the linux image, so it must work in device mode. What we need to do is: (1). Pull USB OTG ID up to 3.3V (2). The USB OTG D+/D- signal is switched to the MicroUSB connector. (3). The USB OTG VBUS is provided with 5V power from the external PC USB HOST. Usage:        -Use a jumper for Pin 1 and Pin2, USB OTG ID pin will be pulled up to High.        With the operation, SEL pin of USB Muxer is High, and USB signals are switched to port B, and USB differential signals are connected to MicroUSB connector. At the same time, MIC2026-1YM output is disabled. The USB OTG1 VBUS pin of CPU is supplied by VBUS of MicroUSB connector, that is to say, supplied by PC USB HOST.        In this mode, software engineer can use it to download images to flash on board. Normal Work—Host mode After the software debugging is completed, two HOSTs are needed on the board. At this time, we need to switch the USB OTG1 from device to HOST mode. What we need to do is: (1). Pull USB OTG1 ID down to LOW (2). The USB OTG D+/D- signal is switched to the USB Type-AF connector. (3). Board should supply 5V power for USB device connected USB Type-AF connector. Usage:        -Use a jumper for Pin 2 and Pin3, USB OTG ID pin will be pulled down to Low.        With the operation, USB OTG1 ID pin is pulled down to Low, SEL pin of USB Muxer is also LOW, USB signals are switched to Port A, and connected to USB type-AF connector. At the same time, MIC2026-1YM is enabled , OUTA will output 5V , which will supply USB device connected on USB type-AF connector.   [Note] Users need to pay attention to. When using the jumper with PIN1/2/3, the board needs to be powered off. In other words, when switching between device and host, you need to switch off the power, then power on, and restart the board. The solution can also be used for i.MX processors with USB 2.0 interface.   NXP CAS team Wedong Sun 01/15/2021

Q: Q&A: Where to find IBIS Models on the web? A: In the first figure (FSL driving 100 ohm), the processor is DC coupled to a transmission line and terminated at the far end with a 100-ohm resistor. The results look pretty normal for this. In the other figure, the processor is dc coupled to a transmission line, then ac coupled to another transmission line segment (0.1u) with 50-ohm resistors to ground, and then drives the inputs of an HCSL clock buffer. The results are pretty un remarkable. The top red signal in the trace is one of the IMX6 clock outputs, the first green signal is the other clock output, and the last green signal (from top to bottom that is) is the differential signal seen by the clock buffer. The customer is concerned about the asymmetrical drive of the processor. It looks like LVDS clock outputs do not like to be AC coupled. This simulation resembles the way the clock is handled in the Smart Device schematics where the clock is AC coupled to the reference clock inputs on the PCIE connector. The ibis files were downloaded from the web (21x21_imx6q, consumer variant). So a few updates: I had the customer download the latest duallite IBIS models. Previously they were apparently using the quad/dual models. They are going to update HyperLynx and are going to run a simulation and let me know if they still see the same issue. He said he's using "linesim". Meanwhile he noticed a different problem with the duallite/solo IBIS models. Although the datasheet says LVDDR3 (1.35V) is supported, there is no model for DDR3_L either as input or output. The same model existed in the quad/dual models. Do you know why this option is not in the duallite IBIS models? Thanks! A ctm of mine would like to get the IBIS model with LVDDR3 support on the i.MX6 DL. For mx6-duallite IBIS models for DDR3L memory (1.35V). It'd be great if the models matched the quad version. Please find the new updated IBIS file in website. http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=i.MX6DL&nodeId=018rH3ZrDRB24A&fpsp=1&tab=Design_Tools_Tab

ccache is a C compiler cache. ccache can save a large amount of compilation time on recurring builds and builds restarted from a clean repository after make clean or git clean. It is well suited for e.g. u-boot and Linux compilation. Caching the host compiler Caching "native" builds is easily done by adding in the beginning of your $PATH a special directory, which contains links to ccache to override the usual compiler. On e.g. Debian this directory is readily available as /usr/lib/ccache, So you can do:   $ export PATH="/usr/lib/ccache:$PATH" Typical links found in this folder are:   c++ -> ../../bin/ccache   cc -> ../../bin/ccache   g++ -> ../../bin/ccache   gcc -> ../../bin/ccache etc... Caching the cross compiler Caching cross-compiled builds can be done in the same way as native builds, provided you create links of the form e.g. arm-linux-gnueabihf-gcc pointing to ccache. But there is an even more convenient way for those projects, which rely on a $CROSS_COMPILE environment variable (as is the case for e.g. u-boot and Linux). You can prefix the cross compiler with ccache there in e.g. the following way:   $ export CROSS_COMPILE="ccache arm-linux-gnueabihf-" Monitoring efficiency Now that your builds are cached, you might want to see how much is "spared" with this technique. ccache -s will tell you all sorts of statistics, such as:   cache directory                     /home/vstehle/.ccache   cache hit (direct)                 10852   cache hit (preprocessed)            3225   cache miss                         19000   called for link                    33267   called for preprocessing            9463   compile failed                         3   preprocessor error                     1   couldn't find the compiler           117   unsupported source language          921   unsupported compiler option         2167   no input file                      31681   files in cache                     51694   cache size                           1.3 Gbytes   max cache size                       4.0 Gbytes Here you see a somewhat typical 50%/50% hit/miss ratio. Enjoy! See Also ccache is usually supported natively by build systems, such as Buildroot or Yocto.

[中文翻译版] 见附件   原文链接： https://community.nxp.com/docs/DOC-343372 

The default FSL android BSP support 1 SD card slot. If customer need to support more sd slot in android.Please reference below steps. There are two steps need to set up. 1 device/fsl.git NOTE: 1  change the fstab. 2194000 is the address of usdhc2.             2  change the mount point in storage_list.xml diff --git a/sabresd_6dq/fstab.freescale b/sabresd_6dq/fstab.freescale index 7f23edb..1529a27 100644 --- a/sabresd_6dq/fstab.freescale +++ b/sabresd_6dq/fstab.freescale @@ -4,6 +4,7 @@ # specify MF_CHECK, and must come before any filesystems that do specify MF_CHECK /devices/soc0/soc.0/2100000.aips-bus/2198000.usdhc/mmc_host /mnt/media_rw/extsd vfat defaults voldmanaged=extsd:auto +/devices/soc0/soc.0/2100000.aips-bus/2194000.usdhc/mmc_host /mnt/media_rw/extsd_expand vfat defaults voldmanaged=extsd_expand:auto /devices/soc0/soc.0/2100000.aips-bus/2184000.usb/ci_hdrc.0  /mnt/media_rw/udisk vfat defaults voldmanaged=udisk:auto /dev/block/mmcblk3p5    /system      ext4    ro,barrier=1                                                                               wait,verify /dev/block/mmcblk3p4    /data        ext4    nosuid,nodev,nodiratime,noatime,nomblk_io_submit,noauto_da_alloc,errors=panic    wait,encryptable=/dev/block/mmcblk3p9 diff --git a/sabresd_6dq/overlay/frameworks/base/core/res/res/xml/storage_list.xml b/sabresd_6dq/overlay/frameworks/base/core/res/res/xml/storage_list.xml index 3639bdc..c3f5105 100644 --- a/sabresd_6dq/overlay/frameworks/base/core/res/res/xml/storage_list.xml +++ b/sabresd_6dq/overlay/frameworks/base/core/res/res/xml/storage_list.xml @@ -41,6 +41,10 @@               android:storageDescription="@string/storage_sd_card"               android:primary="false"               android:removable="true" /> +    <storage android:mountPoint="/storage/extsd_expand" +             android:storageDescription="@string/storage_sd_card" +             android:primary="false" +             android:removable="true" />      <storage android:mountPoint="/storage/udisk" 2  system/core.git NOTE: mkdir the mount point. build@scmbld2:~/maddev_lp5.1_consolidate_ga_10_30/system/core/rootdir$ git diff diff --git a/rootdir/init.rc b/rootdir/init.rc index 2211cc2..fac37c2 100644 --- a/rootdir/init.rc +++ b/rootdir/init.rc @@ -72,7 +72,9 @@ on init      mkdir /storage 0751 root sdcard_r      mkdir /mnt/media_rw/extsd 0755 system system +    mkdir /mnt/media_rw/extsd_expand 0755 system system      symlink /mnt/media_rw/extsd /storage/extsd +    symlink /mnt/media_rw/extsd_expand /storage/extsd_expand      mkdir /mnt/media_rw/udisk 0755 system system

[中文翻译版] 见附件   原文链接： https://community.nxp.com/docs/DOC-343344 

The document descript how to use the win32diskimager to create bootable sdcard.  How to resize sdcard mirror rootfs partition. Ex: fsl-image-validation-imx-imx6qpdlsolox.sdcard

SABRE-AI Development Platform bulletin on Touch Interrupt

[中文翻译版] 见附件   原文链接： i.MX Create Android SDCard Mirror 

Overview This document introduces how to setup i.MX6Dual/Quad and i.MX6Solo/DualLite Linux software for PCIe compliance test. Software Baselines i.MX6Dual/Quad: Linux BSP L2.6.35_1.0.0 i.MX6Solo/DualLite: Linux BSP L2.6.35_2.0.0 Software Changes To enable PCIe compliance test, PCIe software driver should not turn off PCIe clock and power in the tests. So the following changes are required: diff --git a/arch/arm/mach-mx6/pcie.c b/arch/arm/mach-mx6/pcie.c index 26d26f2..ad71085 100644 --- a/arch/arm/mach-mx6/pcie.c +++ b/arch/arm/mach-mx6/pcie.c @@ -801,6 +801,7 @@ static void __init add_pcie_port(void __iomem *base, void __iomem *dbi_base,      } else {          pr_info("IMX PCIe port: link down!\n"); +#if 0          /* Release the clocks, and disable the power */          pcie_clk = clk_get(NULL, "pcie_clk");          if (IS_ERR(pcie_clk)) @@ -820,6 +821,7 @@ static void __init add_pcie_port(void __iomem *base, void __iomem *dbi_base,          imx_pcie_clrset(IOMUXC_GPR1_TEST_POWERDOWN, 1 << 18,                  IOMUXC_GPR1); +#endif      } } Software Build Integrate the patch to the baseline code and recompile the kernel by following the instructions in Linux BSP user guide. Before recompile, please ensure the following configuration is enabled by selecting " System Type -> Freescale MXC Implementations -> PCI Express support" as "*": # MX6 Options: # CONFIG_IMX_PCIE=y

Starting from $52, the VAR-SOM-MX6 sets the bar for unparalleled design flexibility. The VAR-SOM-MX6 ensures scalable and simplified development, while also extending the product lifecycle. Thanks to four CPU core assembly options, customers can apply a single System on Module in a broad range of applications to achieve short time-to-market for their current innovations, while still accommodating potential R&D directions and marketing opportunities.     VAR-SOM-MX6 CPU: Freescale iMX6 Key features include: Freescale i.MX6 1.2GHz Quad / Dual / Single core Cortex-A9       2GB DDR3, 1GB SLC NAND Flash       Full HD 1080p video encoding/decoding capability       Vivante GPU providing 2D/3D acceleration       Simultaneous multiple display support       Gigabit Ethernet       TI WiLink™ 6.0 single-chip connectivity solution (Wi-Fi, Bluetooth®)       PCI-Express 2.0, S-ATA 3.0       Camera interface       USB 2.0: Host, OTG       Audio In/Out       Dual CAN Bus This versatile solution's -40 to 85°C temperature range and Dual CAN support is ideal for industrial applications, while 1080p video and graphics accelerations make it equally suitable for intensive multimedia applications. The impressive scalability of the VAR-SOM-MX6 satisfies the needs of the most demanding future application requirements whether faster processing power, enhanced algorithms or improved graphics and video performance to name just a few. The VAR-SOM-MX6 is an all-round solution with broad connectivity and sophisticated video and acceleration graphic capabilities, delivering a range of middle to high end assembly options all from the same product. For more details, please see VAR-SOM-MX6 CPU: Freescale iMX6

Most common issues with bringup and memory stability come down to memory/system setup during startup phase of i.MX device.   This Python script allows you to dump IVT/DCD tables and data from a i.MX binary (either generated as result of build process or a simple dump of SD/NOR/NAND... content) and analyze them in an easier way. Should work with i.MX 6 and i.MX53 binaries.   Parser for i.MX 6 will also try to print out register values it recognizes, and also parse specific register fields, helping to analyze the data faster. This can be extended if needed to other registers/values.   imxbin.py works with Python3.x and imxbin_2x.py with Python 2.x, so choose appropriate version.   Vladan

The i.MX6 DL/S L3.035_3.0.4 patch release is now available onwww.freescale.com ·         Files available # Name Description 1 L3.0.35_3.0.4_TEMP_PATCH This patch release is based on the i.MX 6DualLite/6Solo   Linux L3.0.35_3.0.0 release. The purpose of this patch release is fix the   miscalibration issue for the thermal sensor.

When you do long test (days or weeks) test on i.MX board and your test fails, you often wants to know what has happen with a JTAG probe. The problem is when you have 50 boards running in parallel, you don't have the budget to have 50 JTAG debug probe. If you do a "hot plug" of your JTAG probe, you have roughly one chance out 2 to reset your board... so you'll have to wait another couple of hour to resee the problem. Anyway to have a reliable JTAG plug with no reset, it is really simple... cut the RESET line on your cable! then you'll still be able to "attach" to your i.MX. On the MEK board, with a 10-pin JTAG connector, you have the cut the cable line 10 of the ribbon cable: On the cable, cut the reset line like this: With my Lauterbach JTAG  probe, when I do a "hot plug" I never have a reset of my i.MX. BR Vincent

Hi All, The i.MX6 Android R13.4-GA.03 patch release is now available on www.freescale.com ·         Files available # Name Description 1 IMX6_R13.4.03_ANDROID_PATCH This patch release is based on the i.MX 6 Android R13.4   release. The purpose of this patch release is correct the PFD workflow in   U-Boot, fix the miscalibration issue for the thermal sensor and corrects   ramp-up time of the internal LDOs

[中文翻译版] 见附件   原文链接： https://community.nxp.com/docs/DOC-343761 

[中文翻译版] 见附件   原文链接： https://community.nxp.com/docs/DOC-342833 

Question: Two boards are used and practically identical - one using the i.MX6Solo, the other is using a Dual. The sw settings in both cases are identical (except IOMUX addresses). On the i.MX6Solo they do not see any packet loss, on the i.MX6Dual they do. I recommended modifying the MTU size, but this also did not help. So here my two questions: 1)      is there still some hw difference between the Ethernet block on the Solo and the Dual/Quad? 2)      They run the AHB at only 100MHz. Could that be a problem? If not, why do the two chips behave so differently? To increase the AHB clock to 133 MHz.appears to solve the packet corruption issue. Is the 100 MHz AHB clock really the root cause. Answer: The DualLite/Solo and SoloLite contain different ethernet controllers. The DL/S has a 1000M controller which requires the AHB bus to be greater than 125MHz, while the SL has a 100M controller. As the question was about the Solo and the Dual and both use the Gigabit Ethernet block I assume that both will require a minimum AHB clock of 125MHz.