core 1 enable in s32k32x

[leo_Z]

Hello Everyone , I'm trying to initialize the core 1 in S32k324 by Core 0.

I attached my Code here.

I made CM7_1_Enable as 0 in core 0 , according to the start_up file of core 0, clock for core 1 is should not enable in there.

In core 0 main file I'm trying to enable the core clock for core 1 , but before that I'm checking the core1 clock status bit , it is already enabled.

Even I not initialized the CM7_1_Enable in path and symbol  core 1 clock is enabled.

#s32

But if try to connect with and flash the core 1 image with debugger with run on reset option, its stuck at wait for clock, then once i enabled the core 1 clock with core 0 , core 1 start running.

1. Why the core clock is enabled even CM7_1_Enable is 0?

2. I need to verify the core 1 clock is enabled by core 0, how can i do that?

void core_one_startup(void)

{

if((IP_MC_ME->PRTN0_CORE1_STAT&0x0001) != 1)

{

printf("Core one not enabled yet");

}

else

{

printf("Core one is enabled"); // Core 1 is always on?

}

IP_MC_ME->PRTN0_CORE1_PCONF |= MC_ME_PRTN0_CORE1_PCONF_CCE_MASK;

IP_MC_ME->PRTN0_CORE1_ADDR = (uint32)AVB_CODE;

IP_MC_ME->PRTN0_CORE1_PUPD |= MC_ME_PRTN0_CORE1_PUPD_CCUPD_MASK;

IP_MC_ME->CTL_KEY = MC_ME_CTL_KEY_KEY( 0x5AF0);

IP_MC_ME->CTL_KEY = MC_ME_CTL_KEY_KEY(~0x5AF0);

while (IP_MC_ME->PRTN0_CORE1_PUPD == MC_ME_PRTN0_CORE1_PUPD_CCUPD_MASK);

/*wait for core1 status*/

while((IP_MC_ME->PRTN0_CORE1_STAT&0x0001) != 1);

}

/*!

\brief The main function for the project.

\details The startup initialization sequence is the following:

* - startup asm routine

* - main()

*/

int main(void)

{

core_one_startup();

return exit_code;

}

S32K3 

[Julián_AragónM]

Hi @leo_Z,

1. CM7_1_ENABLE = 0 in the IVT/boot header doesn’t guarantee the clock is gated. That flag only controls whether CM7_1 is released at boot given a start address:

.section boot_header" header","ax
.long SBAF_BOOT_MARKER /* IVT marker */
.long (CM7_0_ENABLE << CM7_0_ENABLE_SHIFT) | (CM7_1_ENABLE << CM7_1_ENABLE_SHIFT) /* Boot configuration word */
.long 0 /* Reserved */
.long CM7_0_VTOR_ADDR /* CM7_0 Start address */ 
.long 0 /* Reserved */
.long CM7_1_VTOR_ADDR /* CM7_1 Start address */
.long 0 /* Reserved */
.long XRDC_CONFIG_ADDR /* XRDC configuration pointer */
.long LF_CONFIG_ADDR /* Lifecycle configuration pointer */
.long 0 /* Reserved */

 If CM7_1_ENABLE = 1: CM7_1 is enabled during boot. Debugger can connect to CM7_1 at the beginning.

You should ensure that only the master core can initialize the clock for the MSCM module. So, check if CORE1 is defined in core1 project, and CORE0 in the core0 project.

2. Try comparing the bit instead of the whole register like so: 

while (IP_MC_ME->PRTN0_CORE1_PUPD & MC_ME_PRTN0_CORE1_PUPD_CCUPD_MASK) { }

Also, make sure the session uses a destructive reset before the test just in case the debugger is not clearing the registers upon reset.

I imagine you are using the S32K324 Multi-Core Example Projects from community as reference, correct?

Best regards,
Julián

[leo_Z]

Hi @Julián_AragónM 

Thank For reply.

1. I Make it CM7_1_Enable =0 , becoz i don't want to execute the following part in start up code

Becoz i want core 0 application needs to enable the core 1.

and core 0 is defined in core 0 project and core 1 is defined in core 1 project

Does the code which i posted is it enough to enable the core 1 clock?

2. And we are using S32k328(Used S32K324 only for testing), in this mcu remote core is core 1 right like not in S32k358(which is core 0 and core 2).

We are using MC_ME.PRTN0_CORE1_PCONF[CCE] to enable the core 1 clock, is it same for s32k328? 

Becoz in datasheet there is one more register mentioned for s32k328, I'm confused in here

3. Could u tell how can i make sure my debug section uses a destructive reset?

4. There is lot of project listed in S32k324 multicore Example folder which you posted, could u possible to tell me which project does have the details of enabling the remote core clocks?

[Julián_AragónM · Accepted solution]

Hi @leo_Z,

1. Yes, the code you posted should be enough to enable core1 clock for S32K324 and S32K328. Here a code snippet from the example code I've shared at the bottom of my reply.

/*******************************************************************************
 * start_core_cm7_2
 *******************************************************************************/
void start_core_cm7_2(void){

	IP_MC_ME->PRTN0_CORE4_ADDR = (uint32)0x00800000;
	IP_MC_ME->PRTN0_CORE4_PCONF = 0x00000001;
	IP_MC_ME->PRTN0_CORE4_PUPD = 0x00000001;
	IP_MC_ME->CTL_KEY = 0x5AF0U;
	IP_MC_ME->CTL_KEY = 0xA50FU;
	while (IP_MC_ME->PRTN0_CORE4_PUPD == 1) { };
	while ((IP_MC_ME->PRTN0_CORE4_STAT & MC_ME_PRTN0_CORE4_STAT_CCS_MASK) == 0) { };
}

In your case, PRTN0_CORE4 register is PRTN0_CORE1, since CM7_1 is used instead.

Just as a note, you can define which core's clock is gated after boot within the boot configuration word (chapter 32.5.1 from S32K3XX reference manual). If not configured, you can use the code described above to enable it instead.

2. Yes. S32K328 has CM7_0 & CM7_1 as S32K324:

3. You could try modifying PEmicro's script and such, but for testing purposes, I suggest simply power-cycling the device and connecting through "Attach to Running Target" debug config to see if clock from core 1 is enabled:

4. The S32K324 multicore examples simply shows how to build + debug multicore projects. For a simple project on enabling remote core clock, I think this community post is better suited: S32K358 Multicore Start CM7_2 from CM7_0 - NXP Community.

Best regards,
Julián