FS26 FAQ: SPI Protocol Configuration is not sync with current FS26 implementation

[cuongnguyenphu]

Document si849710-FS26 FAQ Frequently Asked Questions(1.0).pdf mentioned about SPI configuration as following:

However, in current implemented code it will get fail if setup SPI configuration like that:
[C:\EB\tresos29\..\..\NXP\S32K3_FS26_R21-11_2.0.0_CD01\eclipse\plugins\Sbc_fs26_TS_T40D34M20I0R0/generate_PB/src/CDD_Sbc_fs26_PBcfg.c (signed):25]:
"The selected SpiChannelRef must has SpiDataWidth equal to 8"

It needs to update the document FS26 FAQ again to sync-up with current implementation code

[cuongnguyenphu · Accepted solution]

Discussed internally  
FAQ will be updated later

[TomasVaverka]

Discussed internally with the author of the FS26 FAQ document.

The fact is that the FS26 uses a 32-bit SPI, with the following arrangement:

MOSI (Main Out, Secondary In) bits:
• Bit 31: Main or fail-safe registers selection
• Bit 30 to 25: Register address• Bit 24: Read/Write (For reading Bit 24 = 0; For writing Bit 24 = 1)
• Bit 23 to 8: Control bits
• Bit 7 to 0: Cyclic redundant check (CRC)

MISO (Main In, Secondary Out) bits:
• Bit 31-24: General device status
• Bits 23 to 8: Extended device status, or device internal control register content or device flags 
• Bit 7 to 0: Cyclic redundant check (CRC)

BRs, Tomas