CAN Multiframe

rak14 · ‎01-16-2024

Hi,

I'm using S32K148 Microcontroller. I've enabled the CAN (not CAN FD) able to send and receive 1 frame (8 bytes) properly.

The issue is when we try to receive CAN multiframe we are missing some frames. It is implemented for UDS.

The logic we implemented is shown below:

Gen_CAN0_write( ID , Buffer, 8); //Request frame
if ((IP_FLEXCAN0->IFLAG1 >> 4) & 1)
{
Gen_CAN0_read(buff); //Response frame
}
Gen_CAN0_write( 0x782 , fc , 8); //Flow control frame
if ((IP_FLEXCAN0->IFLAG1 >> 4) & 1)
{
Gen_CAN0_read(buff1); //Read remaining frame 1
}
if ((IP_FLEXCAN0->IFLAG1 >> 4) & 1)
{
Gen_CAN0_read(buff2); //Read remaining frame 2
}
if ((IP_FLEXCAN0->IFLAG1 >> 4) & 1)
{
Gen_CAN0_read(buff3); //Read remaining frame 3
}

Is this the correct way to implement the logic. Please suggest.

Thanks,

Rak

PetrS · ‎01-16-2024

Hi,

from this code it is hard to comment, if it will work or not. It is not clear what write/read functions do. It is not clear how many MBs are used for TX and RX operation. I can guess you have one TX MB and one RX MB. Then a logic for RX process is simple. The MB flag indicates message was successfully received into the RX MB and its content can be read. You should read it before new message will come and will be moved into this MB, if it is free to receive, means it is not locked. If you do not ensure that you may lost some messages.
I assume using while loop will work better, but depends on application

Gen_CAN0_write( ID , Buffer, 8); //Request frame
while (!((IP_FLEXCAN0->IFLAG1 >> 4) & 1)) {}; //wait till RX MB receive message, MB flag is set
Gen_CAN0_read(buff); // Read Response frame
Gen_CAN0_write( 0x782 , fc , 8); //Flow control frame
while (!((IP_FLEXCAN0->IFLAG1 >> 4) & 1)) {};
Gen_CAN0_read(buff1); //Read remaining frame 1
while (!((IP_FLEXCAN0->IFLAG1 >> 4) & 1)) {};
Gen_CAN0_read(buff2); //Read remaining frame 2
while (!((IP_FLEXCAN0->IFLAG1 >> 4) & 1)) {};
Gen_CAN0_read(buff3); //Read remaining frame 3

BR, Petr

rak14 · ‎01-16-2024

Hi @PetrS ,

Thanks for the quick response.

Replacing while in place of if condition didn't work.

Please find the code of init, read and write functions.

Is there any code for implementing UDS over CAN in S32K148?

void Gen_FLEXCAN0_init(void)

{

#define MSG_BUF_SIZE 4 /* Msg Buffer Size. (CAN 2.0AB: 2 hdr + 2 data= 4 words) */

uint32_t i=0;

IP_PCC->PCCn[PCC_FlexCAN0_INDEX] |= PCC_PCCn_CGC_MASK; /* CGC=1: enable clock to FlexCAN0 */

IP_FLEXCAN0->MCR |= FLEXCAN_MCR_MDIS_MASK; /* MDIS=1: Disable module before selecting clock */

IP_FLEXCAN0->CTRL1 &= ~FLEXCAN_CTRL1_CLKSRC_MASK; /* CLKsrc=0: Clock Source = SOSCDIV2 */

IP_FLEXCAN0->MCR &= ~FLEXCAN_MCR_MDIS_MASK; /* MDIS=0; Enable module config. (Sets FRZ, HALT) */

//CAN0->MCR |= CAN_MCR_FRZ_MASK | CAN_MCR_HALT_MASK;

while (!((IP_FLEXCAN0->MCR & FLEXCAN_MCR_FRZACK_MASK) >> FLEXCAN_MCR_FRZACK_SHIFT)) {}

/*!

* Good practice:

* ===================================================

* wait for FRZACK=1 on freeze mode entry/exit

*/

IP_FLEXCAN0->CTRL1 = 0

#if defined(S32K11x_SERIES)

|CAN_CTRL1_PRESDIV(4) /* PRESDIV=4: Sclock=PEclock/(PRESDIV+1) = 40MHz/5 = 8MHz */

#endif

|FLEXCAN_CTRL1_PSEG2(3) /* Configure for 500 KHz bit time */

|FLEXCAN_CTRL1_PSEG1(3) /* Time quanta freq = 16 time quanta x 500 KHz bit time= 8MHz */

|FLEXCAN_CTRL1_PROPSEG(6) /* PRESDIV+1 = Fclksrc/Ftq = 8 MHz/8 MHz = 1 */

|FLEXCAN_CTRL1_RJW(3) /* so PRESDIV = 0 */

|FLEXCAN_CTRL1_SMP(1);

//|CAN_CTRL1_ERRMSK(1) ; /* Enaable error interrupt mask in CTRL1 register */

/* PSEG2 = Phase_Seg2 - 1 = 4 - 1 = 3 */

/* PSEG1 = PSEG2 = 3 */

/* PROPSEG= Prop_Seg - 1 = 7 - 1 = 6 */

/* RJW: since Phase_Seg2 >=4, RJW+1=4 so RJW=3. */

/* SMP = 1: use 3 bits per CAN sample */

/* CLKsrc=0 (unchanged): Fcanclk= Fosc= 8 MHz */

for(i=0; i<128; i++ )

{ /* IP_FLEXCAN0: clear 32 msg bufs x 4 words/msg buf = 128 words */

IP_FLEXCAN0->RAMn[i] = 0; /* Clear msg buf word */

}

for(i=0; i<16; i++ )

{ /* In FRZ mode, init IP_FLEXCAN0 16 msg buf filters */

IP_FLEXCAN0->RXIMR[i] = 0xFFFFFFFF; /* Check all ID bits for incoming messages */

}

// IP_FLEXCAN0->RXMGMASK = 0x1FFFFFFF; /* Global acceptance mask: check all ID bits */

IP_FLEXCAN0->RXMGMASK = 0x00;

IP_FLEXCAN0->RAMn[ 4*MSG_BUF_SIZE + 0] = 0x04000000; /* Msg Buf 4, word 0: Enable for reception */

/* EDL,BRS,ESI=0: CANFD not used */

/* CODE=4: MB set to RX inactive */

/* IDE=0: Standard ID */

/* SRR, RTR, TIME STAMP = 0: not applicable */

/*0x04000000*/

#ifdef NODE_A /* Node A receives msg with std ID 0x511 */

//IP_FLEXCAN0->RAMn[ 4*MSG_BUF_SIZE + 1] = 0x14440000; /* Msg Buf 4, word 1: Standard ID = 0x111 */

for(i=4;i<7;i++)

{

IP_FLEXCAN0->RAMn[ i*MSG_BUF_SIZE + 0] = 0x04 << 24;

}

#else /* Node B to receive msg with std ID 0x555 */

IP_FLEXCAN0->RAMn[ 4*MSG_BUF_SIZE + 1] = 0x15540000; /* Msg Buf 4, word 1: Standard ID = 0x555 */

#endif

/* PRIO = 0: CANFD not used */

IP_FLEXCAN0->MCR = 0x0000041F; /* Negate FlexCAN 1 halt state for 32 MBs */

while ((IP_FLEXCAN0->MCR && FLEXCAN_MCR_FRZACK_MASK) >> FLEXCAN_MCR_FRZACK_SHIFT) {}

/* Good practice: wait for FRZACK to clear (not in freeze mode) */

while ((IP_FLEXCAN0->MCR && FLEXCAN_MCR_NOTRDY_MASK) >> FLEXCAN_MCR_NOTRDY_SHIFT) {}

/* Good practice: wait for NOTRDY to clear (module ready) */

}

void Gen_FLEXCAN0_transmit_msg(void)

{

/*! Assumption:

* =================================

* Message buffer CODE is INACTIVE

*/

IP_FLEXCAN0->IFLAG1 = 0x00000001; /* Clear CAN 0 MB 0 flag without clearing others*/

IP_FLEXCAN0->RAMn[ 0*MSG_BUF_SIZE + 2] = 0xA5112233; /* MB0 word 2: data word 0 */

IP_FLEXCAN0->RAMn[ 0*MSG_BUF_SIZE + 3] = 0x44556677; /* MB0 word 3: data word 1 */

#ifdef NODE_A

IP_FLEXCAN0->RAMn[ 0*MSG_BUF_SIZE + 1] = 0x15540000; /* MB0 word 1: Tx msg with STD ID 0x555 */

#else

IP_FLEXCAN0->RAMn[ 0*MSG_BUF_SIZE + 1] = 0x14440000; /* MB0 word 1: Tx msg with STD ID 0x511 */

#endif

IP_FLEXCAN0->RAMn[ 0*MSG_BUF_SIZE + 0] = 0x0C400000 | 8 << FLEXCAN_WMBn_CS_DLC_SHIFT;

/* MB0 word 0: */

/* EDL,BRS,ESI=0: CANFD not used */

/* CODE=0xC: Activate msg buf to transmit */

/* IDE=0: Standard ID */

/* SRR=1 Tx frame (not req'd for std ID) */

/* RTR = 0: data, not remote tx request frame */

/* DLC = 8 bytes */

}

void Gen_FLEXCAN0_receive_msg(void)
{
/*! Receive msg from ID 0x556 using msg buffer 4
* =============================================
*/
uint8_t j;
uint32_t dummy;

RxCODE = (IP_FLEXCAN0->RAMn[ 4*MSG_BUF_SIZE + 0] & 0x07000000) >> 24; /* Read CODE field */
RxID = (IP_FLEXCAN0->RAMn[ 4*MSG_BUF_SIZE + 1] & FLEXCAN_WMBn_ID_ID_MASK) >> FLEXCAN_WMBn_ID_ID_SHIFT; /* Read ID */
RxLENGTH = (IP_FLEXCAN0->RAMn[ 4*MSG_BUF_SIZE + 0] & FLEXCAN_WMBn_CS_DLC_MASK) >> FLEXCAN_WMBn_CS_DLC_SHIFT; /* Read Message Length */

for (j=0; j<2; j++)
{ /* Read two words of data (8 bytes) */
RxDATA[j] = IP_FLEXCAN0->RAMn[ 4*MSG_BUF_SIZE + 2 + j];
}
RxTIMESTAMP = (IP_FLEXCAN0->RAMn[ 0*MSG_BUF_SIZE + 0] & 0x000FFFF);
dummy = IP_FLEXCAN0->TIMER; /* Read TIMER to unlock message buffers */
IP_FLEXCAN0->IFLAG1 = 0x00000010; /* Clear CAN 0 MB 4 flag without clearing others*/
}

Thanks

PetrS · ‎01-17-2024

Hi,

code looks normal, even if different functions are used in previous. I do not see cause why it does not work. An UDS demo is available in https://community.nxp.com/t5/S32K-Knowledge-Base/Unified-bootloader-Demo/ta-p/1423099

BR, Petr

rak14 · ‎01-18-2024

Hi @PetrS ,

The flexcan example is working fine but can I get the flexcan implementation with FreeRTOS as the available example is for baremetal which uses Osif.

PetrS · ‎01-19-2024

Hi,

I am not aware of such demo for S32K1. There is some for MPC5748G; https://community.nxp.com/t5/MPC5xxx-Knowledge-Base/Example-MPC5748G-FlexCAN-TX-RX-FreeRTOS-S32DS2-1...

BR, Petr