I recently tried to update U-boot on the PSC9131RDB and struggled for a while with the DIP switches on the board. I thought I'd write up a few pointers in case you try to attempt this yourself. DIP switches for the PSC9131RDB are described on Infocenter here: http://www.freescale.com/infocenter/topic/QORIQSDK/4227333.html A couple of points about the switches and jumpers worth considering: Make sure you read the solder mask on the board. The switches are numbered upside down from what you might expect. SW6[3:4] describe how the JTAG chain is setup on the board. The Starcore and Power cores can be chained in the same scan chain, or separated. If this is set to 11, a side effect is that the NAND flash is write protected. Input clock to the 9131 can either be 66Mhz or 100MHz. Images are built to a specific input clock, so make sure you are using an image for the clock your board is set to. Jumper J16 (near the SMA connectors) configured the input clock to the processor. If the jumper is on, the input clock is 66MHz. If it is off, it's 100MHz. The clock PLL ratios are multiples of the input clock. CCB clock = the input clock * a multipler. The core frequency = CCB clock * multiplier. All of the multiplers are located in the DIP switches and must be changed if you move from an image built for 66MHz to an image built for 100MHz. For example: For a 66MHz input clock, my CCB multiplier = 6:1, so my CCB clock = 400MHz. My core multiplier = 2:1, so my core frequency = 400MHz * 2 = 800MHz. If I were to just switch the input clock to 100MHz with these settings, I'd be running my CCB at 100*6 = 600MHz, and my core at 1.2GHz (which violates the processor's spec's!). Lastly, the board is built with both SPI and NAND flash. You can boot from either. It's either / or, and the images are built differently, so make sure you have the correct image for what you're attempting. If you happen to have an image burnt into both of the flash devices (SPI and NAND) you may select which to use at boot through SW4[ROM_LOC]. This can be set to 0b0110 for SPI, or 0b1001 for NAND.

Hello everyone， I have P1010 + FPGA control board. FPGA chip is mounted on the P1010's IFC interface. FPGA and P1010 is isolated by isolate buffer chip. One Norflash chip is also mounted on the P1010's IFC interface too. The file system built on Norflash. The OS read files from file system at any time are correct. Unfortunately, Once the FPGA is running, The OS write file to the file system will cause file system failure. But if the FPGA stop running, the write operate there will be no errors. I use the test fpga code which just have 1 logic and have nothing input or output pin, all pin . O, Who encountered such a issues? How it happened?

I have the p2041rdb Borad. (P2041RDB-PB) I got the vxWorks BSP from the WindRiber site. I read a target.ref file. then compiled the bootrom and kernel. I can the Tffs, SATA, .. but I can't Pcie. shell log -> **************************************************************************************************************************************** >vxBusShow Registered Bus Types:   MII_Bus @ 0x002eb1ec   PCI_Bus @ 0x002eae5c   PLB_Bus @ 0x002eae78 Registered Device Drivers:   ppcIntCtlr at 0x002e92c4 on bus PLB_Bus, funcs @ 0x002e92b8   m85xxTimerDev at 0x002eada8 on bus PLB_Bus, funcs @ 0x002ead8c   fslSata at 0x002eb2f8 on bus PLB_Bus, funcs @ 0x002eb2e0   fslDma at 0x002e9f28 on bus PLB_Bus, funcs @ 0x002e9f1c   epic at 0x002ea0bc on bus PLB_Bus, funcs @ 0x002ea068   dtsec at 0x002eb0d0 on bus PLB_Bus, funcs @ 0x002eb000   ns16550 at 0x002ea4a8 on bus PLB_Bus, funcs @ 0x002ea3d8   ns16550 at 0x002ea460 on bus PCI_Bus, funcs @ 0x002ea3d8   dtsecMdio at 0x002eb2a0 on bus PLB_Bus, funcs @ 0x002eb274   genericPhy at 0x002eb234 on bus MII_Bus, funcs @ 0x002eb228   miiBus at 0x002eb1a4 on bus PCI_Bus, funcs @ 0x002eb148   miiBus at 0x002eb164 on bus PLB_Bus, funcs @ 0x002eb148   m85xxPci at 0x002e9e38 on bus PLB_Bus, funcs @ 0x002e9e2c   m85xxCCSR at 0x002ea134 on bus PLB_Bus, funcs @ 0x002ea128   QorIQFman at 0x002ea270 on bus PLB_Bus, funcs @ 0x002ea254   QorIQBman at 0x002ea214 on bus PLB_Bus, funcs @ 0x002ea1f8   fslGpio at 0x002ea1b8 on bus PLB_Bus, funcs @ 0x002ea19c   QorIQQman at 0x002ea350 on bus PLB_Bus, funcs @ 0x002ea32c   QorIQPciEx at 0x002e9edc on bus PLB_Bus, funcs @ 0x002e9e78   QorIQLaw at 0x002ea2ec on bus PLB_Bus, funcs @ 0x002ea2b0   plbCtlr at 0x002eaea0 on bus PLB_Bus, funcs @ 0x002eae94 Busses and Devices Present:   PLB_Bus @ 0x002fe368 with bridge @ 0x002eaee0     Device Instances:         ppcIntCtlr unit 0 on PLB_Bus @ 0x002ff328 with busInfo 0x00000000         epic unit 0 on PLB_Bus @ 0x002ff428 with busInfo 0x00000000         ns16550 unit 0 on PLB_Bus @ 0x002ff628 with busInfo 0x00000000         ns16550 unit 1 on PLB_Bus @ 0x002ff828 with busInfo 0x00000000         ns16550 unit 2 on PLB_Bus @ 0x002ffa28 with busInfo 0x00000000         ns16550 unit 3 on PLB_Bus @ 0x002ffc28 with busInfo 0x00000000         fslGpio unit 0 on PLB_Bus @ 0x002ffe28 with busInfo 0x00000000         QorIQLaw unit 0 on PLB_Bus @ 0x002fff28 with busInfo 0x0         QorIQBman unit 0 on PLB_Bus @ 0x00300028 with busInfo 0x00000000         QorIQQman unit 0 on PLB_Bus @ 0x00300128 with busInfo 0x00000000         QorIQFman unit 0 on PLB_Bus @ 0x00300228 with busInfo 0x00000000         QorIQPciEx unit 1 on PLB_Bus @ 0x0030d328 with busInfo 0x00000000         dtsec unit 0 on PLB_Bus @ 0x0030d628 with busInfo 0x0         dtsec unit 1 on PLB_Bus @ 0x0030d728 with busInfo 0x0         dtsec unit 2 on PLB_Bus @ 0x0030d828 with busInfo 0x0         dtsec unit 3 on PLB_Bus @ 0x0030d928 with busInfo 0x0         dtsec unit 4 on PLB_Bus @ 0x0030da28 with busInfo 0x0         dtsecMdio unit 0 on PLB_Bus @ 0x0030db28 with busInfo 0x00000000         m85xxTimerDev unit 0 on PLB_Bus @ 0x0030dc28 with busInfo 0x00000000         fslSata unit 0 on PLB_Bus @ 0x0030dd28 with busInfo 0x00000000         fslSata unit 1 on PLB_Bus @ 0x0030de28 with busInfo 0x00000000         fslDma unit 0 on PLB_Bus @ 0x0030df28 with busInfo 0x00000000         fslDma unit 1 on PLB_Bus @ 0x0030e028 with busInfo 0x00000000         miiBus unit 0 on PLB_Bus @ 0x0030e128 with busInfo 0x002fefa8         miiBus unit 1 on PLB_Bus @ 0x00312328 with busInfo 0x002fef68         miiBus unit 2 on PLB_Bus @ 0x00312528 with busInfo 0x002fefe8         miiBus unit 3 on PLB_Bus @ 0x00312728 with busInfo 0x002ff028         miiBus unit 4 on PLB_Bus @ 0x00312928 with busInfo 0x002ff068     Orphan Devices:   MII_Bus @ 0x002fefa8 with bridge @ 0x0030e128     Device Instances:         genericPhy unit 0 on MII_Bus @ 0x0030e228 with busInfo 0x00000000     Orphan Devices:   MII_Bus @ 0x002fef68 with bridge @ 0x00312328     Device Instances:         genericPhy unit 1 on MII_Bus @ 0x00312428 with busInfo 0x00000000     Orphan Devices:   MII_Bus @ 0x002fefe8 with bridge @ 0x00312528     Device Instances:         genericPhy unit 2 on MII_Bus @ 0x00312628 with busInfo 0x00000000     Orphan Devices:   MII_Bus @ 0x002ff028 with bridge @ 0x00312728     Device Instances:         genericPhy unit 3 on MII_Bus @ 0x00312828 with busInfo 0x00000000     Orphan Devices:   MII_Bus @ 0x002ff068 with bridge @ 0x00312928     Device Instances:         genericPhy unit 4 on MII_Bus @ 0x00312a28 with busInfo 0x00000000     Orphan Devices: value = 1 = 0x1 -> pciDeviceShow value = -1 = 0xffffffff **************************************************************************************************************************************** I used rcw file that rcw_5g_1500mhz.bin (RR_PH_0x19)

This document introduces how to implement Ethernet flow control in DPDK by setting BMAN hardware and software portal depletion entry and exit thresholds. Hardware and Software Portal Depletion Threshold Registers   BMAN Pool hardware Threshold configuration in DPDK.   Pause Quanta Configuration in DPDK Flow control configuration Implementation in DPDK  

1. Different connecting for USB Super-Speed signals. 2. Pin MUX configuration for USB1(USB 3.0) 3. Linux Kernel configuration 4. Device Tree updating 5. Verify on the target board.

T2080PCIe_RDB SPI reboot failure problem

T2080 rev1.1 has fixed the MEM_PLL_RAT issue. but, the set flow is different than T2080 rev1.0. The flow is in the attached doc.

CodeWarrior Development Suite for Networking Applications to support software development on QorIQ Layerscape devices.

The NCSW - NetComm Software - is a package to help speed development on Freescale PowerQUICC and QorIQ processor platforms. It contains NCDD - NetComm Device Drivers - and some other components. Here take P3041 I2C supported in version GA_4.7 as an example to analyze the NetComm Software structure and device driver usage. CW PA 10.3 is used to be compatible for the use case code.

This document describes how to setup the LS1046A RDB as a PCIe End Point(EP) to be link trained and enumerated by the host system. The LS1046A RDB in this scenario is essentially being used to emulate a PCIe Add-in Card in PCIe-EP mode. LS1046ARDB Modifications for PCIe-EP Environment setting up MSI interrupt testing

This is a procedure to enable QorIQ GPIOs in Linux Kernel 

Hypervisor Deployment The Freescale embedded hypervisor is a layer of software that enables the efficient and secure partitioning of a multicore system. A system's CPUs, memory, and I/O devices can be divided into groupings or partitions, as shown in the figure below. Each partition is capable of executing a guest operating system. Figure 1. Partitioning with the Hypervisor in a Multicore Environment Hypervisor DTB changes: The partitioning information is defined in hypervisor package file called hv.dts. By default, the hv.dts file has only 2 interfaces and a mac-less interface defined per partition.  For IPSec demo we need to place all the interfaces within the 1st partition and the attached file has the full source code details. To extract the HV DTB source code, use the bitbake command: bitbake -c patch hv-cfg Build the final binaries using the bitbake command: bitbake fsl-image-core The above command would compile all the binaries required (including hv-2p-lnx-lnx.dtb) Now, the kernel, hypervisor image, device tree, hypervisor device tree and ramdisk filesystem can be flashed onto the board. These steps should be done assuming the user already has switched to the alternate bank.             Step 1: Programming Kernel to Flash TFTP the kernel image to RAM, then copy it to the flash address 0xe8020000. Execute the following commands at the U-Boot prompt to program the kernel to flash: =>tftp 1000000 uImage-t1040rdb.bin =>erase e8020000 +$filesize =>cp.b 1000000 e8020000 $filesize Step 2: Programming Ramdisk Filesystem to Flash TFTP the ramdisk file system to RAM, then copy it to the flash at address 0xe9300000. Execute the following commands at U-Boot prompt to program the ramdisk to flash: =>tftp 1000000 fsl-image-core-t1040rdb.ext2.gz.u-boot =>erase e9300000 +$filesize =>cp.b 1000000 e9300000 $filesize Step 3: Programming Hypervisor Image to Flash TFTP the hypervisor images to RAM, then copy it to the flash at address 0xe8700000. Execute the following commands at U-Boot prompt to program the hypervisor image to flash: =>tftp 1000000 hv.uImage =>erase e8700000 +$filesize =>cp.b 1000000 e8700000 $filesize Step 4: Programming Kernel dtb to Flash TFTP the kernel dtb file to ram, then copy it to the flash at address 0xe8800000. Execute the following commands at U-Boot prompt to program the kernel dtb to flash: Target Deployment - for hv-2p mode deployment: =>tftp 1000000 uImage-t1040rdb.dtb =>erase e8800000 +$filesize =>cp.b 1000000 e8800000 $filesize Program "hv-2p-lnx-lnx.dtb" to 0xe8900000 =>tftp 1000000 hv-2p-lnx-lnx.dtb =>erase e8900000 +$filesize =>cp.b 1000000 e8900000 $filesize           Step 5: Booting Up the System As of now, all the DPAA devices on this platform are given to partition 1. The kernel can boot up automatically after the board is powered on with the correct U-Boot environment. The following command can also be used to boot up the board at U-Boot prompt: =>setenv bootargs config-addr=0xfe8900000 console=ttyS0,115200 =>setenv bootcmd 'bootm 0xfe8700000 - 0xfe8800000' =>saveenv =>boot Step 6: Setup IPSec demo as described in the following link IPSec demo on T1040RDB

This document describes rate limiting solution implementation with QoS features of SJA1105 switch to handle the congestion of competing traffic flows, including the software architecture on TSN platforms, ingress traffic policer, prioritizing configuration, Time-Aware Scheduler in 802.1Qbv engine through SJA1105 switch and using IEEE 1588(Precision Time Protocol) to synchronize the SJA1105 PTP clocks.       Software Solution Architecture on TSN Platform        Ingress Traffic Policer        Prioritizing Configuration        Time-Aware Scheduler         Using IEEE 1588 to Synchronize the SJA1105 PTP Clocks

We’re glad to announce the FSL Community BSP 1.7 (codename Dizzy); it has been a busy release cycle with some new boards support added. In total we now support 42 boards from several vendors. During the 1.7 release cycle, a new SoC family support (QorlQ Layerscape1) has been included and the application and graphical stack support (better Wayland, Qt5 and Chromium support to enumerate some) has been greatly extended. This all has been accomplished with way less changes on the core BSP layer (53% less commits) which enforces the compromise of FSL Community BSP with long term quality and support. Another worth citing news is regarding the release notes. It is available online and gives an overview of supported boards, available version for default and optional packages and known issues at time of the release. The release notes has been completely reworked and extended in this release. It now offers a PDF version (for viewing and printing) alongside with the regular online one.

This session will take an in-depth look at QorIQ Data Path Acceleration Architecture (DPAA) and how each component interact with each other and the e500mc core. Discussion will include FMAN, QMAN, BMAN, SEC4, PME, SRIO manager and RAID Engine.

NEXCOM 1U network security appliance the NSA 5640 is designed for advanced Unified Threat Management (UTM) solutions with multi-Gigabit throughput. Featuring the Freescale multicore QorIQ T4240 SoC and high-speed networking and interconnect interfaces, the NSA 5640 addresses the escalating cyber threats fueled by rising network communication, bandwidth-hungry activities and number and complexity of Internet-based attacks.

This document introduce OpenIL Baremetal framework architecture using NXP Layerscape platforms, describes how to run a sample baremetal project and inter-core Communication application development based on OpenIL Baremetal framework. Inter-core communication(ICC) application works on Linux core(master) and Baremetal core(slave), provides the data transfer between cores via SGI inter-core interrupt and share memory blocks. Baremetal Framework architecture for QorIQ Layerscape platforms. Running Baremetal Binary Inter-core communication(ICC) application Development Based on Baremetal Framework Running ICC demo application

The flow is on sector 3.4.20.10.4 in QorIQ-SDK-1_7-IC-RevA, but it is wrong. So, please follow the steps in the attachment.