T2080 rev1.1 has fixed the MEM_PLL_RAT issue. but, the set flow is different than T2080 rev1.0. The flow is in the attached doc.

This application note introduces how to install and use Yocto to customize and generate required images. QorIQ SDK 1.6 installation and build environment setting up procedures. Using script fsl-setup-poky to create a build project and explaining specific parameters related with local configuration file. Yocto Image types and generation, and how to modify variables in machine configuration file to generate required images. How to run specific bitbake tasks, and how to configure and rebuild u-boot and Linux Kernel. How to create customized rootfs image recipes to add and remove packages list, use ROOTFS_POSTPROCESS_COMMAND to modify RFS content before image generation. Using merge-files package to add users’ own files into root file system. Creating new package recipes in Yocto build environment.

CodeWarrior Development Suite for Networking Applications to support software development on QorIQ Layerscape devices.

The NCSW - NetComm Software - is a package to help speed development on Freescale PowerQUICC and QorIQ processor platforms. It contains NCDD - NetComm Device Drivers - and some other components. Here take P3041 I2C supported in version GA_4.7 as an example to analyze the NetComm Software structure and device driver usage. CW PA 10.3 is used to be compatible for the use case code.

This document describes how to setup the LS1046A RDB as a PCIe End Point(EP) to be link trained and enumerated by the host system. The LS1046A RDB in this scenario is essentially being used to emulate a PCIe Add-in Card in PCIe-EP mode. LS1046ARDB Modifications for PCIe-EP Environment setting up MSI interrupt testing

This is a procedure to enable QorIQ GPIOs in Linux Kernel 

Hypervisor Deployment The Freescale embedded hypervisor is a layer of software that enables the efficient and secure partitioning of a multicore system. A system's CPUs, memory, and I/O devices can be divided into groupings or partitions, as shown in the figure below. Each partition is capable of executing a guest operating system. Figure 1. Partitioning with the Hypervisor in a Multicore Environment Hypervisor DTB changes: The partitioning information is defined in hypervisor package file called hv.dts. By default, the hv.dts file has only 2 interfaces and a mac-less interface defined per partition.  For IPSec demo we need to place all the interfaces within the 1st partition and the attached file has the full source code details. To extract the HV DTB source code, use the bitbake command: bitbake -c patch hv-cfg Build the final binaries using the bitbake command: bitbake fsl-image-core The above command would compile all the binaries required (including hv-2p-lnx-lnx.dtb) Now, the kernel, hypervisor image, device tree, hypervisor device tree and ramdisk filesystem can be flashed onto the board. These steps should be done assuming the user already has switched to the alternate bank.             Step 1: Programming Kernel to Flash TFTP the kernel image to RAM, then copy it to the flash address 0xe8020000. Execute the following commands at the U-Boot prompt to program the kernel to flash: =>tftp 1000000 uImage-t1040rdb.bin =>erase e8020000 +$filesize =>cp.b 1000000 e8020000 $filesize Step 2: Programming Ramdisk Filesystem to Flash TFTP the ramdisk file system to RAM, then copy it to the flash at address 0xe9300000. Execute the following commands at U-Boot prompt to program the ramdisk to flash: =>tftp 1000000 fsl-image-core-t1040rdb.ext2.gz.u-boot =>erase e9300000 +$filesize =>cp.b 1000000 e9300000 $filesize Step 3: Programming Hypervisor Image to Flash TFTP the hypervisor images to RAM, then copy it to the flash at address 0xe8700000. Execute the following commands at U-Boot prompt to program the hypervisor image to flash: =>tftp 1000000 hv.uImage =>erase e8700000 +$filesize =>cp.b 1000000 e8700000 $filesize Step 4: Programming Kernel dtb to Flash TFTP the kernel dtb file to ram, then copy it to the flash at address 0xe8800000. Execute the following commands at U-Boot prompt to program the kernel dtb to flash: Target Deployment - for hv-2p mode deployment: =>tftp 1000000 uImage-t1040rdb.dtb =>erase e8800000 +$filesize =>cp.b 1000000 e8800000 $filesize Program "hv-2p-lnx-lnx.dtb" to 0xe8900000 =>tftp 1000000 hv-2p-lnx-lnx.dtb =>erase e8900000 +$filesize =>cp.b 1000000 e8900000 $filesize           Step 5: Booting Up the System As of now, all the DPAA devices on this platform are given to partition 1. The kernel can boot up automatically after the board is powered on with the correct U-Boot environment. The following command can also be used to boot up the board at U-Boot prompt: =>setenv bootargs config-addr=0xfe8900000 console=ttyS0,115200 =>setenv bootcmd 'bootm 0xfe8700000 - 0xfe8800000' =>saveenv =>boot Step 6: Setup IPSec demo as described in the following link IPSec demo on T1040RDB

DPDK is a user space packet processing framework. OVS-DPDK is a popular software switching package which uses DPDK as the underlying platform. 1. LSDK 1809 Images Deployment 2. Ovs-dpdk Basic Switching 3. Ovs-dpdk MPLS (MultiProtocol Label) Pop_mpls Example 4. DPDK PACKETGEN

Many of the QorIQ processors have CPC (L3 CoreNet platform cache), such as P2040, P3041, P4080, B4860 and T1040 etc. CPC is a CoreNet-compliant target device. It could also be configured as memory-mapped SRAM, or combination of cache and SRAM. Here describe how to configure CPC to be SRAM.

This document describes rate limiting solution implementation with QoS features of SJA1105 switch to handle the congestion of competing traffic flows, including the software architecture on TSN platforms, ingress traffic policer, prioritizing configuration, Time-Aware Scheduler in 802.1Qbv engine through SJA1105 switch and using IEEE 1588(Precision Time Protocol) to synchronize the SJA1105 PTP clocks.       Software Solution Architecture on TSN Platform        Ingress Traffic Policer        Prioritizing Configuration        Time-Aware Scheduler         Using IEEE 1588 to Synchronize the SJA1105 PTP Clocks

For QorIQ Processors you could find documents from official website: Submit Form And below document list in this place: SDK/DPAA/Networking: Using QMAN Dedicated and Pool Channels in USDPAA and Linux Kernel LS2085 NADK Based IPSEC Application Communicating with AIOP DPAA Ethernet Interfaces Shared-MAC between two Linux Partitions under Hypervisor(Topaz) IPv6+AES.docx T1040 L2Switch Software Support IPSec demo on T1040RDB hv.dts IPSec on Freescale Hypervisor (Topaz) and T1040 (T1042) Rate limiting in DPAA QorIQ QMan CEETM Implementation in USDPAA Read T2080 XFI link status Shared-MAC and MAC-less Implementation in DPAA Linux Kernel Driver P2020RDB IPV4 forwarding performance test.pdf Set up NAT on QorIQ RDB Set up VLAN on QorIQ RDB SDK/Virtualization: FTF-DES-F1254_QorIQ Device Virtualization.pdf Virtualization Solutions in Freescale Linux SDK(1)– Hypervisor(topaz) Tools/Build/Debug: FTF-DES-F1321-QorIQ-Debug.pptx AMF-DES-T1053 - Open Source Tools Development Tools for ARM® Architectures .pptx AMF-DES-T1052 - QorIQ DevTools for Layerscape Family Products Applications.pptx AMF-SNT-T1045-Freeescale-Solutions-targeting-SDN-NFV-markets-with-ARM64-processors.pptx Modify T2080 rev1.1 MEM_PLL_RAT w/ using QCVS4.1.1 Using external GNU toolchain with CodeWarrior for QorIQ LS series – ARMv7 ISA QorIQ SDK build for T4240QDS - Beginner's guide Introducing the Scenarios Tool QorIQ Linux SDK 1.6 Working With Yocto T4240QDS_Altivec_example_with_MEPL.zip Building uboot/kernel/test-application out of Yocto Changing RootFS in SDK 1.3.2 Adding a new Flash Device to Codewarrior 10.x Building SDK 1.3.2 Boot/Board: LS2085 u-boot Workflow T2080PCIeRDB_SPI_reboot failure.pdf How to Flash/Reflash U-Boot and Linux to a Freescale Digital Networking Board System Boot from SD/MMC Card with SDK 1.6 images Secure boot for Non-PBL Platform Booting from QSPI on LS102xA Firmware update for LS1-TWR Switches on PSC9131RDB Re-flashing the P3041DS Deploying SDK 1.3.2 Solutions: AMF-SNT-T1045-Freeescale-Solutions-targeting-SDN-NFV-markets-with-ARM64-processors.pptx NEXCOM Introduces Appliance Based on Freescale QorIQ T4240 SoC and Aims for Gbps UTM Throughput Others: T4240QDS_Altivec_example_with_MEPL.zip A quick demo setup to toggle hue bulb using LS1021A IoT host processor and MKW20 zigbee QorIQ_Linux_kernel_GPIO_enable.pdf Announcements I2C NCSW Use Case FTF-DES-F1253 Lunch and Learn: Expedite Your Product Development with Linux SDK Backport Technolog Processors/Cores: L1 D-Cache Flushing Using CPC as SRAM

We’re glad to announce the FSL Community BSP 1.7 (codename Dizzy); it has been a busy release cycle with some new boards support added. In total we now support 42 boards from several vendors. During the 1.7 release cycle, a new SoC family support (QorlQ Layerscape1) has been included and the application and graphical stack support (better Wayland, Qt5 and Chromium support to enumerate some) has been greatly extended. This all has been accomplished with way less changes on the core BSP layer (53% less commits) which enforces the compromise of FSL Community BSP with long term quality and support. Another worth citing news is regarding the release notes. It is available online and gives an overview of supported boards, available version for default and optional packages and known issues at time of the release. The release notes has been completely reworked and extended in this release. It now offers a PDF version (for viewing and printing) alongside with the regular online one.

This session will take an in-depth look at QorIQ Data Path Acceleration Architecture (DPAA) and how each component interact with each other and the e500mc core. Discussion will include FMAN, QMAN, BMAN, SEC4, PME, SRIO manager and RAID Engine.

NEXCOM 1U network security appliance the NSA 5640 is designed for advanced Unified Threat Management (UTM) solutions with multi-Gigabit throughput. Featuring the Freescale multicore QorIQ T4240 SoC and high-speed networking and interconnect interfaces, the NSA 5640 addresses the escalating cyber threats fueled by rising network communication, bandwidth-hungry activities and number and complexity of Internet-based attacks.

This document introduce OpenIL Baremetal framework architecture using NXP Layerscape platforms, describes how to run a sample baremetal project and inter-core Communication application development based on OpenIL Baremetal framework. Inter-core communication(ICC) application works on Linux core(master) and Baremetal core(slave), provides the data transfer between cores via SGI inter-core interrupt and share memory blocks. Baremetal Framework architecture for QorIQ Layerscape platforms. Running Baremetal Binary Inter-core communication(ICC) application Development Based on Baremetal Framework Running ICC demo application

The flow is on sector 3.4.20.10.4 in QorIQ-SDK-1_7-IC-RevA, but it is wrong. So, please follow the steps in the attachment.

The T1023WALN board supports AQR105 only. Adding this patch file for AQR106 support.

QorIQ Device Virtualization with KVM: Performance vs Flexibility