There is some misunderstanding for the reaction time and Trr. To make clear, I will describe the total process for a fault happen and Reset assertion:
1. Recognition time
When output voltage reach UV threshold, and the duration time of output<UV Threshold larger than 10uS(max value),UV event will be recognized. It is 234us for an overvoltage recognition.
2. Internal Processing Time
After an fault recognized, it will take some time for internal Processing, the longest time is about 80 μs for an overvoltage detection. All others are below 80 μs.
3. External indication time
External indication time to notify an observer about the failure external to the SBC. This time is 3.0 µs for RSTB, 22 μs for FS0B .
so,
It should be 10uS+80uS+3uS=93uS(max) from an undervoltage happen to RSTB asserted to Low;
it should be 234uS+80uS+3uS=317uS(max) from an overvoltage happen to RSTB asserted to Low;
