KEA128 UART Bootloader 你好，我在KEA128单片机开发遇到一个问题，这个问题通过Jlink烧写程序调试是完全没有问题的，但是当我通过bootloader下载该程序，出现主程序死机的情况。 当我使用以下该程序（设置占空比）时，通过bootloader下载之后，程序出现死机现象。当我把该函数的内容注释掉，则一切正常。这种情况Jlink烧写是完全没有问题的，这个问题让我无从下手，希望能得到帮助，告诉我应该往那个方向寻找答案。 void heater_output(uint32 duty) { if(heater_switch==on) { ftm_pwm_duty(ftm0,ftm_ch0,duty);//设置占空比 } else { heater_pwm_duty=0; ftm_pwm_duty(ftm0,ftm_ch0,0); } } 这是我的跳转程序 void bootup_application(uint32_t appEntry, uint32_t appStack) { static void (*jump_to_application)(void); static uint32_t stack_pointer; //shutdown_drivers(); jump_to_application = (void (*)(void))appEntry;//跳转APP入口地址 stack_pointer = appStack; //堆栈指针 // SCB->VTOR = appEntry; __set_MSP(appStack); //设置主程序堆栈指针 __set_PSP(appStack); //设置进程堆栈指针 jump_to_application(); //跳转 } Re: KEA128 UART Bootloader Hi, 建议您考虑S32K系列， 它是车规级芯片。 https://www.nxp.com/products/processors-and-microcontrollers/s32-automotive-platform/s32k-auto-general-purpose-mcus:S32K-MCUS 如果你老师进入hardFault, 请看看stack是否分配小了。 BR XiangJun Rong Re: KEA128 UART Bootloader 你好，谢谢您的回复，我通过不下载仿真调试发现总是进入HardFault_Handler函数，我觉得可能是调用层次比较深，然后再主循环里直接调用设置占空比的函数，结果没有出现卡死情况。请问这种情况在这款芯片常见吗，我的APP程序大概33K左右，从0x8000开始，如果我想在项目中选择性能更好的性价比的车规级芯片，能运行更多算法，我应该如何选择。 Re: KEA128 UART Bootloader Hi, 那你把appEntry加上1. BR XiangJun Rong Re: KEA128 UART Bootloader 你好，当我把这行代码放进去，出现一个错误，（jump_to_application =jump_to_application +1；）使用的是IAR软件编译器，报错信息为，Error[Pe852]: expression must be a pointer to a complete object type 。这个该如何解决呀？ Re: KEA128 UART Bootloader Hi, 请使用下列代码： //shutdown_drivers(); jump_to_application = (void (*)(void))appEntry;//跳转APP入口地址 jump_to_application =jump_to_application +1； stack_pointer = appStack; //堆栈指针 // SCB->VTOR = appEntry; __set_MSP(appStack); //设置主程序堆栈指针 __set_PSP(appStack); //设置进程堆栈指针 jump_to_application(); //跳转 因为是thumb指令集， 请试一下，看行不行 BR XiangJunRong

Control GPIO using libgpiod API Hello, I'm using IMX8ULP EVK9 board and i have onboard LED. I'm able to control LED using "gpioset -c /dev/gpiochip4 20=1" command. Now I'm trying to control LED using C code but on that time i'm getting "Request lines failed: Invalid argument" error. I'm using libgpiod 2.0. Following is my C code const char *chipname = "/dev/gpiochip4"; unsigned int line_num = 20; struct gpiod_chip *chip; struct gpiod_request_config *req_cfg; struct gpiod_line_config *line_cfg; struct gpiod_line_request *request; // Open the GPIO chip chip = gpiod_chip_open(chipname); if (!chip) { perror("Open chip failed"); return 1; } // Allocate and configure the request config req_cfg = gpiod_request_config_new(); gpiod_request_config_set_consumer(req_cfg, "led_control"); // Allocate line config line_cfg = gpiod_line_config_new(); // Request the line unsigned int offsets[] = {line_num}; request = gpiod_chip_request_lines(chip, req_cfg, line_cfg); if (!request) { perror("Request lines failed"); gpiod_chip_close(chip); return 1; } // Blink the LED for (int i = 0; i < 10; i++) { gpiod_line_request_set_value(request, line_num, GPIOD_LINE_VALUE_ACTIVE); // Turn on LED sleep(1); gpiod_line_request_set_value(request, line_num, GPIOD_LINE_VALUE_INACTIVE); // Turn off LED sleep(1); } // Clean up gpiod_line_request_release(request); gpiod_request_config_free(req_cfg); gpiod_line_config_free(line_cfg); // Free line_cfg gpiod_chip_close(chip); i.MX8ULP Re: Control GPIO using libgpiod API Hi @Zhiming_Liu ,                       I'm trying to read GPIO line values in imx91  using libgpiod by c application. But showing gpiod.h is not found. I installed libgpiod-tools and able to see gpiod.h in /usr/include/. But when I compile recipe it is showing error undefined reference to API used. It is linking error is there any way to read value of GPIO using C application. Thanks Re: Control GPIO using libgpiod API Hello, Please refer libgpiod 2.0 examples to modify your code. https://github.com/brgl/libgpiod/tree/v2.2.x/examples Best Regards, Zhiming

UART- S32K144 EVB I am currently working with the S32K144-EVB and attempting to perform data transmission and reception using UART. However, I am encountering difficulties with the UART configuration, especially since I am new to S32Design Studio. Initially, I tried the example UART project and successfully received the transmitted value. However, when I created a new project and configured the UART, I did not receive any data. Could you please provide guidance on how to properly configure UART in a new project. Re: UART- S32K144 EVB Hi @DIVYAJ1, Sorry for the misunderstanding, but are you using config tools or are you configuring the drivers yourself with registers? Following the thread, I was giving recommendations on how to configure the UART by using the GUI for the drivers, but the project you shared does not use these generated configurations. If you need to configure the example in bare metal, please follow AN5413: S32K1xx Series Cookbook, which includes an example for a simple UART 9600 baud transfer to a COM port on a PC in chapter 2.7. Best regards, Julián Re: UART- S32K144 EVB Here is the project file; Re: UART- S32K144 EVB Hi @DIVYAJ1, Could you share your code (main.c)? Maybe you are missing some steps initializing or using the functions. The basic uart project should look something like this: int main(void) { /* Initialize and configure clocks * - see clock manager component for details */ CLOCK_SYS_Init(g_clockManConfigsArr, CLOCK_MANAGER_CONFIG_CNT, g_clockManCallbacksArr, CLOCK_MANAGER_CALLBACK_CNT); CLOCK_SYS_UpdateConfiguration(0U, CLOCK_MANAGER_POLICY_AGREEMENT); /* Initialize pins * - See PinSettings component for more info */ PINS_DRV_Init(NUM_OF_CONFIGURED_PINS0, g_pin_mux_InitConfigArr0); /* Initialize for UART_PAL */ UART_Init(&uart_instance, UART_PAL_CONFIG); /* Send a welcome message */ UART_SendDataBlocking(&uart_instance, (uint8_t *)welcomeMsg, strlen(welcomeMsg), TIMEOUT); } Best regards, Julián Re: UART- S32K144 EVB Hi, Thankyou for replying. I imported the file you provided and successfully received transmitted data in the debug terminal. However, after following the UART configuration steps to create a new project, I am only seeing ‘NULL’ in the debug terminal instead of the expected transmitted data. Re: UART- S32K144 EVB Hi @DIVYAJ1, In order to use UART, you can simply add the UART component and configure the pins through Config Tools:         If you want to use interrupts or a callback for your reception and transmission, then the IntCtrl driver must also be added, but for a simple uart configuration that should be enough. I've attached a simple example which echoes the inputs through a serial terminal through UART1 (connected to the EVB's USB): Best regards, Julián

Issue on Tresos tool for I2c configuration - S32K344uC Hello all, I'm facing a issue when configure I2C on Tresos tool for S32K344 microcontroller. The current version that I'm using is: 4.0.0 HF02_D2407 (the latest version). I configured the I2c as Fast mode, but when I try to generate the code, I get this error: Can anyone help me with this problem? I'm not using the HighSpeedMode, so why there is this error? Thank you, MVR Re: Issue on Tresos tool for I2c configuration - S32K344uC Since you don't really need to use LPI2C_HIGHSPEED_MODE, you only need to modify the configuration so that I2cDataValidDelay meets the restrictions. Re: Issue on Tresos tool for I2c configuration - S32K344uC Hello @Robin_Shen , I did it, but I continue getting error: Where should I recalculate this baudarte? I tried in the "Master Configuration" tab.  Re: Issue on Tresos tool for I2c configuration - S32K344uC Hi Sorry for the inconvenience we bring you! The issue is that the I2c Baud Rate field from I2cHighSpeedModeConfiguration container needs to be updated after I2c Prescaler field is updated, To fix this field, I2c Operating Mode should be set on LPI2C_HIGHSPEED_MODE and recalculate the I2c Baud Rate from this container. After I2c Baud Rate field is recalculated, I2c Operating Mode field should be switch on the desired operating mode. Best Regards, Robin ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. -------------------------------------------------------------------------------

Does i.MX 6 support LPDDR2-1066 channels? We are using MCIMX6Q6AVT10AD. So far I got a question about LPDDR2 memory interface frequency.   According to IMX6DQRM.pdf,  "i.MX 6Dual/6Quad Applications Processor Reference Manual" (Rev. 6, 05/2020), Chapter "1.4 Features", the SoC supports 1/2 LPDDR2-1066 channels.   But according to another document, IMX6DQAEC.pdf, "i.MX 6Dual/6Quad Automotive and Infotainment..." , Data Sheet (Rev. 6, 11/2018), Chapter "1.2 Features", it only supports  1/2 LPDDR2-800 channels.   Could you clarify it, please? i.MX6 All i.MX6Quad Re: Does i.MX 6 support LPDDR2-1066 channels? Hello, That is a typo in documentation. i.MX6 supports 1/2 LPDDR2-800 channels. Best regards.

S32DS can't install freertos for S32K344 Hi everyone, What I saw a post just now is the same as my subject. when I install the offline installation package, I also found I can't install freertos, reporting one or more required tiems could not be found. image as follows: it show that I had installed the software., nstallation details as follows:  but I can't create new freertos project from k3 example, images as follows: how do I install successfully? Re: S32DS can't install freertos for S32K344 Thanks, it's done! Re: S32DS can't install freertos for S32K344 Hi @Hanoch  The FreeRTOS version 2.0.3 was developed for S32DS v3.4 using S32K3 Real-Time Drivers AUTOSAR 4.4 Version 2.0.3. According to the provided information, you are using S32DS v3.5 and RTD v3.0.0; the FreeRTOS version compatible with this SW is the 3.1.0 (SW32K3_FreeRTOS_10.5.1_3.1.0_D2304). B.R. VaneB

S32K1XX BOOTLODER Hello, team.     I'm currently developing the bootloader for S32K146, but I'm encountering some issues when writing data to the flash. I'd appreciate it if you could offer some advice. As shown in the image, this is an SREC file generated by S32DS IDE. However, I noticed a discontinuity in the addresses in this file: 0xA7260 ------- 0xA7270 ------- 0x7274. The remaining addresses are incremented by "0x10", but there is a gap between 0xA7270 and 0xA7274 where the increment is only 0x4. This issue prevents me from writing data to the flash because each flash write operation must occupy at least 8 bytes. However, there is only a 4-byte space provided here, making it impossible to write to the flash.    This is the problem I'm facing, and I hope you can suggest some solutions. Thank you. 回复： S32K1XX BOOTLODER Hi @shiqi_seventeen  Yes, that's correct. The minimum amount you can program is one phrase - 8 bytes: The best solution for bootloaders is to align the s-record file. Take a look at this thread for details: https://community.nxp.com/t5/S32-Design-Studio/Why-does-the-AN12218SW-bootloader-fails-to-parse-the-generated/td-p/1275665 Regards, Lukas 回复： S32K1XX BOOTLODER Could you please help me confirm whether the data written to the flash of S32K146 must be at least 8 bytes?

S32DS can't build freertos for S32K312 hi everyone When using 'SW32K3_FreeRTOS_10_5_1_UOS_3_1_0_DS_updatesite_D2304', generate routine for S32K312, compile fails.and where to download template software for S32K312EVK Re: S32DS can't build freertos for S32K312 Hi Select the "S32 Configuration Tool" menu then click on the desired configuration tool (Pins, Cocks, Peripherals etc...). Clicking on any one of those will generate all the components. Make the desired changes(if any) then click on the "S32 Configuration Tool->Update Code" button. Do you still encounter errors when you build after clicking Update Code? I refer to HOWTO: offline install S32K3 RTD 3.0.0 in S32DS v3.5 to install S32K3, and then install SW32K3_FreeRTOS_10_5_1_UOS_3_1_0_DS_updatesite_D2304.zip. No errors will be encountered when building. Sorry, I haven't seen the S32K312 examples since the version after S32K3 RTD 2.0.3. As you know, S32K3 has many derivatives, so to reduce effort, in the most recent RTD releases we only provide examples for K344, K358, and K396. Best Regards, Robin ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. -------------------------------------------------------------------------------

SPI communication with FXIO I encountered two problems in configuring FXIO for SPI communication with S32K312: 1. The baud rate configured by EB is 100KHz, but according to the measurement results, it is actually 200K. What's going on? 2. The configuration of the three parameters Cs2Cs, Clk2Cs and Cs2Clk in EB seems to be invalid for FXIO. What's going on? The following are screenshots of the configuration and test results. Re: SPI communication with FXIO Yes，clock config is Option-B.I have found the answer in the latest version of the update record. It should be that there is a problem with the clock source selected when calculating the baud rate.Thinks！ Re: SPI communication with FXIO Hello @WeiCh, 1. Is the system clock set precisely to one of the clock options listed in the RM? For example:  152. Option B - Reduced Speed mode (CORE_CLK @ 120 MHz) 2. This is a HW feature of the LPSPI module. Regards, Daniel

developemt software support with mc9s12zvc? I want to develope code on MC9S12ZVCA, and I have a debuger multilink universal. I wonder is there any other software tools besides codewarrior support with this chip? Re: developemt software support with mc9s12zvc? I choose generate S-Recode file now I can burn to S12ZVCA success. Re: developemt software support with mc9s12zvc? thanks for your reply, I used codewarrior just now. I can debug with the board by multilink universal, but I wonder how could generate the flash file that can be burn to S12ZVCA in codewarrior. Re: developemt software support with mc9s12zvc? Hi, We are only able to suggest our products or products officially mentioned on our pages. They can be found in the Design resources at the page... https://www.nxp.com/products/processors-and-microcontrollers/additional-mpu-mcus-architectures/s12-magniv-mixed-signal-mcus/s12zvm-mixed-signal-mcu-for-automotive-and-industrial-motor-control-applications:S12ZVM Best regards, Ladislav

Upgrading from MPC5777C to i.MX RT1170 Hello, After many happy years with the MPC55xx, 56xx and 57xx, I am looking for another MCU that I can use when the MPC5777C EOL approaches. For the moment, I do not intend to use the S32Kxx because I am not sure they outperform the MPC5777C when using their internal memories and it seems we would get much less performance from the QSPI interface than we currently get from the EBI. As I am looking for MCUs/MPUs with automotive qualification and automotive temperature range, the S32G family not an option for the moment. Thus, the automotive version of i.MX RT1170 looks a very interesting choice for us as it seems to combine a fast core with decent internal memory, automotive qualification and apparently good external interfaces. As I am contemplating acquiring a development board to start our evaluation, we have the following questions: - Is there any performance comparison between the i.MX family and the MPC? I suppose the core performance is much higher, but I would like to know if internal memory latencies are on par to make the M7 core run that much faster than a PowerPC one. - Is there any way for me to compare external RAM access latency between its SDRAM (assuming a 200MHz one) and sn asynchronous SRAM connected to the 66MHz EBI I have on the MPC5777C? - If I am to connect the processor to an FPGA (besides an external SDRAM), would it be more advisable to use the SEMC or the FlexSPI? While the reference manual mentions the FlexSPI as suitable for the task, we wonder if we could get better performance using a bus with a wider data path. - We took a quick look at the AN13264 and it looked like we would be able to use it as we use the MPC5777C (everything, starting from boot, running bare-metal and M4 core disabled as we do not intend to use a secondary core). Can we assume that booting the i.MX RT1170 is similar to booting the MPC5777C (in the sense that no RTOS is needed and all configurations can be done directly from the M7 core)? - Does it have a good integration with Green Hills tools (compiler, debugger and probe V4) like the MPC5xxx do? Thanks! Best regards, Ricardo Re: Upgrading from MPC5777C to i.MX RT1170 Unfortunately, we don’t have a direct comparison between the two families however on this application note you can get a reference on the memories performance on RT AN12437: i.MX RT Series Performance Optimization – Application Note (nxp.com) I will send you more detailed information for the specific RT1170. Both modules can connect to an FPGA, the decision on which to use will depend on your application requirements. RT1170 can run on the single M7 core as bare-metal, no need for OS to boot.  For the Green Hills integration, I suggest you contact Green Hills directly or your distributor for more detailed information on this. Best regards, Omar

fs23 Lin mode swith question Hello, We encountered a question while debugging the FS LIN functionality. Specifically, we found that in debug mode, we cannot set the LINTRCV_FS23_TRCVMODE_OFF mode using the LinTrcv_fs23_SetMode() function. The code snippet is as follows: Std_ReturnType LinTrcv_fs23_SetMode(uint8 u8LinNetwork, LinTrcv_fs23_TrcvModeType eOpMode) { uint16 u16RegData = 0U; Std_ReturnType eStatus; LinTrcv_fs23_TrcvModeType eNewHwOpMode = LINTRCV_FS23_TRCVMODE_INVALID; /* Read M_LIN register. */ eStatus = Sbc_fs23_ReadRegister(SBC_FS23_M_LIN_ADDR, &u16RegData); if ((Std_ReturnType)E_OK == eStatus) { /* Set new register value. */ u16RegData &= ~(SBC_FS23_M_LIN_MODE_MASK | SBC_FS23_M_LIN_SLOPE_MASK| SBC_FS23_M_LIN_FS_DIS_MASK); if(TRUE == xG_drivers[u8LinNetwork].bLinSlowSlope) { u16RegData |= SBC_FS23_M_LIN_SLOPE_SLOW; } if(FALSE == xG_drivers[u8LinNetwork].bLinFailsafeDisable) { u16RegData |= SBC_FS23_M_LIN_FS_DIS_KEEP; } u16RegData |= ((uint16)eOpMode << SBC_FS23_M_LIN_MODE_SHIFT); eStatus = Sbc_fs23_WriteRegister(SBC_FS23_M_LIN_ADDR, u16RegData); .... /*Check the real hardware state*/ eStatus |= LinTrcv_fs23_GetMode(u8LinNetwork, &eNewHwOpMode); if((eNewHwOpMode == eOpMode) && ((Std_ReturnType)E_OK == eStatus)) { eStatus = (Std_ReturnType)E_OK; } else { eStatus = (Std_ReturnType)E_NOT_OK; } } return eStatus; } The eOpMode is LINTRCV_FS23_TRCVMODE_OFF,  the eNewHwOpMode  is LINTRCV_FS23_TRCVMODE_NORMAL. The manual states that in debug mode, LIN defaults to active mode. Is this behavior normal? Thanks! Re: fs23 Lin mode swith question Hi @gumu , I got confirmation from hardware team that it's a normal behaviour. In debug mode, the transceiver mode is forced ACTIVE. So even if you try and change the LIN_MODE field to OFFLINE (OFF, 2b00) then the transceiver stays in active mode. Re: fs23 Lin mode swith question Hi, I have to check with hardware team. Can you please let me know what version of FS23 that you have? Or what is the part number? Re: fs23 Lin mode swith question Hi Quang (@quangvuanh), Could you please help with this question from Anhui Zhitu Technology China? Thanks & BRs, Tomas

より大きなシステムの一部としてのNNモデル - eIQ、Glowによるビルドプロセス こんにちは、eIQ + Glowなどのサードパーティベンダーの最適化により、複雑なシステムをAIモデルで強化することはどのように可能になるのか疑問に思います。私が理解した限りでは、これらは*推論*中にモデルとCPUの使用率を最適化するだけです。精度を達成するために必要な残りのモジュール、たとえば、データの前処理、特徴エンジニアリングは、グロービルドにこれらのステップを含める必要がある場合、手書きの方法でC言語で個別に記述する必要があります。では、これらの前処理ステップには最適化はありませんよね? さらに大局的に見ると、おそらくすでに独自のビルドプロセスを持っている複雑なシステムでは、Glow eccからHWへの最適化を活用できませんよね?「複雑な」システム全体に対して 1 つのビルド プロセスのみが存在する必要があります。

Why did the FreeRTOS task have problems when using one of the cores in the dual-core project for ENE Dear NXP community At present, MPC5748G is used for dual-core development, in which the core of Z4_0 is used for ENET development, and FreeRTOS is used. The core of Z4_1 is not used for now, and it may be used for USB development in the future. Now, the ENET1 project file used normally in the single-core project is transplanted to the Z4_0 core of the dual-core project. When scheduling FreeRTOS, it does not enter the first task normally. Why is this? Also, if you enter an interrupt like IVOR1_Handler, is there a way to lock down why you entered it? Thank you very much for your help in solving this problem H-chips These three screenshots are the result of three single steps. MPC5748G-GW-RDB  Re: Why did the FreeRTOS task have problems when using one of the cores in the dual-core project for Hi, Lukas Thanks for your help, I found that the problem appears in the address setting of different cores wrong, and there are some problems in the stack size setting. Regards, H-chips Re: Why did the FreeRTOS task have problems when using one of the cores in the dual-core project for Hi @H-chips  it looks like wrong address is used here: If you step the code in asm and if you check the core registers, you should see which address is used. It is also possible to check the core registers related to IVOR1 when the exception is triggered after this access: This can be found in section "5.7.2 Machine Check Interrupt (IVOR1)" in: https://www.nxp.com/webapp/Download?colCode=E200Z4RM Regards, Lukas Re: Why did the FreeRTOS task have problems when using one of the cores in the dual-core project for Thanks for the answer, but only one of my two cores uses FreeRTOS, so SMP is not involved Re: Why did the FreeRTOS task have problems when using one of the cores in the dual-core project for Hi, did you check if the version of FreeRTOS you use supports symmetric multiprocessing (SMP)? Symmetric Multiprocessing (SMP) with FreeRTOS - FreeRTOS™ There exist also quite good ports for other CPU and older FreeRTOS which you can use as draft, I know at least one for a dual-core from a different chip manufacturer. Best regards, Rainer

Where can I find it?S32_SDK_S32K1xx_RTM_4.0.3 Downloading S32_SDK_S32K1xx_RTM_4.0.3 in s32ds will give an error,If downloaded offline, S32_SDK_S32K1xx_RTM_4.0.3 cannot be found in the official website Re: Where can I find it?S32_SDK_S32K1xx_RTM_4.0.3 Some companies' IT restricts http access, so it is recommended to change Available S32DS Software Sites to https. Re: Where can I find it?S32_SDK_S32K1xx_RTM_4.0.3 So now I have returned s32ds 3.4, but can not find S32_SDK_S32K1xx_RTM_4.0.3 Re: Where can I find it?S32_SDK_S32K1xx_RTM_4.0.3 Do not use S32K1 SDK with S32DS v3.5. According to the currently available information, we don’t have any plan to integrate S32SDK S32K1XX 4.0.3 into S32DS 3.5 or above version. Re: Where can I find it?S32_SDK_S32K1xx_RTM_4.0.3 I want to open the project created by old version s32ds3.4+S32_SDK_S32K1xx_RTM_4.0.3, I tried s32ds 3.5 does not work with old version project Re: Where can I find it?S32_SDK_S32K1xx_RTM_4.0.3  Extensions and Updates install the S32 SDK for S32K1xx RTM 4.0.3 in S32DS 3.4.Prompts installation failure, like the first image，S32K1xx development package only S32K1 SDK 4.0.2，There is no S32 SDK for S32K1xx RTM 4.0.3 Re: Where can I find it?S32_SDK_S32K1xx_RTM_4.0.3 Hi You should be able to use Extensions and Updates install the S32 SDK for S32K1xx RTM 4.0.3 in S32DS 3.4. If the online installation fails, please install the S32K1xx development package first, and then install S32SDK S32K1XX RTM 4.0.3.  Sorry, there is no offline installation package for S32K1 SDK 4.0.3. By the way, it is recommended to install the latest S32K1 RTD 2.0.x by refer to HOWTO: offline install S32K1 RTD 2.0.0 in S32DS v3.5   Best Regards, Robin ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "ACCEPT AS SOLUTION" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. -------------------------------------------------------------------------------

K32W061/JN5189: Thread support for ‘Enhanced Frame Pending' (EFP)? Which version of Thread is supported by the current NXP SDK (v2.6.13)? I'm asking because we want to use the Enhanced Frame Pending (EFP) feature introduced in Thread v1.2. If already supported by the SDK, then how do we activate this feature? Re: K32W061/JN5189: Thread support for ‘Enhanced Frame Pending' (EFP)? Hello, Hope you are doing well. The OpenThread middleware is not included on the SDK. You need to get it from the GitHub - NXP/ot-nxp: OpenThread on NXP examples. Please check the information of each release directly: Releases · NXP/ot-nxp · GitHub Regards, Ricardo

S32G3 - HSE FW Install directly without IVT Hello, My goal is to be able to flash the HSE and then test the crypto services. I need to flash the HSE directly using the Lauterbach debugger without the need to flash/create an IVT. When i tried to directly flash the bin/hex file of the HSE, i find that the dedicated area for the HSE is not accessible (??s in T32 window) -> Address 0x22000000 Is there a way to enable the HSE memory area (maybe with a cmm script) so that i can flash it accordingly? Thank you, Re: S32G3 - HSE FW Install directly without IVT Hello @SahaarA,  I'm glad to know that the information answers your question. Thanks for letting me know and thanks for accepting my reply as a solution. Best regards, Alejandro Re: S32G3 - HSE FW Install directly without IVT Hello @alejandro_e ,  Yes actually that answers my question.  I was just wondering if there was a way to access the HSE directly, but now i just have to flash it with a blob image as mentioned in the documentation. Thank You,  Sahar Re: S32G3 - HSE FW Install directly without IVT Hello @SahaarA, It is not possible to access HSE memory, as you can see in the memory map attached to the S32G3 Reference manual: The steps I mentioned before will help you debugging your HSE application, but you cannot write the HSE FW directly like it is done in the S32K microcontrollers. Let me know if this information answers your questions. Re: S32G3 - HSE FW Install directly without IVT Hello @alejandro_e ,  From what i understand, we can boot the board either from RAM or from QSPI. Booting from QSPI needs a blob image, such that the HSE and Application would then be loaded to the RAM. The other way is flashing directly to the RAM using a debugger, which I'm currently doing.  For the Application, i can directly flash it with the debugger in the desired memory address. But for the HSE, the memory region is not accessible by the debugger. so i guess the HSE partition starting address 0x22000000 needs to be enabled somehow, like with a cmm script enabling the clock or something. I saw some other ways where the HSE can be flashed without the IVT but on other targets like the DCF options in S32K, so i'm wondering if there is a similar way but for S32G3 Thank You, Sahar. Re: S32G3 - HSE FW Install directly without IVT Hello @SahaarA, If I understood your problem correctly, you should be able to load and debug an application using the crypto services following the instructions in  AN14070 - How to Run HSE Demo Application, please check section How to load the HSE demo .elf to the SRAM. Let me know if this information solves your problem. Best regards, Alejandro

S32G3 - 无需 IVT 直接安装 HSE FW 您好，我的目标是能够刷新 HSE，然后测试加密服务。 我需要使用 Lauterbach 调试器直接刷新 HSE，而无需刷新/创建 IVT。 当我尝试直接刷新 HSE 的 bin/hex 文件时，我发现无法访问 HSE 的专用区域（在 T32 窗口中）-> 地址 0x22000000 有没有办法启用 HSE 内存区域（也许使用 cmm 脚本）以便我可以相应地刷新它？ 谢谢！

s32K118 Emulated EEPROM Testing with the debugger Hello, I am testing emulated EEPROM functionality on S32K118 eval board. While testing it with the on board debugger, every time I flash the new firmware I assum that it erases all flash sections so EEPROM Area is cleared as well. Is there way to keep Emulated EEPROM area while flashing the firmware (with debugger)? Re: s32K118 Emulated EEPROM Testing with the debugger Hi@zubizeratta you can refer to this post https://community.nxp.com/t5/S32-Design-Studio/How-to-disable-quot-erase-all-data-quot-option-before-flashing/td-p/915417

使用S32k146的定制硬件上的闪存问题 大家好， 我在定制的车辆控制单元上使用 S32k146 微机，编写了一个应用程序代码，我使用 S32Design Studio for ARM 软件上的 RAM 调试对其进行了调试，该应用程序代码是基于 S3k14x EAR SDK v0.8.6 的 Hello World 示例代码的默认设置构建的。我完成了代码编写，并使用 RAM 调试成功对其进行了测试/调试，但是当我想使用闪存进行调试时，出现了如下所示的错误。我用于调试的硬件是 Jlink。有人可以评估错误并帮助我如何才能成功使用 flash SEGGER J-Link GDB Server V7.94c Command Line Version JLinkARM.dll V7.94c (DLL compiled Jan 3 2024 15:20:10) Command line: -if swd -device S32K146 -endian little -speed 1000 -port 2331 -swoport 2332 -telnetport 2333 -vd -ir -localhostonly 1 -singlerun -strict -timeout 0 -nogui -----GDB Server start settings----- GDBInit file: none GDB Server Listening port: 2331 SWO raw output listening port: 2332 Terminal I/O port: 2333 Accept remote connection: localhost only Generate logfile: off Verify download: on Init regs on start: on Silent mode: off Single run mode: on Target connection timeout: 0 ms ------J-Link related settings------ J-Link Host interface: USB J-Link script: none J-Link settings file: none ------Target related settings------ Target device: S32K146 Target device parameters: none Target interface: SWD Target interface speed: 1000kHz Target endian: little Connecting to J-Link... J-Link is connected. Firmware: J-Link ARM V8 compiled Nov 28 2014 13:44:46 Hardware: V8.00 Feature(s): RDI,FlashDL,FlashBP,JFlash,GDB Checking target voltage... Target voltage: 3.29 V Listening on TCP/IP port 2331 Connecting to target... Initializing CPU registers...Connected to target Waiting for GDB connection...Connected to 127.0.0.1 GDB client (conn. 988) requested target.xml from GDB Server Reading common registers: Read register 'r0' (4 bytes) from hardware: 0x00000000 Read register 'r1' (4 bytes) from hardware: 0x00000000 Read register 'r2' (4 bytes) from hardware: 0x00000000 Read register 'r3' (4 bytes) from hardware: 0x00000000 Read register 'r4' (4 bytes) from hardware: 0x00000000 Read register 'r5' (4 bytes) from hardware: 0x00000000 Read register 'r6' (4 bytes) from hardware: 0x00000000 Read register 'r7' (4 bytes) from hardware: 0x00000000 Read register 'r8' (4 bytes) from hardware: 0x00000000 Read register 'r9' (4 bytes) from hardware: 0x00000000 Read register 'r10' (4 bytes) from hardware: 0x00000000 Read register 'r11' (4 bytes) from hardware: 0x00000000 Read register 'r12' (4 bytes) from hardware: 0x00000000 Read register 'sp' (4 bytes) from hardware: 0x00000000 Read register 'lr' (4 bytes) from hardware: 0x00000000 Read register 'pc' (4 bytes) from hardware: 0x00000000 Read register 'xpsr' (4 bytes) from hardware: 0x00000001 Read 4 bytes @ address 0x00000000 (Data = 0xFFFFFFFF) Received monitor command: speed 1000 Target interface speed set to 1000 kHz Received monitor command: clrbp Received monitor command: reset Resetting target Received monitor command: halt Halting target CPU... ...Target halted (PC = 0xFFFFFFFE) Received monitor command: regs R0 = 00000000, R1 = 00000000, R2 = 00000000, R3 = 00000000 R4 = 00000000, R5 = 00000000, R6 = 00000000, R7 = 00000000 R8 = 00000000, R9 = 00000000, R10= 00000000, R11= 00000000 R12= 00000000, R13= FFFFFFFC, MSP= FFFFFFFC, PSP= 00000000 R14(LR) = FFFFFFFF, R15(PC) = FFFFFFFE XPSR 01000000, APSR 00000000, EPSR 01000000, IPSR 00000000 CFBP 00000000, CONTROL 00, FAULTMASK 00, BASEPRI 00, PRIMASK 00 Security extension regs: MSP_S = 00000000, MSPLIM_S = 00000000 PSP_S = 00000000, PSPLIM_S = 00000000 MSP_NS = FFFFFFFC, MSPLIM_NS = 00000000 PSP_NS = 00000000, PSPLIM_NS = 00000000 CONTROL_S 00, FAULTMASK_S 00, BASEPRI_S 00, PRIMASK_S 00 CONTROL_NS 00, FAULTMASK_NS 00, BASEPRI_NS 00, PRIMASK_NS 00 Reading common registers: Read register 'r0' (4 bytes) from hardware: 0x00000000 Read register 'r1' (4 bytes) from hardware: 0x00000000 Read register 'r2' (4 bytes) from hardware: 0x00000000 Read register 'r3' (4 bytes) from hardware: 0x00000000 Read register 'r4' (4 bytes) from hardware: 0x00000000 Read register 'r5' (4 bytes) from hardware: 0x00000000 Read register 'r6' (4 bytes) from hardware: 0x00000000 Read register 'r7' (4 bytes) from hardware: 0x00000000 Read register 'r8' (4 bytes) from hardware: 0x00000000 Read register 'r9' (4 bytes) from hardware: 0x00000000 Read register 'r10' (4 bytes) from hardware: 0x00000000 Read register 'r11' (4 bytes) from hardware: 0x00000000 Read register 'r12' (4 bytes) from hardware: 0x00000000 Read register 'sp' (4 bytes) from hardware: 0xFCFFFFFF Read register 'lr' (4 bytes) from hardware: 0xFFFFFFFF Read register 'pc' (4 bytes) from hardware: 0xFEFFFFFF Read register 'xpsr' (4 bytes) from hardware: 0x00000001 WARNING: Failed to read memory @ address 0xFFFFFFFE Received monitor command: speed auto Select auto target interface speed (2000 kHz) Received monitor command: flash breakpoints 1 Flash breakpoints enabled Received monitor command: semihosting enable Semi-hosting enabled (Handle on breakpoint instruction hit) Received monitor command: semihosting IOClient 1 Semihosting I/O set to TELNET Client Received monitor command: SWO DisableTarget 0xFFFFFFFF SWO disabled successfully. Received monitor command: SWO EnableTarget 0 0 0x1 0 ERROR: Failed to restore original RAM content after CPU clock frequency detection! Failed to enable SWO. Could not measure target CPU frequency. WARNING: Failed to read memory @ address 0xFFFFFFFE Downloading 1024 bytes @ address 0x00000000 - Verified OK Downloading 16 bytes @ address 0x00000400 - Verified OK Downloading 4096 bytes @ address 0x00000410 - Verified OK Downloading 4096 bytes @ address 0x00001410 - Verified OK Downloading 4096 bytes @ address 0x00002410 - Verified OK Downloading 4096 bytes @ address 0x00003410 - Verified OK Downloading 2752 bytes @ address 0x00004410 - Verified OK Downloading 4 bytes @ address 0x00004ED0 - Verified OK Downloading 4 bytes @ address 0x00004ED4 - Verified OK Downloading 3452 bytes @ address 0x00004ED8 - Verified OK Writing register 'pc' = 0x0000046C ERROR: Failed to preserve target RAM @ 0x1FFF0000-0x2000EFFF. Failed to prepare for programming. Cannot read register 16 (XPSR) while CPU is running Cannot read register 20 (CFBP) while CPU is running Cannot read register 0 (R0) while CPU is running Cannot read register 1 (R1) while CPU is running Cannot read register 2 (R2) while CPU is running Cannot read register 3 (R3) while CPU is running Cannot read register 4 (R4) while CPU is running Cannot read register 5 (R5) while CPU is running Cannot read register 6 (R6) while CPU is running Cannot read register 7 (R7) while CPU is running Cannot read register 8 (R8) while CPU is running Cannot read register 9 (R9) while CPU is running Cannot read register 10 (R10) while CPU is running Cannot read register 11 (R11) while CPU is running Cannot read register 12 (R12) while CPU is running Cannot read register 14 (R14) while CPU is running Cannot read register 15 (R15) while CPU is running Cannot read register 17 (MSP) while CPU is running Cannot read register 18 (PSP) whi Read 4 bytes @ address 0x0000046C (Data = 0x00000000) Read 2 bytes @ address 0x00000854 (Data = 0x0000) WARNING: Failed to read memory @ address 0x00000854 Read 2 bytes @ address 0x000004F2 (Data = 0x0000) WARNING: Failed to read memory @ address 0x00000518 Read 2 bytes @ address 0x00000676 (Data = 0x0000) Read 2 bytes @ address 0x00000676 (Data = 0x0000) Read 2 bytes @ address 0x0000058A (Data = 0x0000) Read 2 bytes @ address 0x0000058A (Data = 0x0000) Received monitor command: clrbp Received monitor command: reset Resetting target Received monitor command: halt Halting target CPU... ...Target halted (PC = 0xFFFFFFFE) Read 2 bytes @ address 0x00000854 (Data = 0xFFFF) Read 2 bytes @ address 0x00000854 (Data = 0xFFFF) Read 2 bytes @ address 0x00000854 (Data = 0xFFFF) Received monitor command: regs R0 = 00000000, R1 = 00000000, R2 = 00000000, R3 = 00000000 R4 = 00000000, R5 = 00000000, R6 = 00000000, R7 = 00000000 R8 = 00000000, R9 = 00000000, R10= 00000000, R11= 00000000 R12= 00000000, R13= FFFFFFFC, MSP= FFFFFFFC, PSP= 00000000 R14(LR) = FFFFFFFF, R15(PC) = FFFFFFFE XPSR 01000000, APSR 00000000, EPSR 01000000, IPSR 00000000 CFBP 00000000, CONTROL 00, FAULTMASK 00, BASEPRI 00, PRIMASK 00 Security extension regs: MSP_S = 00000000, MSPLIM_S = 00000000 PSP_S = 00000000, PSPLIM_S = 00000000 MSP_NS = FFFFFFFC, MSPLIM_NS = 00000000 PSP_NS = 00000000, PSPLIM_NS = 00000000 CONTROL_S 00, FAULTMASK_S 00, BASEPRI_S 00, PRIMASK_S 00 CONTROL_NS 00, FAULTMASK_NS 00, BASEPRI_NS 00, PRIMASK_NS 00 Reading common registers: Read register 'r0' (4 bytes) from hardware: 0x00000000 Read register 'r1' (4 bytes) from hardware: 0x00000000 Read register 'r2' (4 bytes) from hardware: 0x00000000 Read register 'r3' (4 bytes) from hardware: 0x00000000 Read register 'r4' (4 bytes) from hardware: 0x00000000 Read register 'r5' (4 bytes) from hardware: 0x00000000 Read register 'r6' (4 bytes) from hardware: 0x00000000 Read register 'r7' (4 bytes) from hardware: 0x00000000 Read register 'r8' (4 bytes) from hardware: 0x00000000 Read register 'r9' (4 bytes) from hardware: 0x00000000 Read register 'r10' (4 bytes) from hardware: 0x00000000 Read register 'r11' (4 bytes) from hardware: 0x00000000 Read register 'r12' (4 bytes) from hardware: 0x00000000 Read register 'sp' (4 bytes) from hardware: 0xFCFFFFFF Read register 'lr' (4 bytes) from hardware: 0xFFFFFFFF Read register 'pc' (4 bytes) from hardware: 0xFEFFFFFF Read register 'xpsr' (4 bytes) from hardware: 0x00000001 WARNING: Failed to read memory @ address 0xFFFFFFFE Setting breakpoint @ address 0x00000854, Kind = 2, Type = THUMB, BPHandle = 0x0001 Starting target CPU... Debugger requested to halt target... Reading common registers: ERROR: Cannot read register 0 (R0) while CPU is running Read register 'r0' (4 bytes) from hardware: 0xEFBEADDE ERROR: Cannot read register 1 (R1) while CPU is running Read register 'r1' (4 bytes) from hardware: 0xEFBEADDE ERROR: Cannot read register 2 (R2) while CPU is running Read register 'r2' (4 bytes) from hardware: 0xEFBEADDE ERROR: Cannot read register 3 (R3) while CPU is running Read register 'r3' (4 bytes) from hardware: 0xEFBEADDE ERROR: Cannot read register 4 (R4) while CPU is running Read register 'r4' (4 bytes) from hardware: 0xEFBEADDE ERROR: Cannot read register 5 (R5) while CPU is running Read register 'r5' (4 bytes) from hardware: 0xEFBEADDE ERROR: Cannot read register 6 (R6) while CPU is running Read register 'r6' (4 bytes) from hardware: 0xEFBEADDE ERROR: Cannot read register 7 (R7) while CPU is running Read register 'r7' (4 bytes) from hardware: 0xEFBEADDE ERROR: Cannot read register 8 (R8) while CPU is running Read register 'r8' (4 bytes) from hardware: 0xEFBEADDE ERROR: Cannot read register 9 (R9) while CPU is running Read register 'r9' (4 bytes) from hardware: 0xEFBEADDE ERROR: Cannot read register 10 (R10) while CPU is running Read register 'r10' (4 bytes) from hardware: 0xEFBEADDE ERROR: Cannot read register 11 (R11) while CPU is running Read register 'r11' (4 bytes) from hardware: 0xEFBEADDE ERROR: Cannot read register 12 (R12) while CPU is running Read register 'r12' (4 bytes) from hardware: 0xEFBEADDE ERROR: Cannot read register 13 (R13) while CPU is running Read register 'sp' (4 bytes) from hardware: 0xEFBEADDE ERROR: Cannot read register 14 (R14) while CPU is running Read register 'lr' (4 bytes) from hardware: 0xEFBEADDE ERROR: Cannot read register 15 (R15) while CPU is running Read register 'pc' (4 bytes) from hardware: 0xEFBEADDE ERROR: Cannot read register 16 (XPSR) while CPU is running Read register 'xpsr' (4 bytes) from hardware: 0xEFBEADDE WARNING: Failed to read memory @ address 0xDEADBEEE Removing breakpoint @ address 0x00000854, Size = 2 Starting target CPU... 回复：使用S32k146的定制硬件上的闪存问题 就我而言，问题是由基于 S32K144 MCU 的定制硬件引起的。我们的设置中有一个 FS2303 SBC，它每 0.7 秒重置一次——更多详情请参阅我同事的帖子——S32K144 + FS2303 SBC 重置未发布 - NXP 社区。移除 SBC 并直接给 MCU 供电后，调试器工作正常。