S32K3 recovery issue when install HSE fw via MU We are currently developing secure boot functionality on the S32K344/S32K314 using HSE, based on the `S32K344_Advanced_SecureBoot` demo from the `S32K3_HSE_DemoExamples`. We have completed most of the feature development and can debug through successfully. In our configuration program, we calculate signatures for the BM, FBL, and APP using ED25519, write them to specified addresses in flash, and configure the SMR and CR for these three applications (BM as pre‑boot SMR, FBL and APP as post‑boot SMR). However, we have encountered some unclear issues and would appreciate your help. We are currently using the FULL_MEM form of HSE. Because we use the ED25519 algorithm to compute signatures for all application binaries, the configuration program takes a long time to execute. If a power failure occurs unexpectedly before the program finishes, we find that HSE enters an unrecoverable error state. Neither power‑cycling nor re‑flashing the firmware makes HSE respond to any host requests anymore. By checking the register at `0x4039C028` (HSE_CONFIG_GPR3), we see the value is `0xC0`; bit 0 has become `0`, which indicates that the HSE firmware may have been erased by SBAF. After power‑up, the MU0 FSR register is also `0`. We therefore tried to re‑install the HSE firmware. Since the normal IVT‑based installation method no longer works, we attempted installation via the MU interface. We simulated the steps described in the documentation, but found that after writing the SRAM address of the Pink Image into the MU Tx register (step 5), the value in HSE_CONFIG_GPR3 immediately changes from `0xC2` back to `0xC0` – i.e., bit 1 goes from `1` to `0` – and we never receive the expected success response `0xDACACADA`. We also referred to a similar issue on the forum:S32K3_The MU installation AB_SWAP process of HSE is incorrect. . We tried performing a functional reset immediately after step 5, but after the reset the new HSE firmware still cannot be installed. Could you please advise how to handle and recover from such a corrupted HSE state? Let me know if you need any adjustments. Re: S32K3 recovery issue when install HSE fw via MU Hi @chengjinwang  I’m unable to read the source files in the project you shared because they are encrypted. Please provide a version with plain (unencrypted) files. A few days ago, I created a Trace32 script to recover the HSE AB_SWAP firmware via the MU interface, so I quickly modified it for the FULL_MEM version. It works on my side - I receive the 0xDACACADA response. Do you wait approximately 1.5 seconds after writing the pink image location before performing any further actions? This delay is not explicitly mentioned in the FULL_MEM installation procedure, but it is required for the AB_SWAP version. This could be the issue. If you are using Trace32, let me know and I can share my script. Regards, Lukas Re: S32K3 recovery issue when install HSE fw via MU Here is the recovery program I'm using for HSE FW installation through MU; could you take a look and see what's wrong? Re: S32K3 recovery issue when install HSE fw via MU The attached file is the unencrypted version of the project I am currently using. For my tests, I am using the S32K344 chip, a PE debugger, and the S32DS project in the attachment. I tried waiting a few seconds after writing the Pink image to receive a successful response from SBAF, but that did not work either. Performing a functional reset directly also did not work. Could you please check if there are any issues with my MU installation routine in the attached project? Re: S32K3 recovery issue when install HSE fw via MU I tested the project on my board. First, I had to fix RAM initialization in startup files because I got hardfault when the pink file was copied to RAM. The RAM initialization is not the best one in these HSE demo examples, so I did quick fix like this: Pemicro debugger initializes the RAM automatically and RAM content is retained over functional resets, so you probably did not see this issue. But it would not work after power-on. I used Trace32 for debugging, so I saw it right at the beginning. Then I modified IVT – I removed pointer to the pink file, so it is not installed automatically after first reset and I can confirm installation via MU. And the result – I got 0xDACACADA and the firmware is installed via MU. So, the procedure is obviously correct. The question is why it does not work on your side. What is the SBAF version on your device? Please read double word at 0x4039_C020. Regards, Lukas Re: S32K3 recovery issue when install HSE fw via MU Additionally, we are currently using HSE FW version 0.2.55.0. Re: S32K3 recovery issue when install HSE fw via MU This is the result I read. Re: S32K3 recovery issue when install HSE fw via MU hello, @lukaszadrapa . I haven't resolved this issue yet. If you have any progress on your end, please let me know. Thank you. Re: S32K3 recovery issue when install HSE fw via MU Thank you! I successfully restored the HSE firmware by directly triggering a SWAP request. However, what puzzles me is that I had been using the FULL_MEM firmware all along—so why was the firmware restored via AB_SWAP in the end? Re: S32K3 recovery issue when install HSE fw via MU I’m sorry for delayed response. You have SBAF version 0.15.0 which is fully compatible with HSE firmware 0.2.55.0. There’s no problem with this. For my test, I erased the firmware completely using service HSE_SRV_ID_ERASE_FW, so there’s no valid backup in passive partition. In your case, it looks like the backup is available, so the flow may be different (not sure why this does not work). I can see in your code that swap only is not implemented. Could you try to add it to your code? This could solve the problem. Regards, Lukas Re: S32K3 recovery issue when install HSE fw via MU That’s interesting. Frankly speaking, I made a mistake – I’m jumping between a lot of customers and I was somehow under impression that you use AB_SWAP, not FULL_MEM. Otherwise I would not recommend it. I can see two possible explanations – if there’s still valid backup of the firmware, it is possible that the “swap” command works also for FULL_MEM version even if it is not described in the MU procedure for FULL_MEM. Second option is that functional resets triggered by your recovery application forced SBAF to erase the firmware completely and then the installation was successful. Not really sure, this is quite hard to reproduce and confirm...

EasyEVSE信号板兼容性和可用性 我正在搭建一个 EasyEVSE 开发系统，有一些问题想请教大家。 从代码修订历史（以及 2026 年 5 月 6 日与 2026 年 5 月 6 日的对比）可以看出，2025 年 12 月版本的 CCEVCPGSUG.pdf），看起来像是软件版本 5.1.2。已移除对 EVSE-SIG-BRD2X 的支持，预计 EVSE 端将改用 SIGBRD-HPGP。 是这样吗？ 软件版本似乎是 v5.1.2增加了对 SIGBRD-HPGP 的大部分支持，之前的版本（v5.0.8）是否仍然支持 EVSE-SIG-BRD2X？ SIGBRD-HPGP 可用吗？我在 Mouser、DigiKey 或 NXP 的商店里都没找到。 我有两个 EVSE-SIG-BRD2X，我想继续推进，因为 SIGBRD-HPGP 目前似乎不是一个可行的选择。 任何见解都将不胜感激。 顺祝商祺！ 克里斯 Re: EasyEVSE signal board compatibility and availability 嗨@chrisedwards ， 正如您所提到的，更新后的电动汽车供电设备（EVSE）平台旨在利用EVSE 端的 SIGBRD-HPGP 协议。目前，电动汽车端仍然支持 EVSE-SIG-BRD2X 协议，尽管也可以使用 SIGBRD-HPGP 协议来实现。 但是，考虑到您已经拥有 EVSE-SIG-BRD2X，并且 SIGBRD-HPGP 仍在认证过程中（可能还需要一段时间才能向公众开放），我建议您坚持使用这种设置，并考虑使用最新修改之前的软件版本。您应该可以使用 v5.0.8 来支持两个 EVSE-SIG-BRD2X 设置。 BR， 埃德温。

Trap to host not working on SJA1110 Rev. D I've been working on the SJA1110-EVM board and created software to read certain frames on the host processor (Cortex-M7). For that I used the "hello world" example provided with the board and build the application from there.  I was using S32DS with Autosar-RTD. Now I switched to another board also using the SJA1110. However it is using a different revision of said switch (Rev. D). I made sure to adapt the configuration. However I can't receive any frames that should be trapped to host on the host processor there. I am trapping the frames via L2 entry with trap flag set. I made sure the L2 entry is actually used for the frames I am trying to trap. In addition I made sure that promiscuous is activated. I am also able to send frames from the host. According to the stat registers the frames, that should be received, are not dropped but still vanish after entering the switch (so the L2 rule works but they never reach the host port??). I am unsure how to narrow down the problem further and how to confirm or rule out any hardware problems. Re: Trap to host not working on SJA1110 Rev. D Hello @flxwly , Could you please clarify whether you are using SJA1110D on the SJA1110-MGS-EVM or on your own custom board? The original SJA1110-EVM was based on SJA1110A, while the newer SJA1110-MGS-EVM uses SJA1110D. At the same time, the SJA1110 family is described as pin-compatible and software-compatible, so I would not expect the trap-to-host concept itself to differ between revisions. This makes a board-specific configuration mismatch more likely than a generic Rev. D limitation. Please ensure that the EthTrcv_43_PHY configuration has been adapted accordingly and that the PHY instances are mapped correctly in EthSwt_43_SJA11XX. Please also verify that the MACConfigurationTable in EthSwt_43_SJA11XX has been updated to match your actual board topology. Unused ports should be disabled. If possible, please also share your .mex file so we can review the configuration. Best regards, Pavel Re: Trap to host not working on SJA1110 Rev. D Hello @PavelL , thank you for your quick response. I've seem to fixed it. It appears I missed to correctly configure the default VLAN 0. However I am still curious to why I could use the L2 entry to route my frames to other ports but not the host. My own custom board is using the SJA1110D.  I've attached the .mex. I am using S32SDK_SJA1110_RTM_1.0.0. Best regards, Nepomuk Re: Trap to host not working on SJA1110 Rev. D Hello @flxwly , Yes, this behavior is consistent with VLAN membership filtering. The L2 entry may still match and select the forwarding destination, but the frame will only be delivered to ports that are members of the corresponding VLAN. If default VLAN 0 was not configured correctly, it is possible that forwarding to other ports still worked while the host port could not receive the frame because it was not included in VMEMB_PORT. I have reviewed your .mex file and in addition to the VLAN 0 correction, you may also consider disabling all unused ports in the MACConfigurationTable as well as in the L2 Forwarding Table, so that the configuration matches your actual board topology as closely as possible. Best regards, Pavel Re: Trap to host not working on SJA1110 Rev. D Hello @PavelL, thank you very much. It is working as intended now. Still I have one more question regarding the in-band control extensions. Is the host port (0) included in the trailer for host-to-switch frames with trailer? The documentation in UM11107 under 5.8.2.1 does not state how exactly the ports should be set. I assumed its one bit per port. Also it seems the trailer information is not stripped completly. Best regards, Nepomuk Re: Trap to host not working on SJA1110 Rev. D Hello @flxwly , Please note: Once an answer is marked as a solution, the original query is no longer actively tracked in our system. I only receive subscription emails for updates and those can occasionally be missed. If you need further assistance, the best approach is to create a new query. Best regards, Pavel

Top 10 Ways To Get Free Adopt Me Pets Instantly in 2026 If you play Roblox's Adopt Me, you already know how exciting it is to collect rare, legendary, and ultra-rare pets. From dragons and unicorns to unique event pets, building a strong pet collection is one of the most enjoyable parts of the game. However, not everyone wants to spend Robux to expand their inventory. The good news is that there are several legitimate ways to get free Adopt Me pets without spending real money. ➤➤ Click Here To   In this guide, we'll explore the top 10 ways to get free Adopt Me pets and help you grow your collection safely and efficiently. 1. Complete Daily Login Rewards One of the easiest ways to earn free Adopt Me pets is by logging into the game every day. Adopt Me rewards active players with daily streak bonuses, including Bucks, items, and occasional opportunities to obtain eggs. The longer you maintain your login streak, the more rewards you receive. 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VOL for I2C lines at IOL 3mA Hello, This is Arumugam. May I know the VOL max voltage to consider for I2C lines. Should I consider as 0.7V @1mA or 3mA Thanks Arumugam Re: VOL for I2C lines at IOL 3mA Hi @Arumugam1982  The VOL/VOH levels for the I2C lines depend on the pad supply rail and the corresponding electrical specification of the selected pin configuration. The LPI2C pads can be supplied from either VDD_HV_A or VDD_HV_B, depending on the pin muxing and pad assignment, so this should be verified using the device IOMUX information. The datasheet defines the input thresholds (VIH/VIL) directly in the GPIO DC electrical characteristics tables. However, VOH/VOL are usually defined indirectly through the output drive current conditions, such as IOH and IOL. In practice, the recommended approach is to rely on the VOH/VOL conditions linked to the corresponding IOH/IOL parameters for the selected pad configuration, rather than assuming a specific current value (mA). A specific current should only be used if it is explicitly defined in the datasheet for that electrical characteristic. BR, VaneB Re: VOL for I2C lines at IOL 3mA Should I consider the same VOL for IOL -1mA /3mA /8mA. I need this number for my WCA calculation. Re: VOL for I2C lines at IOL 3mA Hello, Which Symbol are you using in the data sheet from Table 27 (ex. IOL_33_S)? Regards, John

LX2160A XSPI 单模式 - 未使用的引脚 您好， 当配置 XSPI 以单路模式运行时，DAT2-DAT7 信号的配置尚不明确。 它们可以不连接吗？ 诺姆 Re: LX2160A XSPI in Single Mode - Unused pins 你好， 在 LX2160A XSPI 单模式下，DAT2–DAT7 可以保持未连接状态，文档建议将未使用的 XSPI 数据引脚配置为 GPIO 输出，并保持未连接状态。 此致 Re: LX2160A XSPI in Single Mode - Unused pins 您好， 问题在于引脚是成组配置的，具体来说： XSPI1_A_DATA30_PMUX：配置 XSPI_A_DATA[3:0] 为 SPI 或 GPIO 模式 使用单模式 SPI 时，让 DAT[3:2] 浮空是否仍然安全？

S32K344 SWT reset Hello , I am trying to understand the SWT functionality. I injected stackoverflow to check how SWT reset the controller. Reset happening properly. Reset reason also match with SWT. when i continously trigger stackoverflow error, After 8 times, controller does not power up. I check many times, it working exactly 8 times only, is there any specific reason? or is it configurable? Re: S32K344 SWT reset Hi @nirmal_masilamani  This is caused by reset escalation feature. Take a look at following sections in the reference manual or just search for “reset escalation” keyword in the document for more details: 33.7.7 Functional reset escalation 33.7.8 Destructive reset escalation It can be disabled by FRET and DRET registers in MC_RGM module. Regards, Lukas Re: S32K344 SWT reset Hello @lukaszadrapa  Thank you for your response. I understood that by changing FRET and DRET, we can cfg reset escalation. In Power module there is a parameter for that.  If I keep zero in both, i am able to disable escalation but, if I change the counter between 1 to 15, its not reflecting. Still SWT working only for 8 times.

How to enter in LPM mode of MSDI MC33CD1030 on S32K396BMS-EVB using NXP MBDT Hi,  I need some MBDT reference settings or ready model for entering LPM in CD1030 using S32K396BMS-EVB. Please support. Thanks

拥有自己的身份验证系统有什么不好？ 正如标题所示。我开发了一个应用程序，它没有使用第三方身份验证，而是基于知名的库和工具（jwt、bcrypt 等）构建了自己的身份验证系统。我没有使用 Passport，因为我唯一会用到的方案是本地解决方案。这有什么问题？为什么人们建议使用第三方身份验证解决方案而不是自己构建一个？

VREFH for S32K324 Hi NXP Team, I am using the S32K324 microcontroller operating at 3.3V for my circuit. The VREFH pin in the microcontroller is connected with 3.3V (VDD_HV_A / VDD_HV_B) itself. In the datasheet, I saw a note regarding the VREFH voltage levels. But in the hardware design guidelines document this comment is not mentioned. Can somebody please explain the significance of the note mentioned in the datasheet. Thanks & Regards Hemanth  Re: VREFH for S32K324 HI @JulesW, That would be out of specification, as VREFH is limited to a minimum of 2.97 V according to the datasheet (Table 3, Operating Conditions). BR, Daniel Re: VREFH for S32K324 What if the VREH is much lower than VDD_HV_A, typically VREFH = 2.5V for a VDD = 3.3V? Re: VREFH for S32K324 The ADC result would be saturated. The injection current must be limited to 3mA per a pin. BR, Daniel Re: VREFH for S32K324 Hi Daniel, Thanks for the response. What happens if the input voltage of an ADC is greater than the VREFH of the ADC? Whether the microcontroller's ADC have any overvoltage protection or saturation mechanisms? Re: VREFH for S32K324 Hi Hemanth, The VREFH reference does not have to be connected to VDD_HV_A / VDD_HV_B. But the reference is clamped to VDD_HV_A, therefore, the voltage must not exceed VDD_HV_A + 0.1V, and the 0.1V is for RF signal only. In the HWDG rev.C, you can find the specification too: Regards, Daniel

IW610 - WLAN 活动指示器 请问一下，是否有任何 GPIO 引脚/功能可以被“误用”为 WLAN 活动指示器（随 WLAN 流量闪烁/切换）来为 LED 供电？ 据我所见，没有专用的功能来实现这一点，而且使用主机唤醒功能的想法也行不通，因为它只有在主机真正处于睡眠状态时才会启用。 Re: IW610 - WLAN Activity Indicator 谢谢，我从文档中也看到了同样的内容，但我想问一下我是否遗漏了什么。 我错误地认为 HOST WAKE UP 可能会被滥用，因为它能够为传入的数据生成事件。但是，只有当主机处于睡眠状态时，该 GPIO 信号才可用，因此也无法使用。 Re: IW610 - WLAN Activity Indicator 你好， 希望你一切都好。没有 GPIO 或备用引脚功能用于指示一般的 WLAN 流量/活动。可用的 GPIO 功能包括标准接口、共存信号、RESET 和唤醒/中断信号。 实际实现需要来自主机端（例如，基于驱动器/网络活动的软件驱动的 LED 控制）。 顺祝商祺！ 里卡多

Voltage specification for externally provided clock signal (MCX A185 VLH) I can not find the max. voltage allowed at the EXTAL48M pin for the MCXA185VLH MCU in the datasheets. I know from the LPCxxx families of microcontrollers that the oscillator input is very picky about this amplitude (0.85Vpp or similar).  Can I feed an externally generated 3.3V oscillator clock signal directly to the EXTAL48M pin?  Clock|Timers MCXA Re: Voltage specification for externally provided clock signal (MCX A185 VLH) Thanks for your post.  Yes, the datasheet specifies Vec (Externally provided input clock amplitude) with max. voltage as VIH. But as VIH is 0.7xVDD, this would mean that with VDD=3.3V, Vec max. would be 2.31V only.  So either this datasheet specification is wrong, or Vec max. is really 2.31V in case of VDD=3.3V? Re: Voltage specification for externally provided clock signal (MCX A185 VLH) Hi @wyss-11  Thanks for your post! MCXA18 does have an EXTAL48M input voltage definition, but it is specified indirectly through the standard input thresholds VIH/VIL relative to VDD, not as a separate fixed EXTAL48M voltage value. The datasheet only stands the Peak-to-peak amplitude of oscillation as typical value of 0.6V. When VDD is 3.3 V, EXTAL48M can be driven by a 3.3 V external oscillator as long as the clock meets the VIH/VIL thresholds and does not exceed the VDD + 0.3 V input limit. Re: Voltage specification for externally provided clock signal (MCX A185 VLH) Hi @wyss-11  The VEC specification refers to the minimum voltage levels required by the external oscillator input to recognize valid low and high states. When VDD = 3.3 V, 2.31 V is the minimum voltage that will be detected as a valid high level.

MK10DX256VLH7 的封装标记 你好， 能否提供 MK10DX256VLH7 的包装标记说明？ 谢谢！ Re: Package Marking for MK10DX256VLH7 为防止假冒伪劣产品，零件上的编码属于机密信息，我们无法通过此渠道提供特定字符的含义或分享任何详细信息。如有疑问，请提交工单寻求帮助。 https://www.nxp.com/support/support:SUPPORTHOME 此致， 阿隆德拉

AB SWAPS32K312 具体的な問題点は以下のとおりです。ソフトウェアがSRAM領域で停止しており、これはHSEがリカバリモードを開始したためにソフトウェアがWFI状態のままになっていることが原因と考えられます。 現在、顧客のワークフローはおおよそboot_1→boot_2→appという流れで、2段階のジャンプがあります。boot_1は更新されません。顧客がエリアAでboot_2を個別に更新した場合、その後のA/Bスワップやリセットデバッグに問題は発生しません。 しかし、エリアAでアプリを個別にアップデートすると、 ABスワップジャンプが時々失敗するが、リセット後には通信が正常に戻ることがわかった。 クライアントは過去2日間、以下の進捗状況を調査してきました（スクリーンショットが多数ありますので、以下のメールをご確認ください）。 1. エラーは依然として0X2040012eです。対応する変数DCMROD3/DCMROD4を確認しましたが、ECCエラーは見つかりませんでした。 2. お客様と進捗状況を確認した結果、デバイスがリカバリーモードに入った可能性が高いと判断しました。 Re: AB SWAPS32K312 こんにちは、 @scott071209 まず最初に、S32K3リファレンスマニュアルからリカバリーモードの可能な理由を挙げます。 こちらはHSE FWリファレンスマニュアルからの引用です: セキュアブートを使用していますか？ 両方のパーティションに同じboot_1が存在しますか？両方のパーティションに有効なIVTは存在しますか？ リセット回数は8回以上ありますか？オシロスコープでリセット信号を確認しましたか？ この文について、もう少し詳しく教えていただけますか? 「しかしながら、エリアAでアプリを個別にアップデートした場合、ABスワップ遷移が時折失敗するものの、リセット後には通信が正常に戻ることが確認されています。」 具体的にどのような点で失敗するのですか？ よろしくお願いいたします。 ルーカス

J1850-PWM SC371016 Replacement Is there a substitute for the SC371016 or a way to generate the J1850-PWN signals? I am looking to communicate with a 1999 Mustang GT cluster. Thanks, David

CodeWarrior for LA1224 Hi, I have an LA1224-RDB-BHS development board and 'CodeWarrior Development Studio for QorIQ LS series - ARM V8 ISA' (version 11.5.15) with e200 tools add on. But when I try and setup a new project for the LA1224 (e200 side, rather than VSPA), via 'File' - 'New' - 'QorIQ Configuration Project' when I get to the device selection page it does not list the LA1224 device: How do I configure a project for the LA1224 processor? Thanks Nigel Re: CodeWarrior for LA1224 New thread https://community.nxp.com/t5/Layerscape/LA1224-support-for-codewarrior-download-link-isnt-working/m-p/2382533#M16738 Re: CodeWarrior for LA1224 Please create a new thread. Thanks. Re: CodeWarrior for LA1224 Hello, this download link https://support.nxp.com/s/case/500Tg00000KW12ZIAT/community-codewarrior-for-la1224?language=en_US  doesnt work Re: CodeWarrior for LA1224 As mentioned in one of my previous posts I'm using Windows Sandbox to test this. Windows Sandbox is a VM that provides a clean Windows 11 install to allow testing of applications in a clean environment. If it does not work in that then there is something missing as it is not dependant on anything I have on the host machine.  Re: CodeWarrior for LA1224 I have verified the installation on my side, there is no problem. Please prepare a clean installation environment. Please install CW_ARMv8_v2020.06_b200629GA_Win_Offline.exe first. Then open CodeWarrior IDE in a new worksapce path. Then install the service pack com.freescale.armv8.11.5.15.E200.INT.Win.updatesite.230810 1.zip from Help->Install New Software->Add->Archive in CodeWarrior IDE. Re: CodeWarrior for LA1224 Sorry that does not work, see attached image  Re: CodeWarrior for LA1224 Please install CW_ARMv8_v2020.06_b200629GA_Win_Offline.exe in a new path. Then install the service pack com.freescale.armv8.11.5.15.E200.INT.Win.updatesite.230810 1.zip from Help->Install New Software->Add->Archive in CodeWarrior IDE. Re: CodeWarrior for LA1224 Thanks, I already have that installed, was required to get the e200 compilation working. I went back to try and install everything in a clean environment (Windows Sandbox) to see if I did something wrong. I installed CodeWarrior from CW_ARMv8_v2020.06_b200629GA_Win_Offline.exe. Once complete I check for updates, once requested all available updates to be installed it fails part way through with this error: An error occurred while installing the items session context was:(profile=epp.package.cpp, phase=org.eclipse.equinox.internal.p2.engine.phases.Install, operand=[R]com.freescale.core.debugger.fsl_gdb 13.0.0.202003111126 --> [R]com.freescale.core.debugger.fsl_gdb 14.0.0.202204131357, action=com.freescale.updater.customactions.actions.FreescaleProcessCheck). NLS missing message: param_not_set in: com.freescale.updater.customactions.Messages If I then try to install updates from com.freescale.armv8.11.5.15.E200.INT.Win.updatesite.230810.zip it takes me to a 'Install Remediation Page' (see attached image). If I go with it's recommendations it eventually returns with this error: An error occurred while installing the items session context was:(profile=epp.package.cpp, phase=org.eclipse.equinox.internal.p2.engine.phases.Install, operand=null --> [R]com.freescale.core.debugger.fsl_gdb 14.0.0.202204131357, action=com.freescale.updater.customactions.actions.FreescaleProcessCheck). NLS missing message: param_not_set in: com.freescale.updater.customactions.Messages If I try again and instead select 'Show original error and build my own solution' from the install remediation page it shows these details: Cannot complete the install because one or more required items could not be found. Software being installed: CodeWarrior Debugger 14.0.0.202308092015 (com.freescale.core.debugger.gdb.feature.feature.group 14.0.0.202308092015) Missing requirement: Target Model 14.0.0.202212091004 (com.freescale.debug.tcc 14.0.0.202212091004) requires 'osgi.bundle; org.eclipse.emf.edapt.history 0.0.0' but it could not be found Missing requirement: Target Model 14.0.0.202308092015 (com.freescale.debug.tcc 14.0.0.202308092015) requires 'osgi.bundle; org.eclipse.emf.edapt.history 0.0.0' but it could not be found Cannot satisfy dependency: From: CodeWarrior Debugger 14.0.0.202308092015 (com.freescale.core.debugger.gdb 14.0.0.202308092015) To: osgi.bundle; com.freescale.debug.tcc 12.0.0 Cannot satisfy dependency: From: CodeWarrior Debugger 14.0.0.202308092015 (com.freescale.core.debugger.gdb.feature.feature.group 14.0.0.202308092015) To: org.eclipse.equinox.p2.iu; com.freescale.core.debugger.gdb [14.0.0.202308092015,14.0.0.202308092015] Any ideas how to fix any of this? Can you install a version of Code Warrior that supports the LA12xx family of devices? And if so what images and steps are required. It's 2 weeks since my original question and we still haven't got a development environment that we can build, debug and create new projects in, which is not great considering the cost of the development platform. Thanks Nigel Re: CodeWarrior for LA1224 Please download and install the following service package from the above link. com.freescale.armv8.11.5.15.E200.INT.Win.updatesite.230810 1.zip Re: CodeWarrior for LA1224 Thanks for the documents but none of these explain how to configure Code Warrior for the LA1224 (or LA1235 more specifically).  I think something is missing from the Code Warrior installation preventing us from creating a new project for the required device (or fully debugging it).  We are using version 11.5.14 of CodeWarrior Development Studio for QorIQ LS series - ARM V8 ISA.  It has an update installed to provide the e200 compiler. We have an NXP supplied example project which builds for the LA1235 but we cannot create a new project for this device or correctly debug it (it uses the wrong gdb). So it looks like something is missing from the default installation that allows full support of the LA1224/1235 devices. Re: CodeWarrior for LA1224 Please refer to the attached use guide for configure tools for i.MX. Re: CodeWarrior for LA1224 Thanks, I've downloaded, installed and run that but it's not clear how that lets me generate a new LA1224 based project within the Code Warrior IDE. Is there some information on how to do this? Re: CodeWarrior for LA1224 I uploaded the installation file to sharepoint, please pay attention to your email box to receive the download invitation. Re: CodeWarrior for LA1224 Hi, It's not our firewall blocking it, the blocked message is coming from an NXP site: https://support.nxp.com/AFSC__FileDisallowed?name=Config_Tools_for_i.MX_v16_x64_b240506.exe&refURL=https%3A%2F%2Fsupport.nxp.com%2Fs%2Fcase%2F500Tg00000KW12ZIAT%2Fcommunity-codewarrior-for-la1224%3Flanguage%3Den_US (NOTE when trying to post this message I got this warning 'Your post has been changed because invalid HTML was found in the message body. The invalid HTML has been removed. Please review the message and submit the message when you are satisfied.' not sure what it changed) Thanks Nigel Re: CodeWarrior for LA1224 This version software cannot be downloaded from the NXP public Website. Please ask your IT to help to fix your firewall problem to access the download link. Re: CodeWarrior for LA1224 Thanks for the reply, but the download link is blocked, I've updated the case as well. Re: CodeWarrior for LA1224 Please download and install Config_Tools_for_i.MX_v16_x64_b240506.exe from the following link. https://support.nxp.com/s/case/500Tg00000KW12ZIAT/community-codewarrior-for-la1224?language=en_US LA12xx is listed under processor.

GD3160 SPI 配置 根据数据手册，如果我要配置 GD3160，需要先将 MODE_2 中的 CONFIG_EN 位设置为 1。既然如此，MODE_2 的第一位（Rb/W）应该是 0 还是 1？ Re: GD3160 SPI 配置 了解后请看下面： 正确的解释确实是： 0 = 读取 1 = 写入   Re: GD3160 SPI 配置 是的，另外除了下图中说的 CONFIG1 to 7 registers, the MODE1 and 2 registers, the RMSK1 and RMSK2 registers, and the MSK1 and 2 registers ，这些寄存器的写受MODE_2的CONFIG_EN控制，其余寄存器只要bit23为1的情况就会进行配置吗？ Re: GD3160 SPI 配置 你说的是bit23吗？

P1013 CPU/CCB/DDR Underclocking for Thermal and Communication Stability I have old P1013NSE2MHB components on dev boards.  I want to work to under clock them to reduce the thermal load on the component and use the communication clock for PCIe and SPI standard from the P1013NSE2LFB component, It is what I am most familiar with. Essentially, I want to have the P1013NSE2MHB use the P1013NXE2LFB PLL clocking setup, i.e, CPU/CCB/DDR final clock rates of the P1013NSE2MHB to be 1067/533/533 MHz.  Based on the AN4343 Section 6 both components should be able to support the 1067/533/533 clock speeds.  The only concern that I have is that the CCB limit of the P1013NSE2MHB is supposedly 480MHz. I can find no reasoning for this besides that only CCB clocks 400 and 480 MHz can use the built in PLL settings to get to the maximum of 1200MHz. (See AN4343 Section 6.2.1 Table 16) I just want the CPU to have a core clock of 1067MHz.  Both the P1013NSE2MHB use the P1013NXE2LFB are from the exact same line and should share the same architecture, the improvement in the CPU maximum clock to 1200MHz should not prevent the previously implemented CCB architecture from being used to reach a lower CPU clock speed. Unless the CCB bus was redesigned, which would be a massive waste of resources, to support the new CPU even though it isn't radically different.  Thanks for any insights. QorIQ P1 Devices Re: P1013 CPU/CCB/DDR Underclocking for Thermal and Communication Stability It seems the architecture may be different according to the data below, the CPU/CCB/DDR may not share the same trend CPU/CCB/DDR frequency (MHz) LF=1067/533/667    MH=1200/480/800 But this is old device so may need to check with NXP internal team for the explaination Re: P1013 CPU/CCB/DDR Underclocking for Thermal and Communication Stability The T2080/T2081 are not the processors I am asking about. I am looking at the P1013/P1022 processors. Re: P1013 CPU/CCB/DDR Underclocking for Thermal and Communication Stability Hello, Yes — the documentation supports your observation that CPU/core, platform/CCB, and DDR do not have to follow the same scaling trend on T2080/T2081, because they are generated by different PLL domains and the memory bus is explicitly dictated by its own PLL . Core and platform clocks are generated by different PLLs , and the T2080/T2081 clocking map exposes separate status/control points for core-cluster PLLs, the platform PLL, and the DDR PLL ( Clocking_PLLCnGSR , Clocking_PLLPGSR , Clocking_PLLDGSR ) The hardware specs also state directly that the memory bus clock speed is dictated by its own PLL. So the architectural explanation is: CPU/core frequency comes from the core cluster PLL(s) and may run at PLL/1, /2, or /4 depending on configuration. Platform/CCB frequency is a separate platform clock domain with its own allowed SYSCLK ratios. DDR frequency is separate again, and the memory bus clock is half the DDR data rate and is controlled by its own PLL That is why a non-monotonic-looking pair such as: LF = 1067 / 533 / 667 MH = 1200 / 480 / 800 is architecturally plausible in principle: the three domains are not required to rise and fall together. However, I could not find those exact two T2080 frequency triplets documented in the available T2080/T2081 material.   Regards

PN7462AU FreeRTOS: Unable to switch from heap_3 to heap_4, system stuck + heap usage visibility Hi Team, I am using the PN7462AU platform with FreeRTOS, and the SDK example is configured to use heap_3.c. I am facing memory overflow issues and would like to better understand the heap configuration. Since heap_3 uses the standard library's malloc()/free(), functions such as xPortGetFreeHeapSize() and heap statistics are not available. To gain visibility into heap usage and potentially increase the available heap, I tried switching from heap_3.c to heap_4.c by disabling heap_3.c and enabling heap_4.c. However, the application gets stuck during startup after making this change. I have the following questions: Is it safe and recommended to switch from heap_3 to heap_4 on PN7462AU? How can I determine the amount of memory currently available to heap_3? Since heap_3 does not support xPortGetFreeHeapSize(), what are the recommended methods to monitor heap usage and detect memory exhaustion? What additional configuration changes are required when migrating from heap_3 to heap_4 (e.g., configTOTAL_HEAP_SIZE, linker script changes, memory regions, etc.)? Any guidance or examples specific to PN7462AU and FreeRTOS would be appreciated. Thank you Core and Memory Re: PN7462AU FreeRTOS: Unable to switch from heap_3 to heap_4, system stuck + heap usage visibility Hello @uday_gowda, The NFC reader library offers examples that shows the implementation of FreeRTOS with the PN7462 that could be helpful. Also, I can recommend see the AN11784, it provides guidance on integrating an RTOS with the PN7462, that you can take by reference. MCUXpresso IDE also includes several debugging features for FreeRTOS based applications. In particular, the "Heap Usage view" can help you in this case. Additional details are available in the chapter 3.6 of MCUXpresso IDE 25.06 FreeRTOS Debug Guide. Finally, please take in mind that the PN7462 only have 12k of the SRAM. BR Habib

S32K328でのマルチコア有効化後のHSE_Bサービス応答なし問題 NXPテクニカルサポートチーム様 S32K328プラットフォームでマルチコア操作を有効にした後、HSE_Bサービスがハングアップ（応答なし）する問題について、技術的なサポートをお願いしたくご連絡いたしました。 1. 環境とセットアップ - MCU: S32K328 (デュアル Cortex-M7 + HSE_B) - 設定ツール：EB tresos（MCAL設定用） - コアロール: M7_0 と M7_1 は Autosar-OS と同時に実行されます。 M7_0は、メッセージ記述子用の共有SRAMを使用してHSE_Bと通信します。 2. XRDCおよびペリフェラルの設定（テスト用） 権限の問題を切り分けるために、非常に寛容な構成を適用しましたが、M7_0とHSE_Bを単一のドメインにグループ化するか、別々のドメインに分離するかに関わらず、症状は同じままです。 - メモリ構成: すべてのSRAM領域へのフルアクセスが許可され、特定のPFLASH/DFLASH領域がHSEに割り当てられます。 - 周辺機器設定 (PDAC): CONFIGURATION_GPR、PFC/PFC_ALT、FMU/FMU_ALT、および MU_0 / MU_1 にフルアクセス権限が割り当てられています。 3. ブートシーケンス アプリケーションは以下の起動シーケンスに従います。 3.1 M7_0 ブート → クロック初期化。 3.2 HSE STATUS が INIT_OK であることを確認します。 3.3 リソースマネージャの初期化（XRDC セットアップ用の RM_Init）。 3.4 ペリフェラルの初期化 3.5 M7_1 (コア 1) を開始します。 3.6 OSを起動する。 4．問題の説明と症状 M7_0とM7_1はどちらもOS環境内で正常に起動し、動作します。しかし、その後HSEサービスリクエストが呼び出されると、HSEは応答せず、ハングアップ状態になる。ハング発生時のレジスタの状態は以下のとおりです。 - XRDC登録状況: XRDC_DERRLOC[3]が0x00020000に変更されます。 ただし、DERR_W3_0/1/2 レジスタまたは DERR_W3_16/17/18 レジスタにはエラー値は記録されません。 - メッセージングユニット（MU_0）ステータス： MU_0_TSRレジスタでは、フラグTE1とTE2は「空でない」状態のままで、クリアされません。 MU_0_FSRレジスタでは、F3フラグは変更されません。 5. 質問 5.1 XRDC_DERRLOC[3]がシフトしているにもかかわらず、DERR_W3_xレジスタに特定のエラーの詳細が表示されない場合、この動作を引き起こしている原因は何でしょうか？これは、HSE内部のDMAまたはバスマトリックス構成による暗黙的なアクセス違反に関連している可能性がありますか？ 5.2共有SRAMはMPUによって明示的にキャッシュ不可として構成されているにもかかわらず、HSEがディスクリプタを読み取ることを妨げるような、既知のマルチコア制約やOS環境下での隠れたキャッシュ動作はありますか？ 5.3 HSE_STATUS_INIT_OK チェックまたはコア 1 の起動に関連して、RM_Init (XRDC 初期化) の実行タイミングに関する既知の制約または前提条件はありますか？ 5.4 MU送信ステータスレジスタ（TE1/TE2）がスタックし、HSEが記述子を処理しない理由を特定するために、どのような手順または追加のレジスタを確認する必要がありますか？ このボトルネックを解消するためのご意見やご指導をいただければ大変ありがたく存じます。 よろしくお願いいたします。 Re: HSE_B Service No-Response Issue after Multi-Core Activation on S32K328 こんにちは、 @NewbieNerd さん HSEは常に回答を返すことになっている。応答がない場合、HSEはシャットダウンモードに移行した可能性が高いです。これは致命的なエラーが発生した場合に起こります。例えば、アクセス権限の不足、ダブルビットECCエラー、無効なアドレスなどが原因でHSEがデータを読み書きできない場合。 これは、MU_0のGSRレジスタを読み取ることで確認できます。ビット「0」が設定されている場合、HSEはシャットダウンモードです。 XRDCでエラーの詳細を確認するには、「19.7.3.2」の項に従う必要があります。S32K3リファレンスマニュアルの「ドメインアクセス違反エラーの処理」を参照してください。 ステップ2では、DERRレジスターの詳細を確認することが重要です。 デバッグを迅速に行うには、MDA_W0_0_DFMT0にDID=3を書き込むことで、Cortex-M7_0 / Cortex-M7_0_debugをドメイン3に移動できます（S32K328ではHSEは常にドメイン3にあります）。 すると、DERR に詳細が表示されます (これは、HSE によって何らかのエラーが発生したときにデバッガーで確認した例です)。DID = 0 の場合は、これは表示されませんでした。 これは何が問題だったのかの手がかりになるはずだ。 もう一つ重要な点は、HSE_STATUS_INIT_OKが設定された後にXRDCを有効にする必要があるということです。これはHSE FWリファレンスマニュアルに明記されています。 よろしくお願いいたします。 ルーカス Re: HSE_B Service No-Response Issue after Multi-Core Activation on S32K328 迅速なご返信ありがとうございます。ご要望いただいた開発環境の具体的なバージョン情報は以下のとおりです。 1. ソフトウェアおよびファームウェアのバージョン - HSEファームウェア: S32K358_0_2_40_0 注：このバージョンを使用しているのは、ドキュメントにS32K328派生版をサポートしていると明記されているためです。    -  RTD (リアルタイム・ドライバ):  AUTOSAR リリースバージョン: 4.7.0、ソフトウェアバージョン：3.0.0 2. 開発ツールチェーン IDE: このプロジェクトではS32DSを使用していません。 設定ツール：EB tresos Studioは、すべてのMCAL設定に使用されています。 EB tresos バージョン: 27.1.0 3. 追加情報 私は現在、ホスト側（Cortex-M7）の開発を主導しています。私たちは既に、この行動について社内のHSE FW開発チームと徹底的に協議し、合意形成を図っています。しかしながら、HSE FWの観点からは根本原因や異常は見つからなかったため、これはマルチコア/OSの初期化中に発生したホスト側のランタイム構成または同期の問題である可能性が高いと推測されます。 あなたのご指導のもと、正確なボトルネックを特定できることを心から願っております。EB tresosプロジェクトから、さらに設定ダンプやレジスタキャプチャが必要な場合はお知らせください。 よろしくお願いいたします。 Re: HSE_B Service No-Response Issue after Multi-Core Activation on S32K328 使用されているHSEファームウェアのバージョン、RTDおよびS32DSのリビジョンを具体的にご指定いただけますでしょうか？ありがとう Re: HSE_B Service No-Response Issue after Multi-Core Activation on S32K328 貴重なデバッグガイドと洞察をありがとうございました。 ご提案いただいた件について、さらに調査を行い、弊社側で以下の結果を確認いたしました。これらの調査結果を共有し、ツール構成の制約を回避する方法についてご助言をいただきたく存じます。 1. RTDバージョンの明確化 前回のやり取りでお伝えしたとおり、現在弊社では以下のものを使用しています。 - RTDソフトウェアバージョン：3.0.0 - AUTOSAR リリースバージョン: 4.7.0 2. EB tresos構成制約（ドメイン割り当て） S32K328では、HSEはドメイン3に恒久的に割り当てられているとおっしゃっていましたね。 しかし、EB tresos (v27.1.0) ではRTD 3.0.0 環境プラグインの場合、リソースマネージャ（RM）の構成構造では、ドメイン2（ドメインID 0、1、2）までしか割り当てることができません。 設定ツールではドメインの最大数が2に制限されているため、EB tresosを介してドメイン3にマスター/スレーブを適切に設定または割り当てることはできません。 質問：S32K328派生機種のEB tresosでドメイン3の設定を公式に有効化するRTDバージョンまたはパッチを具体的に教えていただけますか？それとも、実行時コードを使ってXRDCレジスタを手動でオーバーライドする必要があるのでしょうか？ 3. XRDCエラーレジスタの状態（DERRLOCとDERR_Ww_iの比較） リファレンス・マニュアルの手順に従って、エラー状態中に以下の動作を確認しました。 XRDC_DERRLOC[3]はダンプによって0x00020000としてキャプチャされますが、周辺機器ビューではキャプチャされません（DERRLOC[3]は存在しません）。 しかし、エラー処理の手順に従ったにもかかわらず、すべてのDERR_Ww_iレジスタは0のままです。 ご指摘のとおり、DERRに詳細情報が不足しているのは、ホストコア（Cortex-M7_0）が別のドメイン（例えば、DID=0または1）で動作しているため、ドメイン3（HSE）によって生成されたエラーログを読み取ることができないことが原因のようです。 4. 実行タイミングの検証 ブートシーケンスを再確認した結果、HSE_STATUS_INIT_OKが設定された後にXRDCが明示的に有効になっていることを確認しました。これはHSE FWリファレンスマニュアルの要件に準拠しています。 5．指導依頼 上記のツール制約により、Cortex-M7_0またはそのデバッグマスターをEB tresos内のドメイン3に容易に移動できないため、以下の点についてアドバイスをいただけますでしょうか。 MCALの初期化を壊さずに、デバッグのためにMDA_W0_0_DFMT0を強制的にDID=3にオーバーライドする適切な方法はありますか？ RTD 3.0.0において、ドメイン0/1からドメイン3のエラーレジスタを検査するための既知の回避策はありますか？ 引き続きサポートいただき、誠にありがとうございます。 Re: HSE_B Service No-Response Issue after Multi-Core Activation on S32K328 ドメイン3が欠落していることは、RTD 3.0.0における既知の問題です。バージョン4.0.0以降で修正されています。推奨される解決策は、RTDを最新バージョンにアップグレードすることです。そうでなければ、XRDC レジスタの書き換え、構成ファイルの書き換え、新しい RTD で構成ファイルの生成、そしてそれをプロジェクトで使用するなど、何らかの回避策を手動で実装する必要が生じます。しかし、これは一時的な応急処置に過ぎず、推奨されるクリーンな解決策は、新しい RTD を使用することです。 「19.7.3.2」の項によるとドメインアクセス違反エラーの処理」では、エラーハンドラのためにドメインを再設定するのが一時的であるべきです。この段階では、デバッガーを使ってDIDを修正し、エラーの詳細を読み取れるようにしてみるのが良いでしょう。 MU_0のGSRレジスタのビット0が設定されていることを確認しましたか？ よろしくお願いいたします。 ルーカス