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P1013 CPU/CCB/DDR Underclocking for Thermal and Communication Stability

I have old P1013NSE2MHB components on dev boards.

I want to work to under clock them to reduce the thermal load on the component and use the communication clock for PCIe and SPI standard from the P1013NSE2LFB component, It is what I am most familiar with.

Essentially, I want to have the P1013NSE2MHB use the P1013NXE2LFB PLL clocking setup, i.e, CPU/CCB/DDR final clock rates of the P1013NSE2MHB to be 1067/533/533 MHz.

Based on the AN4343 Section 6 both components should be able to support the 1067/533/533 clock speeds.

The only concern that I have is that the CCB limit of the P1013NSE2MHB is supposedly 480MHz. I can find no reasoning for this besides that only CCB clocks 400 and 480 MHz can use the built in PLL settings to get to the maximum of 1200MHz. (See AN4343 Section 6.2.1 Table 16)

I just want the CPU to have a core clock of 1067MHz.

Both the P1013NSE2MHB use the P1013NXE2LFB are from the exact same line and should share the same architecture, the improvement in the CPU maximum clock to 1200MHz should not prevent the previously implemented CCB architecture from being used to reach a lower CPU clock speed. Unless the CCB bus was redesigned, which would be a massive waste of resources, to support the new CPU even though it isn't radically different.

Thanks for any insights.

QorIQ P1 Devices

Re: P1013 CPU/CCB/DDR Underclocking for Thermal and Communication Stability

It seems the architecture may be different according to the data below, the CPU/CCB/DDR may not share the same trend

CPU/CCB/DDR frequency (MHz) LF=1067/533/667 MH=1200/480/800

But this is old device so may need to check with NXP internal team for the explaination

Re: P1013 CPU/CCB/DDR Underclocking for Thermal and Communication Stability

The T2080/T2081 are not the processors I am asking about.
I am looking at the P1013/P1022 processors.

Re: P1013 CPU/CCB/DDR Underclocking for Thermal and Communication Stability

Hello,

Yes — the documentation supports your observation that CPU/core, platform/CCB, and DDR do not have to follow the same scaling trend on T2080/T2081, because they are generated by different PLL domains and the memory bus is explicitly dictated by its own PLL . Core and platform clocks are generated by different PLLs , and the T2080/T2081 clocking map exposes separate status/control points for core-cluster PLLs, the platform PLL, and the DDR PLL ( Clocking_PLLCnGSR , Clocking_PLLPGSR , Clocking_PLLDGSR) The hardware specs also state directly that the memory bus clock speed is dictated by its own PLL.

So the architectural explanation is:

CPU/core frequency comes from the core cluster PLL(s) and may run at PLL/1, /2, or /4 depending on configuration.
Platform/CCB frequency is a separate platform clock domain with its own allowed SYSCLK ratios.
DDR frequency is separate again, and the memory bus clock is half the DDR data rate and is controlled by its own PLL

That is why a non-monotonic-looking pair such as:

LF = 1067 / 533 / 667
MH = 1200 / 480 / 800

is architecturally plausible in principle: the three domains are not required to rise and fall together. However, I could not find those exact two T2080 frequency triplets documented in the available T2080/T2081 material.

Regards