Unable to access the UART port using A55 core of imx93 board (Digi coreconnect 93) Dear NXP Support Team, I want to attach a sensor in the UART port of the board and access via A55 core. I have tried below things but neither of them worked. Total available port from UART1 to UART8 – 8 Nos The UART4 port as a Xbee interface is available like ttyXBee, so I also attempted to transfer data using c code and directly using command line but none of them where worked. Followed the URAT instruction from this website, and I am getting port ttyLP3, ttyLP5 and ttyLP6 port. The port ttyLP3 and ttyLP5 have no pinout on the board. The ttyLP6 is connected with the console port which is ttyACM0 (UART to USB), so we cannot use it. Tried to configure UART7 (Mikroe interface) but the tty node is not created, maybe it missed configuration from dts side. (I am unsure about it) The UART1 is connected to the Bluetooth chip, so it cannot be accessible. No details found from UART2 and UART8.   Can you guide me how to access the UART port using A55 core of the board and C language programming? Re: Unable to access the UART port using A55 core of imx93 board (Digi coreconnect 93) Hi @rk4! Your UART7 is configured as a rs485 in file ccimx93-dvk.dts &lpuart7 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart7>; linux,rs485-enabled-at-boot-time; digi,rts-gpio = <&gpio2 10 GPIO_ACTIVE_HIGH>; /delete-property/dmas; /delete-property/dma-names; status = "okay"; }; only delete the line linux,rs485-enabled-at-boot-time; and the uart7 should be listed in the device folder with the name ttyLP6 Best Regards! Chavira Re: Unable to access the UART port using A55 core of imx93 board (Digi coreconnect 93) Hello @Chavira ,  Please find attached dts file that I am using. Re: Unable to access the UART port using A55 core of imx93 board (Digi coreconnect 93) HI @rk4! Please share your device tree file. Re: Unable to access the UART port using A55 core of imx93 board (Digi coreconnect 93) Dear @Chavira ,  Thanks for prompt response. Could you tell me how to create a ttynode for UART7 (MIKROE interface) in A55 core? OR if its already available in it, can you tell me what is the name of it? Re: Unable to access the UART port using A55 core of imx93 board (Digi coreconnect 93) HI @rk4! Thank you for contacting NXP Support! I don´t have access to the device tree of that board since is not an NXP board. I can help you to analyze the device tree if you can share the device tree with me. Unfortunately we don´t have any guide of how to use UART ports in Linux, but you can check some guides in internet like this guide. For Further support please contact to digi support. Best Regards! Chavira

S32G2 load dtb I got dts both in ATF and in kernal.When the board boots,Which dtb it will actually use?Or it will load both? Thank u. Re: S32G2 load dtb Hi, Both DTB/DTS will be used. When booting, TF-A/uboot will use the TF-A DTS/DTB, when uboot passes the control to the kernel, the kernel will use its own DTB/DTS. There is no conflict between both. Both DTB/DTS should be configured accordingly, if not when uboot passes control to the kernel, devices might not be available to the kernel itself. Please, let us know. Re: S32G2 load dtb Sorry，I can not understand well and could you describe it more detailed.I can find the same device in DTS both in ATF and kernal. Do they conflict with each other? Re: S32G2 load dtb Hi, Both DTB's will be used at the end, but the one that is available under the root partition of the SD card should be the Kernel one. Please, let us know.

I2C MPC5478G Hi, I want to communicate with an amplifier using the MPC5748G. I'm using the i2c_transfer_mpc5748g sample code from the Power Architecture. The amplifier's address is 0x70. What modifications do I need to make to achieve this? also i2c driver sends adress->data  but i want to make it adress of amplifier(adress) ->amplifier register(subadress)-> data. Re: I2C MPC5478G Hi, the Slave device address is set within Component inspector and it is automatically sent as first byte after START is issued. The Slave’s register/memory address, must be stored into first byte(s) of the “txBuffer” depending on address size.   So assuming 16bit address is used and you want to write 8 bytes (1,2,3,..,8) to Slave address 0x000C, then prepare txBuffer as   txBuffer = {0x00, 0x0C, 1, 2, 3, 4, 5, 6, 7, 8};   and use I2C_DRV_MasterSendDataBlocking(instance, txBuffer, 10, true, timeout);   If you want to read 8 bytes from the same memory address then use this   I2C_DRV_MasterSendDataBlocking(instance, txBuffer, 2, false, timeout); // just memory/register address will be sent after Slave address so total 3 bytes, STOP is not generated I2C_DRV_MasterReceiveDataBlocking(instance, rxBuffer, 8, true, timeout); // Repeat Start is issued following Slave address and waiting reading for 8 bytes Hope it helps. BR, Petr

FS4500 wake up Asking for help, 1. I want to know whether it is only necessary to call the SPI instruction to set the GO_LPOFF bit to 1 when setting the FS4500 sleep mode. After the SPI instruction is written successfully, the code running phenomenon will stop executing the subsequent code. 2. Given that the INH pin of 1145 transceiver is connected to IO_0 of FS4500, if you want to use 1145 transceiver to wake up FS4500 from LPOFF, do you only need to use the host computer to send CAN packet to wake up 1145 transceiver? The INH pin of the 1145 transceiver automatically affects the IO_0 of the FS4500 to wake up the FS4500. Can the subsequent code be continued, or does another method be required to wake up the FS4500? Asking for help Re: FS4500 wake up 1. I want to know whether it is only necessary to call the SPI instruction to set the GO_LPOFF bit to 1 when setting the FS4500 sleep mode. After the SPI instruction is written successfully, the code running phenomenon will stop executing the subsequent code. [GW]看我标出来的箭头两个方式进入sleep的模式。 DFS要不要进入看上面的SELECTpin设定 2. Given that the INH pin of 1145 transceiver is connected to IO_0 of FS4500, if you want to use 1145 transceiver to wake up FS4500 from LPOFF, do you only need to use the host computer to send CAN packet to wake up 1145 transceiver? The INH pin of the 1145 transceiver automatically affects the IO_0 of the FS4500 to wake up the FS4500. Can the subsequent code be continued, or does another method be required to wake up the FS4500? [gw]你是想通过1145的INHpin唤醒FS45吗从LPOFF模式？可以看下面圈出来的唤醒方式，如果是通过IO唤醒在进入sleep之前就要设定好，你要看不同模式下1145 INH的状态是不是符合唤醒的要求从而决定要不要1145 进入低功耗模式，逻辑很清楚需要您自己去设计这个功能 Re: FS4500 wake up Hello, we don’t have a corporate email yet, but we have corporate WeChat. Can you send me the relevant information through corporate WeChat? Corporate WeChat inbox: [email protected] Re: FS4500 wake up The board I am using now has several layers, and the wiring between them is in the middle, which is not easy to disconnect. According to the manual, IO_0 should be input. I am not sure why the SPI operation FS4500 instruction enters sleep mode and affects the INH output of 1145 Re: FS4500 wake up What caused this? Re: FS4500 wake up There is a test of the INH pin of 1145. When it initially enters the low power mode, it is 0 when tested with a multimeter. After sending a message using the host computer, the INH pin is tested again and it is 12v. Re: FS4500 wake up 1. After using the SPI instruction to set the register GO_LPOFF to 1, is it normal for the code to stop running at this time? 【gw】See the description below and the MCU is out of power after entering sleep mode. 2. From the manual, no matter the current state is LPOFF-sleep or Deep fail safe, it can be awakened by IO_0. Before using the SPI instruction to set FS4500 to enter low power consumption, 1145 has been set to sleep mode, and the register WU_IO0_1:0 of FS4500 has been set to 01. Is there any other operation required? Then use the host computer to send CAN message to wake up 1145. Phenomenon: FS4500 cannot exit low power consumption and the code cannot continue to run 【gw】After entering sleep, did you capture the voltage change waveform of INH? Re: FS4500 wake up I have tested a phenomenon. 1. After the 1145 transceiver is initialized and enters sleep mode, the INH pin of 1145 is measured to be low level, and the IO_0 pin of FS4500 is tested to be low level at this time (this is correct). 2. Then FS4500 executes the initialization process, FS4500 changes to normal mode, measures the INH pin of 1145 to be low level, and tests the IO_0 pin of FS4500 to be low level (this is correct). 3. After setting FS4500 to sleep mode through SPI instruction (just modify register GO_LPOFF to 1), the INH pin of 1145 is high at this time, and the IO_0 pin of FS4500 is high at this time. Currently, no message is sent to the host computer. Why is this? However, the code phenomenon still stops executing subsequent codes. Re: FS4500 wake up What company are you from? Do you have a website? Re: FS4500 wake up Thank you for your answer, I found the cause of the problem now. Re: FS4500 wake up This wake-up configuration is configured during the initialization INIT phase, not during the normal phase. Did you touch this register during initialization? Re: FS4500 wake up In the third step, disconnect 1145 INH and see if SBC IO0 is high or INH is high. If you do not operate, 1145 is still in sleep. Re: FS4500 wake up Thanks for your answer, I want to confirm. 1. After using the SPI instruction to set the register GO_LPOFF to 1, is it normal for the code to stop running at this time? 2. From the manual, no matter the current state is LPOFF-sleep or Deep fail safe, it can be awakened by IO_0. Before using the SPI instruction to set FS4500 to enter low power consumption, 1145 has been set to sleep mode, and the register WU_IO0_1:0 of FS4500 has been set to 01. Is there any other operation required? Then use the host computer to send CAN message to wake up 1145. Phenomenon: FS4500 cannot exit low power consumption and the code cannot continue to run Re: FS4500 wake up Hello, company website https://gkanghui.com/ Re: FS4500 wake up Which company are you from? Can I use the company's email address to ask questions? Because we can handle it at a lower level if you use a personal email address

If develop something using GoldVIP-1.6.0, cannot use LLCE CAN. I am using GoldVIP-S32G2-v1.6.0 on S32G2 due to some circumstances and I am having a problem. I referred to the User Manual.pdf file of GoldVIP-S32G2 v1.6.0 and proceeded as follows. 1. I installed Goldvip- S32G2 v1.6.0 and EBTresos ACG8.8.7, S32DS 3.4. 2. Follow the steps in Figure 13.4 Building the M7 Application below.   2-1. Generated the default configuration information using EBTresos.   2-2. I built using Util of GoldVIP-S32G2-v1.6.0 and created an Elf file.   2-3. create goldvip-gateway.bin file using objcopy in S32DS Build_tools folder. 3. create an SDcard using fsl-image-goldvip-s32g274ardb2.sdcard and replace only the goldvip-gateway.bin file in the SDcard to write to the board. 4. I checked using Trace32 Debug and found that it booted well and LLCE_CAN0 and LLCE_CAN1 were set to use. 5. The problem was that even though I sent LLCE_CAN0 and LLCE_CAN1 using CANoe, CAN Interrupt did not work, so I could not check the can data coming in. I used GoldVIP-S32G2-v1.0.0 two years ago and experienced that the CanIf_RxIndication function shown in the screen below is called when CANoe successfully sends CAN data in the same way as above. Currently, I confirmed that the CanIf_RxIndication function is not called in the same way, and after debugging, I realized that receiving CAN data does not cause an interrupt. I would be grateful if you could let me know if I missed something and what else I can do and if you need more information to answer. S32G-VNP-RDB2 AUTOSAR GOLDVIP 1.6 Re: If develop something using GoldVIP-1.6.0, cannot use LLCE CAN. Thank you for your continued response. I'm resolved.  When I disable CanMultiplexedTransmission and change both Filter and Mask to 0, I get an interrupt. It looks like filter and mask were preventing the data from coming in. Re: If develop something using GoldVIP-1.6.0, cannot use LLCE CAN. Hi, We might be misunderstanding the overall inquiry. If so we do apologize. For the following comment: "After writing, a CAN data is sent via CANoe, but CANoe shows that the transmission was successful, but no RX interrupt occurs in Trace32." We understand that you are able to receive CAN frames under the S32G2, is this correct? This might seem to be related to Trace32 rather than S32G2 if you are able to receive CAN Frames. Can you replicate the examples available under the BSP User Manual?  Please, let us know. Re: If develop something using GoldVIP-1.6.0, cannot use LLCE CAN. Hello Thank you for the reply. I was refer to GoldVIP-S32G2-1.6.0-User-Manual.pdf. I have attached the file. I didn't use anything related to the Linux BSP.  I used the fsl-image-goldvip-s32g274ardb2.sdcard file provided by NXP to create the SDcard. and then I created the goldvip-gateway.bin file for Firmware and then replaced the goldvip-gateway.bin on the SDcard as described in the question above. After writing, a CAN data is sent via CANoe, but CANoe shows that the transmission was successful, but no RX interrupt occurs in Trace32. For reference, when I installed and developed the RTD and LLCE Driver using S32DesignStudio, I found that CAN Rx interrupts were generated. Re: If develop something using GoldVIP-1.6.0, cannot use LLCE CAN. Hi, We apologize for the delay. Can you help us share the respective logs of your system? Also, were you able to run the available examples for LLCE CAN under the BSP User Manual?  Overall, we have not seen any problems with LLCE CAN not receiving information, for which seems to be a configuration problem.  Please, let us know. Re: If develop something using GoldVIP-1.6.0, cannot use LLCE CAN. There is a typo in the above post. The version of GoldVIP I've been using is v1.1.0, not v1.0.0. I used GoldVIP-S32G2-v1.0.0 two years ago -> I used GoldVIP-S32G2-v1.1.0 two years ago

How to flush the uart FIFO with CTS enabled for S32K146 Hi support team, We're using UART Tx FIFO function with CTS feature enabled. After having checked with the errata file of S32K146, we find that the ERR051629 is related to our case. My understanding of this issue is that if the CTS pin is changed to low during the tx FIFO is flushing with CTS feature enabled, the transmit complete bit will not be set, the workaround is to clear the MODIR[TXCTSE] bit before setting FIFO[TXFLUSH] bit to 1 if the CTS feature is enabled, and then set the MODIR[TXCTSE] bit again, such as the following code changes based on the NXP RTD code: /** * @brief : Flush Tx Buffer * * This function causes all data that is stored in the transmit FIFO/buffer to be flushed. * * * @Param Base LPUART Base pointer */ static inline void Lpuart_Uart_Ip_FlushTxBuffer(LPUART_Type * Base) { Base->MODIR &= 0xFFFFFFFEu; /*Clear (MODIR[TXCTSE]) bit*/ Base->FIFO |= 0x00008000u; /*reset the transmit FIFO (FIFO[TXFLUSH] = 0b1)*/ Base->MODIR |= 0x00000001u; /*Set (MODIR[TXCTSE]) bit*/ } Is my understanding correct? If it's not correct, how should I handle this problem?  Re: How to flush the uart FIFO with CTS enabled for S32K146 HI @snowy, CTS_B is asserted when the input voltage level goes LOW. The CTS_B pin must assert for longer than one bit period to guarantee that a new transmission is started when the transmitter is idle. The transmitter checks the state of the CTS signal each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the TXD signal remains in the mark state and transmission is delayed until CTS is asserted. So, it will not stop transmitting, it will send the data present in the FIFO. Regards, Daniel Re: How to flush the uart FIFO with CTS enabled for S32K146 Hi Daniel, Thank you very much for your reply. Could you please help check the following question? If the CTS pin is changed to low during writing data into tx FIFO, will the data stop transmitting until the CTS pin be changed back to high? Or the tx will be abort directly with data lost? Re: How to flush the uart FIFO with CTS enabled for S32K146 Helle @snowy, Yes, this is correct. If you have any specific question, let me know, BR, Daniel

How to quit u-boot and start normal boot? I am not able to return to normal boot after executing the following command. Is there any solution for this? u-boot=> setenv fdtfile imx8mq-evk-usdhc2-m2.dtb u-boot=> saveenv u-boot=> reset Environment: OS: LF_v6.6.3-1.0.0_images_IMX8MMEVK.zip Hardware: i.MX 8M Mini Evaluation Kit Re: How to quit u-boot and start normal boot? I close this topic because it will be more appropriate to move to the following topic. https://community.nxp.com/t5/Other-NXP-Products/How-to-use-an-external-WiFi-card-on-8MMINILPD4-EVKB/m-p/1916040#M24339 Re: How to quit u-boot and start normal boot? I just found the following guidance on console after power on, but nothing happens even if I hit any key within 2sec. time limit. Hit any key to stop autoboot: 2

S32KのSDKについて助けが必要で、ASPICEのクラスです S32KのSDKについて助けが必要で、ASPICEのクラスです、ありがとう!

How To read the IAP Flash Memory read on LPC865 Hi NXP Experts, I am trying to write and read data to the IAP flash memory on the LPC865M201JHI48 microcontroller. My condition is that I want to write and read data for different pages of one sector. Case 1: Data = 10 Sector = 60 Data1 Address = 0x0000F000 Page = 960 Case 2: Data = 3999 Sector = 60 Data2 Address = 0x0000F040 Page = 961 Case 3: Data = 200 Sector = 60 Data3 Address = 0x0000F080 Page = 962 Case 4: Data = 1234 Sector = 60 Data4 Address = 0x0000F0C0 Page = 963 I am trying to write the data individually to single pages. In Case 1, I write data to the address 0x0000F000 and read the data using the same address. I get the correct data that I wrote. Later, I use Case 2 with the address 0x0000F040, and I read the data using the same address. I get the correct data perfectly as I wrote before. However, whenever I try to write to both addresses at the same time (0x0000F000 and 0x0000F040), the last written address prints the correct data, but the first written address prints garbage values. My question is, can I write and read a single page of data at one time? Is this true? #read part : #define dummy_ADD   0x0000F000 #define dummy_ADD1 0x0000F040 uint32_t dum,dum1; dum = IAP_ReadFlash(dummy_ADD); printf(dum) dum1 = IAP_ReadFlash(dummy_ADD1); printf(dum1) uint32_t IAP_ReadFlash(uint32_t FLASH_DATA_ADDRESS) { uint32_t *flashAddress = (uint32_t *)FLASH_DATA_ADDRESS; uint32_t data = *flashAddress; // Read the data from the flash memory address return data; } LPC800 Re: How To read the IAP Flash Memory read on LPC865 I want to configure USART0 with TX on P0_4 and RX on P0_1. Re: How To read the IAP Flash Memory read on LPC865 Hi, @Alice_Yang you are great! Thank you so much for your wonderful effort.   Alice, I am new to NXP controllers. Previously, I had been working on STM32 controllers, where I found it easy to configure the USART peripherals using the IOC configuration tool. We just had to select the UART number, choose synchronous or asynchronous mode, set the baud rate, and data length, and the code would be auto-generated. In a similar way, if I want to configure the UART in the LPC865, how should I go about it? Could you share a screenshot of the configuration process? Re: How To read the IAP Flash Memory read on LPC865 Hello @BerlinRaj  There are many errors in your code. So refer to your requirements, I create a project for you.  I have tested on my side, there is no issue when writing two pages and reading. From the result, we can see write to flash 78 and 190. They are read back correclty. I attach my project  for you.  Hope it helps. BR Alice Re: How To read the IAP Flash Memory read on LPC865 hii @Alice_Yang , i just try to write the code this console consider, i have to stored the VERSION and Temperature on the IAP FLASH Memory, and i displayed theVERSION and Temperature value with 1.8 inch TFT DISPLAY. uint32_t DEMO_IAP_FLASH_SECTOR = 63;//sector number uint32_t PAGE_SIZE_BYTES = 64; #define SECTOR_SIZE_BYTES (1024) static uint32_t s_IapFlashAddress = 64512;//=>1008(page_num)*64(page size) static uint32_t s_IapFlashAddress1 = 64576;//=>1009(page_num)*64(page size) int main() { TFT_Init(); home_screen(); while(1) { } } void home_screen() { static uint32_t s_PageBuf=78; static uint32_t s_PageBuf1=190; Erace(DEMO_IAP_FLASH_SECTOR); Writing_Data _one(s_PageBuf); Writing_data_two(s_PageBuf1); //read part uint32_t *read_ptr = (uint32_t *)(s_IapFlashAddress); uint32_t Version_value = *read_ptr; uint32_t *read_ptr1 = (uint32_t *)(s_IapFlashAddress1); uint32_t Temp_value = *read_ptr; print_tft(145, 2,Version_value , YELLOW_COLOR, BLUE_COLOR); print_tft(145, 20,Temp_value , YELLOW_COLOR, BLUE_COLOR); } void Write_data_one(uint32_t s_PageBuf) { IAP_FLASH_WRITE(DEMO_IAP_FLASH_SECTOR,s_IapFlashAddress,s_PageBuf,PAGE_SIZE_BYTES); } void Write_data_two(uint32_t s_PageBuf1) { IAP_FLASH_WRITE(DEMO_IAP_FLASH_SECTOR,s_IapFlashAddress1,s_PageBuf1,PAGE_SIZE_BYTES); } void IAP_FLASH_WRITE(uint32_t DEMO_IAP_FLASH_SECTOR,uint32_t FlashAddress,uint32_t s_PageBuf,uint32_t PAGE_SIZE_BYTES) { // IAP_PrepareSectorForWriteone(DEMO_IAP_FLASH_SECTOR, DEMO_IAP_FLASH_SECTOR); // IAP_EraseSectorone(DEMO_IAP_FLASH_SECTOR, DEMO_IAP_FLASH_SECTOR, SystemCoreClock); IAP_PrepareSectorForWriteone(DEMO_IAP_FLASH_SECTOR, DEMO_IAP_FLASH_SECTOR); IAP_CopyRamToFlashone(FlashAddress, &s_PageBuf,PAGE_SIZE_BYTES, SystemCoreClock); } void Erace(uint32_t DEMO_IAP_FLASH_SECTOR) { IAP_PrepareSectorForWriteone(DEMO_IAP_FLASH_SECTOR, DEMO_IAP_FLASH_SECTOR); IAP_EraseSectorone(DEMO_IAP_FLASH_SECTOR, DEMO_IAP_FLASH_SECTOR, SystemCoreClock); } void IAP_PrepareSectorForWriteone(uint32_t startSector, uint32_t endSector) { uint32_t command[5] = {0x00U}; uint32_t result[5] = {0x00U}; command[0] = (uint32_t)kIapCmd_IAP_PrepareSectorforWrite;//50u command[1] = startSector; command[2] = endSector; iap_entry(command, result); } void IAP_EraseSectorone(uint32_t startSector, uint32_t endSector, uint32_t systemCoreClock) { uint32_t command[5] = {0x00U}; uint32_t result[5] = {0x00U}; command[0] = (uint32_t)kIapCmd_IAP_EraseSector;//52u command[1] = startSector; command[2] = endSector; // command[3] = systemCoreClock / HZ_TO_KHZ_DIV; iap_entry(command, result); } void IAP_CopyRamToFlashone(uint32_t dstAddr, uint32_t *srcAddr, uint32_t numOfBytes, uint32_t systemCoreClock) { uint32_t command[5] = {0x00U}; uint32_t result[5] = {0x00U}; command[0] = (uint32_t)kIapCmd_IAP_CopyRamToFlash;//51u command[1] = dstAddr; command[2] = (uint32_t)srcAddr; command[3] = numOfBytes; // command[4] = systemCoreClock / HZ_TO_KHZ_DIV; iap_entry(command, result); } Whenever I write the above program, the FLASH MEMORY writes and reads the data properly. However, whenever I hide the #Erace(DEMO_IAP_FLASH_SECTOR); function, the first data is not read properly, but the second data is read well. Why? explain  these below two function if i hide why first data should not printed. IAP_PrepareSectorForWriteone(DEMO_IAP_FLASH_SECTOR, DEMO_IAP_FLASH_SECTOR); IAP_EraseSectorone(DEMO_IAP_FLASH_SECTOR, DEMO_IAP_FLASH_SECTOR, SystemCoreClock); Re: How To read the IAP Flash Memory read on LPC865 Yes, I have an issue with my code! I can't post the code because of my company's policy. Anyway, I will try to send my issue through a private ticket.. thank you @Alice_Yang  Re: How To read the IAP Flash Memory read on LPC865 Hello @BerlinRaj  Yes, you can write and read more data for a single page.  I recommend you debug step by step to check.  If you still have issue, and do not want to publish your code. You can also create a private ticket.  https://support.nxp.com/s/?language=en_US   BR Alice Re: How To read the IAP Flash Memory read on LPC865 hi, @Alice_Yang  thank you for your reply. i can write and read each data on a single page,can you tell me can i write and read more data for a single page? Re: How To read the IAP Flash Memory read on LPC865 Hello @BerlinRaj  For better help you, please share your project. I will help you check on my side. Thanks. BR Alice

Regarding the issue of mass production of safety tools HI： I see that there is an option for UART, but it seems to only support USB? Re: Regarding the issue of mass production of safety tools HI： I solved it according to your method. thank you Re: Regarding the issue of mass production of safety tools Hi, if you click on the "Failed" label in the 3rd column, it will open the LOG with details about the execution. This should help you understand, what failed. Re: Regarding the issue of mass production of safety tools I installed MCUXpresso Secure Provision tool v9.0.1 and it works fine, but after importing the manufacturing package, burning it with UART failed Re: Regarding the issue of mass production of safety tools Hi, UART should be supported for RT10xx processor, but unfortunately, there is regression problem for RT1xxx processors in manufacturing. We have reproduced the problem on our side, so we will fix this for next release. As a workaround, can you use MCUXpresso Secure Provisioning tool v9.0.1. There were no significant changes for RT10xx between v9.0.1 and v10, so this should work for you as well. We're sorry for an inconvenience.

S32K314 lwip tcp/ip multiple definition issue Hello, I am currently applying the lwIP TCP/IP stack to the S32K314 product and encountered a "multiple definition" error, so I am leaving a question. When I add the TCP/IP stack to the peripherals and build, the following error occurs: However, when I remove the multiple definition issue using linker options, the build succeeds as follows: Using linker options to bypass the multiple definition issue does not seem like a proper solution, so I want to address the root cause of the problem. Thank you. Re: S32K314 lwip tcp/ip multiple definition issue Thank you! Re: S32K314 lwip tcp/ip multiple definition issue Hi @malove  In the actual example, fsdata.c is not included for the compilation. only fs.c included. You can exclude the fsdata.c from build to avoid fsdata.o generation. which will help you to solve the problem without modifying the linker options. Thanks, Sathish. Re: S32K314 lwip tcp/ip multiple definition issue Thank you @PavelL  Re: S32K314 lwip tcp/ip multiple definition issue Hello @malove , I see your point now. Please check this: Re: linker error:multiple definition of `_start' - NXP Community Solved: Multiple definitions of functions 'isprintf' etc - NXP Community   Link Order: Using Multiple Definitions with ARM GNU Linker and Eclipse. Best regards, Pavel Re: S32K314 lwip tcp/ip multiple definition issue Hello @PavelL  What I want to clarify is that I am not trying to have two static IP addresses. Instead, I am trying to resolve the issue where certain elements in the fsdata.c source file are being defined multiple times. However, this file is not something I wrote myself; it is part of the TCP/IP stack that I am using as is. I am not sure how to modify or resolve this issue. Re: S32K314 lwip tcp/ip multiple definition issue Hello @malove , what is your goal? To have two static IP addresses? As far as I know, dual stack IPv4 and IPv6 should work on lwip. However, I did a web search but I didn't find a solution - all questions like this one mapping multiple * IP addresses to one Ethernet interface (LWIP) - NXP Community stayed unanswered or the solution didn't work. So, it looks like not feasible. As David already replied to here S32K3 Lwip iperf test issue - NXP Community, LWIP is an open source and we do not have resources to support. Best regards, Pavel

TJA1043 VBAT < Vuvd(VBAT)のウェイクアップ NXPメンバーの皆さん、こんにちは。 VBATステータスのウェイクアップについて質問があります。 VCC / VIOがVuvd>、次にVBAT 私たちは以下のように、この鳴き声で目を覚ますことができるのでしょうか? 1. ローカル ウェイク (ピン WAKE のロジック レベルが変化) 2. CABバスによるリモートウェイクアップ(ウェイクアップパターン) Meoth 2については、データシート7.2.2の「UVBATが設定されると、トランシーバーは電力を節約するためにスタンバイモードに入ろうとし、バスから切断されます(ゼロ負荷)」。つまり、CANバスは解除できるということですか?だから、CABバス経由でリモートウェイクアップすることはできませんよね?メオス1だけ大丈夫ですか? Re:TJA1043 VBAT<Vuvd(VBAT)のウェイクアップ こんにちはヨゼフ、 いつも迅速な返信とサポートをいただきありがとうございます。 よい一日を。 BRの 空 Re:TJA1043 VBAT<Vuvd(VBAT)のウェイクアップ こんにちはヨゼフ、 迅速な返信をありがとう、 つまり、VBAT

i.MX6ULL カスタム ボードで QSPI の eFuse をプログラムする方法は? 親愛なる専門家の皆様、 私は eFuse プログラミングの概念に慣れていないので、i.MX6ULL に基づくカスタム ボードでこれにアプローチする方法を理解したいと考えています。 以下の点についてご指導いただけますか? 1. eFuseプログラミングの理解: eFuseプログラミングとは正確には何であり、カスタムボードにどのように適用されるのでしょうか? その利点と用途は、特にi.MX6ULLのコンテキストでどのようなものですか? 2. QSPI用の電子ヒューズのプログラミング: カスタムi.MX6ULLボードでeFuseをプログラムするにはどうすればよいですか?従うべき特定のツール、手順、または方法はありますか? 参考資料、ガイド、または例が利用可能な場合は、それらを共有してください。 これは、eFuse プログラミング プロセスと i.MX6ULL への適用を理解するのに非常に役立ちます。 ご協力いただきありがとうございます。 よろしくお願いいたします ラビクマール Re: i.MX6ULL カスタム ボードで QSPI の eFuse をプログラムする方法は? こんにちはホル ヘカス 情報をありがとう。 カスタムボードのefuseプログラミングを成功裏に行いました。 よろしくお願いいたします ラビクマール

How to Program eFuses for QSPI in the i.MX6ULL Custom Board? Dear Experts, I'm new to the concept of eFuse programming & would like to understand how to approach this for a custom board based on the i.MX6ULL. Could you please provide guidance on the following: 1. Understanding eFuse Programming: What exactly is eFuse programming, & how does it apply to a custom board? What are its benefits and uses, specifically in the context of the i.MX6ULL? 2. Programming eFuses for QSPI: How can I program the eFuses on a custom i.MX6ULL board? Are there specific tools, steps, or methods I should follow? If there are any reference materials, guides, or examples available, please share them. This would greatly help in understanding the eFuse programming process and its application for the i.MX6ULL. Thank you for your assistance. Best regards, Ravikumar Re: How to Program eFuses for QSPI in the i.MX6ULL Custom Board? Hi JorgeCas Thanks for the information. I successfully done the efuse programming for our custom board. Best Regards, Ravikumar Re: How to Program eFuses for QSPI in the i.MX6ULL Custom Board? Hello, 1. The eFuses are a location to store different kinds of permanent configuration settings. This could, for example, be boot configuration, MAC address, secure boot settings, and so on. 2. Please take a look on the next guide to understand the process of read and write eFuses on your i.MX device. Program and access fuses | Embedded Artists Developer Site Best regards.

Can you provide the FS26 datasheet? Hi, Can you provide the FS26 datasheet?

S32K344 SAF SWT0 ISR triggerd after sCheck unistall ISR. I have try the S32 SAF V1.0.4 example code with RTD V4.0.0 1. The system enter ISR_SWT0 during sCheck xbic test (which the next test after SWT0 count test )(please refer screentshot1) 2. I have try to add breakpoint on SWT0 test.  all of count passed(screentshot2).  but scheck ISR triggered after SWT0 uninstall (screenshot3) May I ask if there any suggestion ? screenshot 1 screentshot2 screentshot3 Re: S32K344 SAF SWT0 ISR triggerd after sCheck unistall ISR. Hi RadoslavB My sales support team told me there is a bug of SWT0  since RTM 1.0.2  , and RTM 1.0.4 not fixed it. Thanks for you help. Re: S32K344 SAF SWT0 ISR triggerd after sCheck unistall ISR. Hi Sifan, I need to see your setup during debug session. Please contact me via NXP Sales Force system, so we can arrange the debug session. Kind Regards, Radoslav Re: S32K344 SAF SWT0 ISR triggerd after sCheck unistall ISR. Hi RadoslavB 1. Yes, demo example, not modifed on configuration.  startup & ld file has update to IAR format 2. I have try to add break pointer on SWT0_ISR first line,  but it reboot again & again which seems cause by SWT0 timeout because no ISR handler it  ( stop at breakpoint ) 3. The WEN are zero when hang on SWT0_ISR trap. 4. I have try to disable SWT0 check via EB,  and system won't enter SWT0 ISR. Re: S32K344 SAF SWT0 ISR triggerd after sCheck unistall ISR. Hi Sifan, if I understand correctly, you are executing SAF demo example, did you anyhow modify the code or configuration? On my side with the Demo example for S32K344 the SWT0 handler is triggered only once during the test as expected. I have all the time FRZ=0. Could you set breakpoint inside SWT0 handler, first intentional break stop should be during execution of sCheck_Swt_CounterTestRun() during the for loop. The SWT0 is enabled and disabled within Check_Swt_CounterBitCycle(), so beside that part the SWT IRQ should not be triggered. You can check if WEN bit is really zeroed or if there is still SWT0 interrupt pending bit set even after leaving SWT0 interrupt routine. Kind Regards, Radoslav Re: S32K344 SAF SWT0 ISR triggerd after sCheck unistall ISR. Hi RadoslavB 1. SWT0 is disabled before the test. also it is disabled when issue occured. 2. AIPS_SLOW_CLK frequency is 40M.  3. Yes, FRZ bit is set to 0 which as same as SAF Demo V1.0.4.  I have to try to run without any debugger or without any breakpoint, The system hang on SWT0 ISR "while trap", too. Re: S32K344 SAF SWT0 ISR triggerd after sCheck unistall ISR. Hi Sifan, sCheck does lat1ent faults check, as per ISO26262 it is sufficient to perform the test only once per drive cycle so no need to execute in both startup and runtime/shutdown. Before the test could you please check the SWT0 CR register if it is really disabled? Because SBAF bootrom enables SWT0 if it's enabled in Boot Configuration Word, bit APP_SWT_INIT.  SAF Demo should disable the SWT0 in startup, but please double check. Please check if the selected STM instance in sCheck Tresos is really same as it is configured in the RTD MCU driver And please check also AIPS_SLOW_CLK frequency in RTD MCU (CGM0_MUX0). The interrupt should be not triggered when disabling the SWT0 (if it was really disabled before the test). Edit: If you are using SWT0 setting from the SAF Demo startup, there is FZR bit se to 0 which means that the SWT0 is running even during debug break, so it might happen that if you have breakpoint before the sCheck restore function the timer elapses and trigger interrupt as soon as you continue debugging. For test purpose you can change the bit setting to 1 manually in the startup by modifying the value as depicted: Or use RTD WDG configuration with unchecked depicted option: But for production code you need to have FRZ bit se to 0, this is also checked by the sBoot module as this is recommended safety configuration by NXP.  Kind Regards, Radoslav Re: S32K344 SAF SWT0 ISR triggerd after sCheck unistall ISR. Hi RadoslavB 1. I'm executing the SWT0 test as Starup & Runtime 2.This issure not 100% occured for each time. so Startup may success ,  but for runtime always hang on ISR trap under continue test. 3.I'm not enable SWT0 . not configure it up & running.  Just test it on runtime continue test. I think it may cause by SWT disable ( when sCheck swt count test done) and SWT interrupt coming at same time,  and S32K has few time to uninstall ISR before it handle the interrupt. Re: S32K344 SAF SWT0 ISR triggerd after sCheck unistall ISR. Hello Sifan, please are you executing the SWT0 test as Starup or Runtime/Shutdown? In case of startup test, sCheck does restore SWT.CR register, so if SWT0 was disabled it should be disabled after the test as well and should not trigger the interrupt. In case you are executing the SWT0 test in runtime/shutdown it is expected that you have configured the SWT0 so it's up and running and therefore you should have implemented also your handler for refreshing the SWT0, from the screenshot I can see there is just the while trap instead. In this case, please update the interrupt handler and replace the while trap with routine refreshing the SWT0. Kind Regards, Radoslav

Changes to the p_flash of the S32K312 may cause the program to run erratically. Hi,nxp 1.By modifying the linker_flash_s32k312.ld file, the starting address of p_flash was changed from 0x00400000 to 0x00440200, resulting in the program malfunctioning, as shown in the attached image. The code is included in the attachment. 2.The expected outcome is that the program does not feed the watchdog and should restart from the beginning, rather than malfunctioning. That's all, thank you. Re: Changes to the p_flash of the S32K312 may cause the program to run erratically. Hi, Erase the entire chip and reload the program. Thanks Re: Changes to the p_flash of the S32K312 may cause the program to run erratically. I modified the original project by changing the starting address of int_pflash to 0x00500000 in the linker_flash_s32k312.ld file, but the program still runs incorrectly. Am I misunderstanding something, or is there another area that I haven't changed? 1)linker_flash_s32k312.ld->MEMORY 2)Schematic of program malfunction Re: Changes to the p_flash of the S32K312 may cause the program to run erratically. You can place it at 0x50_0000, which is a valid IVT address and it is in the next block, so it can be programmed by the bootloader in the 0x40_0000 block. Regarding the HSE_FW, please create a new thread. Thank you, BR, Daniel Re: Changes to the p_flash of the S32K312 may cause the program to run erratically. Hi,danielmartnek 1.I understand that this project should be flashed by a bootloader, right? Reply：Yes，There are other matters to pay attention to. 2.But if you flash the project directly (DM181S_S32K312_BOOT.elf), the SBAF then searches for the first valid IVT starting from the lowest address at 0x00400000. Reply：According to your intention, when debugging the app project online without the bootloader, the starting address of int_pflash still needs to be set to 0x00400000. 3.Additionally, if we enable the HSE firmware later on, how should we debug the app project that does not include the bootloader, and how do we allocate memory? Re: Changes to the p_flash of the S32K312 may cause the program to run erratically. Hi @victory, I understand that this project should be flashed by a bootloader, right? But if you flash the project directly (DM181S_S32K312_BOOT.elf), the SBAF then searches for the first valid IVT starting from the lowest address at 0x00400000. Regards, Daniel

LPC43S70 HSADC THRESHOLD_SEL=1(THR_A) And HSADC MATCH_VALUE=1 Hi Want to know the behavior HSADC_DESC_MATCH(0x0) and HSADC_DESC_THRESH_A below example, As my undestand,  HSADC_DESC_MATCH(0x0) will start simpling imediataly in this case. and HSADC_DESC_THRESH_A will start simpling at trigger threshold_A. In this case. which behavior will be higher priority? simpling  imediataly or wait unitl THRSH_A trigger? Chip_HSADC_SetupDescEntry(LPC_ADCHS, 0, 0, (HSADC_DESC_CH(1) | HSADC_DESC_BRANCH_NEXT | HSADC_DESC_MATCH(0x1) | HSADC_DESC_THRESH_A | HSADC_DESC_RESET_TIMER)); Re: LPC43S70 HSADC THRESHOLD_SEL=1(THR_A) And HSADC MATCH_VALUE=1 Hi xiangjun_rong thanks for your clarification. No more question. Re: LPC43S70 HSADC THRESHOLD_SEL=1(THR_A) And HSADC MATCH_VALUE=1 Hi, I suppose that you misunderstood the threshold_A, it is not a trigger source, it is a compare register, the ADC sample result is compared with the threshold_A register automatically, then update flag or fire interrupt which indicates that the analog signal is below a threshold or above a threshold. If you set HSADC_DESC_MATCH(0x10), the adchs module has an internal counter, the tick is the ADC clock, after hardware/software trigger, when the counter reaches 16 or 0x10, the ADC will convert, so the ADC conversion rate is Fadc/16.is you set  HSADC_DESC_MATCH(0x00), the ADC will generate a sample for each ADC clock cycle. Hope it can help you BR Xiangjun Rong Re: LPC43S70 HSADC THRESHOLD_SEL=1(THR_A) And HSADC MATCH_VALUE=1 Hi @xiangjun_rong  I don't quite understand. Here a case of  both  HSADC_DESC_THRESH_A and HSADC_DESC_MATCH(0x10) set to descriptor. then  while  threshold_A was trigger at hsadc timer 0x5, what is the timing clock of simpling? clock 0x5, 0x6 or 0x10? thanks Peter Re: LPC43S70 HSADC THRESHOLD_SEL=1(THR_A) And HSADC MATCH_VALUE=1 Hi, Q1)HSADC_DESC_MATCH(0x0)will start sampling immediately in this case. >>>>>The HSADC_DESC_MATCH(0x0) does not mean that the ADC converter starts-up immediately, the HSADC_DESC_MATCH(0xxx)  can control the ADC sampling time(ADC conversion rate). Setting HSADC_DESC_MATCH(0x00) means that the ADC can get one sample for each ADC clock. You can use software trigger to start ADC conversion by setting the SW_TRIGGER bit in Trigger register, pls refer to section 48.6.5 Trigger register. You can use hardware trigger to start ADC conversion by setting the ADCHS_TRIGGER_IN reg, pls refer to section 18.4.25 ADCHS trigger input multiplexer (ADCHS_TRIGGER_IN). Q2)and HSADC_DESC_THRESH_A will start simpling at trigger threshold_A. >>>>>DESCRIPTOR0x[THRESHOLD_SEL] selects the ADC result comparsion threshold register, it is NOT related to ADC starting. Hope it can help you BR XiangJun Rong

ls1046a kernel panic in xhci_irq. How do I parse NXP custom ISS field in esr_el1? I am trying to resolve a problem I'm having with a kernel panic on the LS1046a. Our custom board has a PCIe switch and 12 PCIe slots, with each PCIe slot containing an ASM3142 dual USB host controller. Intermittently, I receive kernel panics from routines related to the Linux XHCI implementation. These always seem to occur in 1 of 2 places. Either in the xhci_irq routine, or the xhci_handshake routine, but in either location, the panic always occurs on the instruction: dmb oshld This is a data memory barrier instruction, and the panic is caused by an SError (shown below).  I have no idea what could possibly cause an SError at this instruction, as there were no obvious illegal memory accesses prior to this. I am hoping the ESR_EL1 register may offer some clues, but I don't know how to parse it. According to the AArch64-Registers document on developer.arm.com, the ESR_EL1 register value 0xbf000002 can be parsed as: (bits 31:26) ESR_ESL1.EC = 0b101111   ==>  SErrror (bit 25)  ESR_ESL1.IL = 0b1 (32 bit instruction) (bit 24)  ESR_ESL1. = 0b1 (Implementation defined) Then, ISS bits 23:0 are an implementation defined value and I can't find any documentation that explains NXP's custom codes for the arm64 implementation in the LS1046a. Does anyone know how to interpret the ISS value 0x000002 on an SError exception for  the LS1046a? Or where I can download something that documents this? Importantly, does this offer any assistance at all in figuring out why a data memory barrier command would generate such an exception? Alternatively, does anyone have any clue at all what might be happening here?  I'm stumped on what could be the problem. Any assistance is appreciated. ------------------------------ [ 353.446849] SError Interrupt on CPU0, code 0x00000000bf000002 -- SError [ 353.446857] CPU: 0 PID: 185 Comm: kworker/0:3 Tainted: G O 6.1.41-devel #49 [ 353.446862] Hardware name: LS1046A Copier Board (DT) [ 353.446864] Workqueue: events xhci_handle_command_timeout [ 353.446873] pstate: 600000c5 (nZCv daIF -PAN -UAO -TCO -DIT -SSBS BTYPE=--) [ 353.446877] pc : xhci_handshake+0x68/0x110 [ 353.446884] lr : xhci_handshake+0x60/0x110 [ 353.446887] sp : ffffffc00adf3b40 [ 353.446889] x29: ffffffc00adf3b40 x28: 0000000000000000 x27: 0000000000000000 [ 353.446895] x26: 0000000000000000 x25: ffffffc00b379210 x24: 0000000000000000 [ 353.446899] x23: 0000000000000000 x22: 0000000000000008 x21: ffffffc00b360038 [ 353.446904] x20: 00000053693ee8a8 x19: 00000000004c4b40 x18: ffffffc00e463c88 [ 353.446909] x17: 0000000000000000 x16: 0000000000000000 x15: 0000000000000001 [ 353.446913] x14: 00000000000003bb x13: 0000000000000000 x12: 0000000000000000 [ 353.446917] x11: 0000000000000000 x10: 00000000000009e0 x9 : ffffffc00adf3d70 [ 353.446922] x8 : ffffff8801c7fb40 x7 : fefefefefefefeff x6 : 000000023074d81b [ 353.446926] x5 : 00ffffffffffffff x4 : 002e7ddb00000000 x3 : 0000000000000018 [ 353.446931] x2 : 0000000000000000 x1 : ffffffc00adf3b00 x0 : 0000000000000000 [ 353.446936] Kernel panic - not syncing: Asynchronous SError Interrupt [ 353.446938] CPU: 0 PID: 185 Comm: kworker/0:3 Tainted: G O 6.1.41-devel ##4 [ 353.446942] Hardware name: LS1046A Copier Board (DT) [ 353.446943] Workqueue: events xhci_handle_command_timeout [ 353.446947] Call trace: [ 353.446948] dump_backtrace+0xf0/0x130 [ 353.446955] show_stack+0x18/0x28 [ 353.446959] dump_stack_lvl+0x68/0x84 [ 353.446965] dump_stack+0x18/0x34 [ 353.446970] panic+0x1a0/0x998 [ 353.446974] nmi_panic+0xac/0xb0 [ 353.446979] arm64_serror_panic+0x64/0x78 [ 353.446982] do_serror+0x34/0x80 [ 353.446984] el1h_64_error_handler+0x34/0x50 [ 353.446987] el1h_64_error+0x64/0x68 [ 353.446990] xhci_handshake+0x68/0x110 [ 353.446994] xhci_handle_command_timeout+0x180/0x5c0 [ 353.446997] process_one_work+0x1fc/0x350 [ 353.447001] worker_thread+0x44/0x440 [ 353.447004] kthread+0xf8/0x110 [ 353.447007] ret_from_fork+0x10/0x20 Re: ls1046a kernel panic in xhci_irq. How do I parse NXP custom ISS field in esr_el1? Refer to the doc of "ARM Cortex-A72 MPCore Processor" for the interpretation of "ISS" filed in SError exception. ISS=2 means "Slave Error". It might related to a PCIe Error. Please comment out "ls_pcie_fix_error_response" in "drivers/pci/controller/dwc/pci-layerscape.c" and run the test again, then share the crash log Re: ls1046a kernel panic in xhci_irq. How do I parse NXP custom ISS field in esr_el1? Discussing with the AE team, will provide more update later.

S32G3 QSpi NorFlash Hi, I was looking at the AN13563 document and saw that"S32G does not have internal flash", but in "S32G3 Reference Manual" annexes "S32G3_memory_map.xlsx",I see that the address from 0x0-0x1fff ffff is the QSPI AHB Buffer So I've got a few questions for you. 1. Is this QSPI AHB Buffer referring to the external 64M size flash? 2. So how does this portion of memory migrate to ram after power up and how is it mapped in ram, also please let me know,or maybe we should go to that document. 3. When I need to perform an erasure and write action on an external flash, how do I go about it? Please guide me,because the flash in the previous project was inside the chip. MY environments: S32G-VNP-RBD3, S32DS 3.5  S32G-VNP-RDB3 S32G3  Re: S32G3 QSpi NorFlash Hello @jiajun , Thanks for contacting NXP support. Here is the information I was able to find for all your questions: Q1. Is this QSPI AHB Buffer referring to the external 64M size flash? A1. This memory region, from 0x00_0000_0000 to 0x00_1FFF_FFFF, is not the 64M flash directly, it is the AHB buffer, that works like an intermediary between the real flash and the processors reading it. There is a direct mapping between the addresses in ram buffer and the flash device. You can read more about this in the following sections of the reference manual [S32G3 Reference Manual, Rev. 4, 02/2024]: 39.5 Flash memory mapped AMBA bus 39.5.1 AHB bus access read considerations 39.5.5.2 AHB RX Data Buffer Register (ARDB0 - ARDB127)   39.6.2.8 Flash memory read Q2. So how does this portion of memory migrate to ram after power up and how is it mapped in ram, also please let me know, or maybe we should go to that document. A2. This migration of data occurs during the boot process, you can find more info about it in the following documents: Reference manual [S32G3 Reference Manual, Rev. 4, 02/2024]: 31.7 Boot flow 31.7.1 Boot flow phases 31.7.2 Boot flow diagram AN13456 - S32G3 Boot Process [Rev. 1, 02/2023] 6. BootROM 7.2. QSPI Boot You can also check the application note “AN13750 - Enabling Multicore App” [Rev. 0, 11/2022] for the RDB2, although it may no work exactly like that in the RDB3, it can give you a good idea on how the mapping of the ram and the flash is done. As you will see in that App note, the exact mapping will is related your linker file. Q3. When I need to perform an erasure and write action on an external flash, how do I go about it? A3. There are two ways to do it: one is with the flash tool, you can also check the steps in the “AN13750 - Enabling Multicore App”, in section “6. Deployment on s32g-vnp-rdb2”, step 8. If you want to do it during runtime you can check the RTD example “Qspi_Ip_Example_S32G399A_M7”, there you can see how to init, erase, write and read the QSPI flash. You can also go inside the functions definitions for more details about the registers usage. Please let us know if this information answers all your questions.