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"DEV_ROUTE 位" 是什么?   谁能告诉我 LPC546xx 用户手册中"DEV_ROUTE 位" 是什么意思? LPC54xxx USB Re: What is "DEV_ROUTE bit"? 你好@Lex2 感谢您的提问。 我认为这是一个错别字。 将 端口模式 寄存器(偏移量 0x50)中的 DEV_ENABLE 位设置为 0 ,以确保端口路由至 USB1 主机 控制器。 在 端口模式 寄存器(偏移量 0x50)中将 DEV_ENABLE 位设置为 1 ,以确保该端口路由到 USB1 设备控制器。   谢谢!   BR 爱丽丝 Re: What is "DEV_ROUTE bit"? 现在我明白了。感谢您的及时回复。
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2.5G SGMII connected to LX2162A Hi, we need to connect 2.5G SGMII interface to LX2162A processor. Is it possbile directly? In LX2162A reference manual is written that it supports only 1G SGMII however there is USXGMII interface with 2.5G bouadrate. Is it possible to connect 2.5G SGMII to 2.5G USXGMII directly? Kind regards! Re: 2.5G SGMII connected to LX2162A USXGMII and 2.5G SGMII are not directly compatible because they are designed for different Ethernet speeds and use different encoding schemes. To support 2.5Gbps device to LX2162A, an external PHY that converts 2.5G with the line-side interface to USXGMII is required. Thanks
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Facing issue while setting the RAM catalog key as key provision using key usages flag Hello NXP Team, I want to use the RAM catalog key (which is in plain) to provision the next import keys in RAM catalog. For this purpose, we add the key usages flag as shown below for the key. But the hse service gives HSE_SRV_RSP_INVALID_PARAM as response after adding the usages flag HSE_KF_USAGE_KEY_PROVISION. As per my understanding we can use RAM key if it is with usages flag HSE_SRV_RSP_INVALID_PARAM to provision the keys, then why this happened? Here is my service descriptor: - hseSrvResponse_t RetVal = HSE_SRV_RSP_GENERAL_ERROR; hseSrvDescriptor_t *pHseSrvDescriptor; uint8 u8MuChannel = Hse_Ip_GetFreeChannel(MU0_INSTANCE_U8);   keyInfo.keyBitLen = 128; keyInfo.keyType = HSE_KEY_TYPE_AES; keyInfo.keyFlags =  (HSE_KF_USAGE_KEY_PROVISION | HSE_KF_USAGE_DECRYPT | HSE_KF_USAGE_ENCRYPT ); //keyInfo.specific.aesBlockModeMask = HSE_KU_AES_BLOCK_MODE_ANY;   if(HSE_IP_INVALID_MU_CHANNEL_U8 != u8MuChannel) { pHseSrvDescriptor   = &Hse_aSrvDescriptor[u8MuChannel]; memset(pHseSrvDescriptor, 0, sizeof(hseSrvDescriptor_t));   pHseSrvDescriptor->srvId = HSE_SRV_ID_IMPORT_KEY; pHseSrvDescriptor->hseSrv.importKeyReq.keyLen[2] = 16; pHseSrvDescriptor->hseSrv.importKeyReq.pKey[2] = HSE_PTR_TO_HOST_ADDR(App_au8AesRamKey); pHseSrvDescriptor->hseSrv.importKeyReq.pKeyInfo= HSE_PTR_TO_HOST_ADDR(&keyInfo); pHseSrvDescriptor->hseSrv.importKeyReq.targetKeyHandle = GET_KEY_HANDLE(2,1,0); // Both the fields given below must be configured. pHseSrvDescriptor->hseSrv.importKeyReq.cipher.cipherKeyHandle= HSE_INVALID_KEY_HANDLE; pHseSrvDescriptor->hseSrv.importKeyReq.keyContainer.authKeyHandle= HSE_INVALID_KEY_HANDLE;         /* Build the request to be sent to Hse Ip layer */         HseIp_aRequest[u8MuChannel].eReqType   = HSE_IP_REQTYPE_SYNC;         HseIp_aRequest[u8MuChannel].u32Timeout = TIMEOUT_TICKS_U32;           /* Send the request to Hse Ip layer */         RetVal = Hse_Ip_ServiceRequest(MU0_INSTANCE_U8, u8MuChannel, &HseIp_aRequest[u8MuChannel], pHseSrvDescriptor); thanks... Re: Facing issue while setting the RAM catalog key as key provision using key usages flag Also, I have the following questions: 1. We know that while importing RAM/NVM keys, the owner of the provisioning key and the target key must be the same. So, can we use a provisioning key of a different type than the importing key type? For example, can we use an AES-type provisioning key to import an RSA key pair? 2. Can we import an encrypted key into the RAM/NVM catalog without using authentication if I have superuser rights? 3. For importing an authenticated key, we need to configure keyConatiner. I understand the data fields other than pKeyContainer. Since there is no standard structure that describes this field, could you please explain it with an example? Re: Facing issue while setting the RAM catalog key as key provision using key usages flag Any updates, Team Re: Facing issue while setting the RAM catalog key as key provision using key usages flag Hi @KaleRushikesh  Description of hseImportKeySrv_t in HSE Service API reference manual explicitly states: “The RAM provision keys can be imported only authenticated and can be used only to import RAM keys.” It also says: “The NVM provisioning keys can be installed/updated without authentication only having SuperUser rights; they can also be updated having User rights using the pre-installed provision keys.” So, SuperUser rights are not sufficient for RAM keys, the authentication is needed. We know that while importing RAM/NVM keys, the owner of the provisioning key and the target key must be the same. So, can we use a provisioning key of a different type than the importing key type? For example, can we use an AES-type provisioning key to import an RSA key pair? - That’s correct, you can use different key types – like mentioned AES provisioning key to import RSA key pair. Can we import an encrypted key into the RAM/NVM catalog without using authentication if I have superuser rights? - No. The HSE Service API reference manual explicitly says: “An encrypted key can be imported only authenticated.” This is valid for both User rights and SuperUser rights. For importing an authenticated key, we need to configure keyConatiner. I understand the data fields other than pKeyContainer. Since there is no standard structure that describes this field, could you please explain it with an example? - KeyContainer has no defined structure. But the idea is simple – it’s just an array somewhere in RAM. You are supposed to copy KeyInfo structure and the Key itself to the array. The size of array must be large enough for KeyInfo + Key. It can be bigger, it’s not limited. Then you need to generate a signature of the container/array. When importing authenticated key, fill structure hseImportKeySrv_t.keyContainer – there’s pointer to the container, length of the container, keyhandle for verification, pointer to signature… Pointer to the key and to the KeyInfo is configured in hseImportKeySrv_t. That’s the reason why no specific structure is needed for the container. HSE itself will check if the key and KeyInfo fall within the container. I have an example for update of ECC public key. This operation requires authentication. I used HSE framework from HSE DemoExamples SW package. If you are interested, please create a case here and I will share it: https://support.nxp.com/s/?language=en_US Write something like “Assign to Lukas Zadrapa” to the description. Regards, Lukas Re: Facing issue while setting the RAM catalog key as key provision using key usages flag Hi @KaleRushikesh  Sorry for delay, I'm quite overloaded now. I will try to check this later today or tomorrow. Thanks for patience.  Regards, Lukas Re: Facing issue while setting the RAM catalog key as key provision using key usages flag More quick questions- 1) As the authentication is mandatory for provision key to import in RAM catalog. So, when there is not any provision key present in catalog (means we are importing our first provision key), what are the fields for cipherKeyHandle, authKeyHandle. 2) I am struggling while calculating the M1, M2, M3, M4, M5 of SHE Key update protocol, do we have some standard tool to calculate these parameters?
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i.mx93 RT Core possible linker script issue Hi, I may have found an issue in the RT core linker script / memory layout used in the SDK, and I would like to check whether I am misunderstanding something or whether this is indeed a bug. Development environment VS Code 1.111.0 MCUXpresso for VS Code extension 26.2.46 SDK 25.09.00 In the linker scripts, the .data section is defined as a section that is copied from program memory to working memory at startup, which is fine and expected. In other words, .data is placed into RAM at runtime, while its initialization values are stored in program memory, using something like: .data : AT(__DATA_ROM) { ... } > m_data My concern is about what happens after that. As I understand GNU ld behavior, once an output section gets a load address via AT(...), the following allocatable sections in the same memory region may inherit a related LMA handling unless explicitly separated or marked otherwise. In this case, it appears that subsequent sections such as .bss, .heap, and .stack also end up reserving space in m_text / program memory, even though they should not require ROM initialization data. This seems problematic because: .bss should normally only occupy RAM and be zero-initialized by the startup code .heap and .stack should also only reserve RAM space none of these sections should consume additional space in program memory I can reproduce the behavior very easily with the standard Hello World example: Build the unmodified example and check the memory layout using the IMAGE INFO Add a large uninitialized global array, for example: /*! * @brief Task responsible for printing of "Hello world." message. */ volatile uint32_t test_array[10240]; /* 40KB array */ static void hello_task(void *pvParameters) {     (void)test_array[0]; /* prevent optimization */     for (;;)     {         PRINTF("Hello world.\r\n");         vTaskSuspend(NULL);     } } Rebuild and inspect the map file / memory usage It appears that increasing the size of this uninitialized object also increases the usage of m_text / program memory, as if .bss-type content were being accounted for there as well My expectation would be that only .data consumes ROM image space, while .bss, .heap, and .stack only consume RAM. Newer SDK does not solve this problem. Adding (NOLOAD) attributes to sections also does not solve the problem. Reordering the sections in m_data memory (for example moving the .bss before .data) resolves some of the issues but moving .heap and .stack introduces some other. So my question is: Am I missing something in how this linker script is intended to work, or is this a bug in the SDK linker layout? Re: i.mx93 RT Core possible linker script issue Hi @albi84  It appears to be a display issue with the "image info" tool. If you use readelf to compare the before and after versions, the .data section hasn't grown, while the .bss section has clearly expanded, but .bss is marked as NOBITS. The file offset "Off" is the same for all NOBITS segments. Original: Section Headers: [Nr] Name Type Addr Off Size ES Flg Lk Inf Al [ 0] NULL 00000000 000000 000000 00 0 0 0 [ 1] .interrupts PROGBITS 0ffe0000 001000 000474 00 A 0 0 4 [ 2] .resource_table PROGBITS 0ffe0478 004044 000000 00 W 0 0 1 [ 3] .text PROGBITS 0ffe0478 001478 0028b4 00 AX 0 0 4 [ 4] .ARM ARM_EXIDX 0ffe2d2c 003d2c 000008 00 AL 3 0 4 [ 5] .init_array INIT_ARRAY 0ffe2d34 003d34 000004 04 WA 0 0 4 [ 6] .fini_array FINI_ARRAY 0ffe2d38 003d38 000004 04 WA 0 0 4 [ 7] .interrupts_ram PROGBITS 20003000 004044 000000 00 W 0 0 1 [ 8] .data PROGBITS 20003000 004000 000044 00 WA 0 0 4 [ 9] .bss NOBITS 20003044 004044 00007c 00 WA 0 0 4 [10] .m33_suspend PROGBITS 20000000 004044 000000 00 W 0 0 1 [11] .heap NOBITS 200030c0 004044 000400 00 WA 0 0 1 [12] .stack NOBITS 200034c0 004044 000400 00 WA 0 0 1 [13] .ARM.attributes ARM_ATTRIBUTES 00000000 004044 000036 00 0 0 1 [14] .debug_line_str PROGBITS 00000000 00407a 000373 01 MS 0 0 1 [15] .debug_info PROGBITS 00000000 0043ed 00a36c 00 0 0 1 [16] .debug_abbrev PROGBITS 00000000 00e759 00146b 00 0 0 1 [17] .debug_aranges PROGBITS 00000000 00fbc8 000498 00 0 0 8 [18] .debug_rnglists PROGBITS 00000000 010060 000326 00 0 0 1 [19] .debug_line PROGBITS 00000000 010386 003f34 00 0 0 1 [20] .debug_str PROGBITS 00000000 0142ba 0076f4 01 MS 0 0 1 [21] .comment PROGBITS 00000000 01b9ae 000045 01 MS 0 0 1 [22] .debug_frame PROGBITS 00000000 01b9f4 001230 00 0 0 4 [23] .symtab SYMTAB 00000000 01cc24 002d00 10 24 267 4 [24] .strtab STRTAB 00000000 01f924 002949 00 0 0 1 [25] .shstrtab STRTAB 00000000 02226d 000115 00 0 0 1 Add array Section Headers: [Nr] Name Type Addr Off Size ES Flg Lk Inf Al [ 0] NULL 00000000 000000 000000 00 0 0 0 [ 1] .interrupts PROGBITS 0ffe0000 001000 000474 00 A 0 0 4 [ 2] .resource_table PROGBITS 0ffe0478 004044 000000 00 W 0 0 1 [ 3] .text PROGBITS 0ffe0478 001478 0028b4 00 AX 0 0 4 [ 4] .ARM ARM_EXIDX 0ffe2d2c 003d2c 000008 00 AL 3 0 4 [ 5] .init_array INIT_ARRAY 0ffe2d34 003d34 000004 04 WA 0 0 4 [ 6] .fini_array FINI_ARRAY 0ffe2d38 003d38 000004 04 WA 0 0 4 [ 7] .interrupts_ram PROGBITS 20003000 004044 000000 00 W 0 0 1 [ 8] .data PROGBITS 20003000 004000 000044 00 WA 0 0 4 [ 9] .bss NOBITS 20003044 004044 00a07c 00 WA 0 0 4 [10] .m33_suspend PROGBITS 20000000 004044 000000 00 W 0 0 1 [11] .heap NOBITS 2000d0c0 004044 000400 00 WA 0 0 1 [12] .stack NOBITS 2000d4c0 004044 000400 00 WA 0 0 1 [13] .ARM.attributes ARM_ATTRIBUTES 00000000 004044 000036 00 0 0 1 [14] .debug_line_str PROGBITS 00000000 00407a 000373 01 MS 0 0 1 [15] .debug_info PROGBITS 00000000 0043ed 00a763 00 0 0 1 [16] .debug_abbrev PROGBITS 00000000 00eb50 0014c6 00 0 0 1 [17] .debug_aranges PROGBITS 00000000 010018 000498 00 0 0 8 [18] .debug_rnglists PROGBITS 00000000 0104b0 000326 00 0 0 1 [19] .debug_line PROGBITS 00000000 0107d6 0040d5 00 0 0 1 [20] .debug_str PROGBITS 00000000 0148ab 0076ff 01 MS 0 0 1 [21] .comment PROGBITS 00000000 01bfaa 000045 01 MS 0 0 1 [22] .debug_frame PROGBITS 00000000 01bff0 001230 00 0 0 4 [23] .symtab SYMTAB 00000000 01d220 002d20 10 24 268 4 [24] .strtab STRTAB 00000000 01ff40 002954 00 0 0 1 [25] .shstrtab STRTAB 00000000 022894 000115 00 0 0 1 Best Regards, Zhiming Re: i.mx93 RT Core possible linker script issue One more thing: the RT core image is loaded via remoteproc on Linux.
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复制:迁移到 SW32K3_S32M27x_RTD_R21-11_7.0.1_P01 - Tresos 提出的意外警告 本帖复制自 此处 大家好, 将我们的项目从 MCAL SW32K3_S32M27x_RTD_R21-11_6.0.0 迁移到 SW32K3_S32M27x_RTD_R21-11_7.0.1_P01 后,我们在代码生成前后都看到了多个 Tresos 警告。 代码生成前(对许多参数重复): WARNING 26-03-17,15:38:12 (1621) 忽略 '/TS_T40D34M70I1R0/Mcu/McuModuleConfiguration' 的属性 'ORIGIN':未知属性 生成代码后: ASPath:/BaseNXP/BaseNXP/OsIfGeneral/OsIfOperatingSystemType'>ASPath:/BaseNXP/BaseNXP/OsIfGeneral/OsIfOperatingSystemType 与 content-type asc:2.0 不完全兼容。指向该选择的参考文献可能已损坏! ASPath:/Can_43_FLEXCAN/Can/CanConfigSet/Can_Network_CANNODE_0/CanRxFiFo'>ASPath:/Can_43_FLEXCAN/Can/CanConfigSet/Can_Network_CANNODE_0/CanRxFiFo 与 content-type asc:2.0 不完全兼容。指向该选择的参考文献可能已损坏! 代码生成似乎已成功完成,但我们在以前的 MCAL 中并未看到这些警告。请确认 7.0.1_P01 是否会出现这些问题?如果没有,请就如何解决这些问题(如所需的模板更新、模型迁移步骤或配置更改)提供指导。 使用的 Tresos 版本:29.0.0 谢谢, Arturo EB TRESOS 许可证 优先级:高 RTD 资料来源直接客户 Re: Copy: Migration to SW32K3_S32M27x_RTD_R21-11_7.0.1_P01 - Unexpected warnings raised by Tresos 我会在原主题上回复
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KEA128 CAN 我用KDS3.0生成库代码,生的CAN代码PE_ISR(CAN1_TxInterrupt), ErrorFlags = MSCAN_PDD_GetRxStatusInterruptFlags(MSCAN_BASE_PTR); /* Read the status register */ if (     ((ErrorFlags & MSCAN_PDD_RX_BUS_OFF) != MSCAN_PDD_RX_BUS_OFF)||         ((ErrorFlags & MSCAN_PDD_TX_BUS_OFF) != MSCAN_PDD_TX_BUS_OFF)   )   { /* Is bus-off detected? */         DeviceDataPrv->Stats.BusOffs++;  /* Increase BusOffs interrupt counter */       CAN1_OnBusOff(DeviceDataPrv->UserData); /* Invoke user event */     } MSCAN_PDD_RX_BUS_OFF为0x30,查看手册中 MSCAN_CANRFLG ,bit5-4中为0b11时总线离线,但代码中判断不为0b11则为离线。 LDD_TError CAN1_GetError(LDD_TDeviceData *DeviceDataPtr, LDD_CAN_TErrorMask *ErrorMaskPtr) { CAN1_TDeviceData *DeviceDataPrv = (CAN1_TDeviceData *)DeviceDataPtr; /* {Default RTOS Adapter} Critical section begin, general PE function is used */ EnterCritical(); *ErrorMaskPtr = DeviceDataPrv->ErrorMask; /* Return last value of error mask */ DeviceDataPrv->ErrorMask = 0x00U; /* {Default RTOS Adapter} Critical section end, general PE function is used */ ExitCritical(); return ERR_OK; } DeviceDataPrv->ErrorMask = 0x00U;,查看代码ErrorMask 为内存中数据,为什么ErrorMask 清零后总线可以立刻恢复。 Kinetis EA Series MCUs Re: KEA128 CAN HI@lzhjxgz 感谢您的耐心等待。 1.Regarding "MSCAN_PDD_RX_BUS_OFF for 0x30,查看手册中 MSCAN_CANRFLG ,bit5-4中为0b11时总线离线,但代码中判断不为0b11则为离线"、 ->> 我同意你的观点--代码中的总线断开检测逻辑确实与硬件手册中的描述相反。 请手动输入代码并检查其是否正常工作。我也会向内部团队报告这个问题。 2。对于第二个问题,我认为清除 ErrorMask 和恢复 CAN 总线之间没有任何关系。总线断开恢复完全由硬件机制处理。 谢谢! BR 爱丽丝
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i.MX8QX6 – UUU flashing stalls with libusb error (possible LPDDR4 row address mismatch) Hello, We are currently working with the following configuration: SoC: NXP i.MX8QX6 (MIMX8QX6AVLFZAC) LPDDR4: Micron MT53E768M32D2ZW-046 (AIT:C) Yocto Release: walnascar-6.12.34-2.1.0 We are attempting to flash the imx-boot-imx8qxp-mek-sd.bin-flash_spl image using the Universal Update Utility. During the flashing process, the tool gets stuck and eventually reports LIBUSB_ERROR_NO_DEVICE, preventing the flashing process from completing. Troubleshooting performed To isolate the issue, we attempted the following: Tested with older imx-boot binaries from previous releases: LF_v6.6.52-2.2.2_images_IMX8QXPC0MEK LF_v5.15.32-2.0.0_images_IMX8QXPC0MEK Used the latest version of the UUU tool Repeated the flashing process multiple times However, the behavior remains the same. Suspected cause After reviewing the memory device specification, our internal investigation suggests there may be a DDR address row configuration mismatch between the SoC DDR controller configuration and the actual LPDDR4 device. According to the Micron datasheet, the memory device uses row address R[16:0] (17 rows). However, based on the SoC documentation, the DDR controller appears to support a maximum of 16 row address lines (R0–R15). Because of this difference, we suspect there may be a mismatch between the DDR controller configuration and the memory device addressing scheme. Questions Could a row address mismatch in the LPDDR4 configuration cause the UUU flashing process to stall with a LIBUSB_ERROR_NO_DEVICE during early boot? If this is a possible cause, what would be the recommended way to correctly configure the DDR parameters for this LPDDR4 device on the i.MX8QX6? Should the configuration be generated using the DDR Tool / RPA tool provided by NXP, or are there reference configurations available for this specific memory device? Any guidance or recommendations would be greatly appreciated. Thank you. Re: i.MX8QX6 – UUU flashing stalls with libusb error (possible LPDDR4 row address mismatch) Hi @Yogesh_    I tested in my imx8qxp board. There is no problem occurred. I use the below command flash the flash.bin file. uuu -b emmc .\imx-boot-imx8qxpc0mek-sd.bin-flash   Answer your questions: Q1 & Q2 : This will not cause this problem Q3: you should configure the right parameters for your DRAM. Then re-compile the new flash.bin file. But as you said. your DRAM rows number is 17, But the maximum row size supported by imx8qxp is 16. So please change another DRAM with 16 rows. This means, in order to support the maximum 4GB (32Gb) LPDDR4 density, the configuration must be 16-row, 2 rank B.R Re: i.MX8QX6 – UUU flashing stalls with libusb error (possible LPDDR4 row address mismatch) Could you suggest any alternative solution to resolve the UUU tool hanging/stuck issue? I have already tried both older releases and the latest version of the UUU tool, but I am still encountering the same error. Re: i.MX8QX6 – UUU flashing stalls with libusb error (possible LPDDR4 row address mismatch) Thank you for your response. I have attached the logs for both the Yocto-generated imx-boot-imx8qxp-mek-sd.bin-flash_spl and the flash.bin image. The flash.bin was configured using the RPA tool and built with the SCFW Porting Kit, and it is booting successfully. Re: i.MX8QX6 – UUU flashing stalls with libusb error (possible LPDDR4 row address mismatch) Hi @Yogesh_  Do not use the below command sudo uuu -v -b emmc_all imx-boot-imx8qxp-mek-sd.bin-flash_spl Use below code: uuu -b emmc imx-boot-imx8qxp-mek-sd.bin-flash_spl 1. Try to run the uuu tool under Windows OS 2. Share the result about below command: uuu -lsusb  B.R Re: i.MX8QX6 – UUU flashing stalls with libusb error (possible LPDDR4 row address mismatch) Hi @Yogesh_  What is the result after running the following command? uuu -lsusb B.R 
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S32DS 2018 ライセンス期限 こんにちは: S32 Design Studio for ARM v2018 R1 ライセンス过期,麻烦帮繁忙处理一下,谢谢! Re: S32DS 2018 license 过期 こんにちは、 S32DS ライセンスが延長されました。
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