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MPC5777M ESR0 functional reset coverage Hello, I have a question about the MPC5777M reset behavior via the external ESR0 signal. My understanding is that an ESR0 signal triggers a functional reset, but not all modules are reset in this process. Based on Table 8-1, "Module Status During Reset Phases," modules like FCCU and PIT_1 are listed as not being reset. Can you confirm if this table is exhaustive? Are there additional modules or parts of the device that are not reset during a functional reset? Also, is it possible to manually reset these modules, such as by using MC_RGM? Lastly, is there a way to configure ESR0 so it initiates a destructive reset instead of just a functional reset? Thanks in advance for your insights. Re: MPC5777M ESR0 functional reset coverage Q: Based on Table 8-1, "Module Status During Reset Phases," modules like FCCU and PIT_1 are listed as not being reset. Can you confirm if this table is exhaustive? A: Apparently yes, I have not indication it should not be. Q: Are there additional modules or parts of the device that are not reset during a functional reset? A: I don’t think so. Q: Also, is it possible to manually reset these modules, such as by using MC_RGM? A: You may use mode entry module and trigger SW functional or SW destructive reset. Q: Lastly, is there a way to configure ESR0 so it initiates a destructive reset instead of just a functional reset? A: No, but for this purpose there is a PORST pin. Re: MPC5777M ESR0 functional reset coverage Hello David, Thank you for your response. I have submitted a follow-up question on the NXP support page. Best regards 

i.MX95: 2ch LVDS output Hello,  https://community.nxp.com/t5/i-MX-Processors/iMX95-Two-video-inputs/m-p/2330401#M244435 This is a related question. We are currently proposing an i.MX95 project to a client, and similar to danielsan-77’s post, it requires two MIPI inputs and two LVDS outputs. Regarding the MIPI inputs, we believe there will be no issues since we are currently able to handle input from eight cameras using MIPI-CSI2 and MIPI-DSI-CSI2 ports. My concern is the two-channel LVDS output. In our case, we will connect the following two independent LCDs via a TI FPDLink3 Serializer: LVDS1) 800x480@60Hz RGB LCD, LVDS2) 1280x720@60Hz RGB LCD Question 1) The referenced thread mentioned that dual LVDS outputs are possible, and my understanding is that the pixel resolution, size, and pixel clock can be set independently. Is this correct? Question 2) I’ve been reviewing the reference manual, but I can't find out. Which registers control the clock, Hsize, Vsize settings for LVDS1 and LVDS2? Question 3) I don’t think 2-channel LVDS is implemented in the BSP. Can NXP Engineering Services (Paid service) support this? Best Regards, Kanou Re: i.MX95: 2ch LVDS output Hi Joanxie,  Thank you for your prompt response. You mentioned that it is currently possible to output an independent LVDS signal, but I believe this may actually be difficult. The reasons are as follows: The two LVDS displays must be different in resolution and frequency, But I’m guessing that they cannot be independent in any case.  From the display domain architec The i.MX95 has one LVDS interface block. That interface supports:  - Single-channel LVDS  - Dual-channel LVDS (odd/even pixel split)  From the manual - 165 MHz pixel clock per LVDS channel - 330 MHz pixel clock in dual-channel mode A single Display Controller and single LVDS Interface means the two channels share: - the same pixel clock - the same timing generator - the same frame timing (HSYNC/VSYNC) So both channels are driven by the same display pipeline timing. Also the single Pixel Interleaver and Pixel Mapper hints that no independent LVDS displays are possible. Split mode and other modes that play with Odd/Even bits should be possible. Note that the link in Q3 appears to be a tds configuration for splitting a single video into two files (odd and even). Is this understanding correct? Best Regards, kanou Re: i.MX95: 2ch LVDS output Question 1) The referenced thread mentioned that dual LVDS outputs are possible, and my understanding is that the pixel resolution, size, and pixel clock can be set independently. Is this correct? > this is imx95 lvds performance:165MHz Single 330MHz Dual Question 2) I’ve been reviewing the reference manual, but I can't find out. Which registers control the clock, Hsize, Vsize settings for LVDS1 and LVDS2? >if customer use linux as OS, they don't need change the register to control this, change the ldb clock in the dts Question 3) I don’t think 2-channel LVDS is implemented in the BSP. Can NXP Engineering Services (Paid service) support this? > current bsp has dts file for dual lvds channel support, you can refer to this https://github.com/nxp-imx/linux-imx/blob/lf-6.12.y/arch/arm64/boot/dts/freescale/imx95-19x19-evk-it6263-lvds-dual.dtso Re: i.MX95: 2ch LVDS output Thank you for your response. In other words, since there is only one PLL, LVDS1 and LVDS2 must share the same clock. Therefore, I understand that while this would work with the same panel, the following configuration is not feasible: LVDS1) 800x480@60Hz RGB LCD, LVDS2) 1280x720@60Hz RGB LCD BR, Kanou Re: i.MX95: 2ch LVDS output yes correct, The 2 LVDS ports need output same LVDS clock in frequency because only one LDB pll Re: i.MX95: 2ch LVDS output yes, The two LVDS ports are same resolution and timing in hardware

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Built the images to be signed I have enabled the configuration of CONFIG_IMX_HAB=y in the following files of imx8mp under the directory ./vendor/nxp-opensource/uboot-imx/configs/ imx8mp_iwg40m_4gb_android_defconfig imx8mp_iwg40m_4gb_android_dual_defconfig imx8mp_iwg40m_4gb_android_uuu_defconfig imx8mp_iwg40m_osm_4gb_android_defconfig imx8mp_iwg40m_osm_4gb_android_uuu_defconfig imx8mp_iwg40m_0sm_4gb_usbotg_android_defconfig Then again built the image source build/envsetup.sh lunch iwg40m_8mp-trunk_staging-userdebug ./imx-make.sh -j4 2>&1 | tee build-log.txt 3. Generation of Keys and Certificates Download Code Signing Tool (CST) from NXP official website. Decompress the package with the following command: tar zxvf cst-3.1.0.tgz Generate the HABv4 PKI tree. After the tool package is decompressed, enter the directory of ${CST}/keys/, and execute the following command: ./hab4_pki_tree.sh   Then entered some parameters based on the output. Do you want to use an existing CA key (y/n)?: n Do you want to use Elliptic Curve Cryptography (y/n)?: n Enter key length in bits for PKI tree: 2048 Enter PKI tree duration (years): 5 How many Super Root Keys should be generated? 4 Do you want the SRK certificates to have the CA flag set? (y/n)?: y Generate AHAB SRK tables and eFuse hash. Enter the directory of ${CST}/crts/, and execute the following command: ../linux64/bin/srktool -h 4 -t SRK_1_2_3_4_table.bin -e \ SRK_1_2_3_4_fuse.bin -d sha256 -c \ SRK1_sha256_2048_65537_v3_ca_crt.pem,\ SRK2_sha256_2048_65537_v3_ca_crt.pem,\ SRK3_sha256_2048_65537_v3_ca_crt.pem,\ SRK4_sha256_2048_65537_v3_ca_crt.pem After the preceding commands are executed successfully. The SRK table and its SHA256 value are generated and saved respectively in two files under ${CST}/crts/. f. Dump the SRK hash value. Change directory to crts/ in Code Signing Tool (CST). Execute the following command to dump the SRK hash value: hexdump -e '/4 "0x"' -e '/4 "%X""\n"' SRK_1_2_3_4_fuse.bin 4. Configure csf files with UUU defconfig and signing Copy a template of csf files from the directory android_build/vendor/nxp-opensource/uboot-imx/doc/imx/habv4/csf_examples/mx8m/ to the directory /cst/linux64/bin/ cp~/android_build/vendor/nxpopensource/ubootimx/doc/imx/habv4/csf_examples/mx8m/csf_spl.txt /cst-3.4.1/linux64/bin cp~/android_build/vendor/nxpopensource/ubootimx/doc/imx/habv4/csf_examples/mx8m/csf_fit.txt /cst-3.4.1/linux64/bin cp~/android_build/vendor/nxpopensource/ubootimx/doc/imx/habv4/csf_examples/mx8m/csf_fit_fdt.txt /cst-3.4.1/linux64/bin Copy the image files to be signed for single boot: cp ~/android_build/out/target/product/imx8mp_iwg40m/u-boot-imx8mp-iwg40m-4gb.imx /cst-3.4.1/linux64/bin cp ~/android_build/out/target/product/imx8mp_iwg40m/u-boot-imx8mp-iwg40m-4gb-uuu.imx /cst-3.4.1/linux64/bin To configure each CSFs file for its offset and Blocks: They can be obtained from the build log - make_android.txt and configure each of the csf text files from the Block addresses obtained from the build_log.txt Csf_spl_uuu.txt Csf_fit_uuu.txt Csf_fit_fdt.txt signing spl and fit: ./bin/cst -i csf_spl_uuu.txt -o csf_spl_uuu.bin ./bin/cst -i csf_fit_uuu.txt -o csf_fit_uuu.bin dd if=csf_spl_uuu.bin of=u-boot-imx8mp-iwg40m-4gb.imx seek=$ ((0x2de00)) bs=1 conv=notrunc dd if=csf_fit_uuu.bin of=u-boot-imx8mp-iwg40m-4gb-uuu.imx seek=$((0x58c20)) bs=1 conv=notrunc signing fit_fdt ./bin/cst -i csf_fit_fdt_uuu.txt -o csf_fit_fdt_uuu.bin dd if=csf_fit_fdt_uuu.bin of=u-boot-imx8mp-iwg40m-4gb-uuu.imx seek=$((0x5ac20)) bs=1 conv=notrunc Copying the image: After the image is signed with the keys in /cst/release/linux64/bin then again copy the image back to the flashing directory of /android_build. Flashing the device: 5. HAB events test and close device After flashing the board, the HAB event is displayed as: iWave-G40 >hab_status Secure boot disabled HAB Configuration: 0xf0, HAB State: 0x66 --------- HAB Event 1 ----------------- event data:         0xdb 0x00 0x14 0x45 0x33 0x0c 0xa0 0x00         0x00 0x00 0x00 0x00 0x40 0x1f 0xbd 0xc0         0x00 0x00 0x00 0x20 STS = HAB_FAILURE (0x33) RSN = HAB_INV_ASSERTION (0x0C) CTX = HAB_CTX_ASSERT (0xA0) ENG = HAB_ENG_ANY (0x00) --------- HAB Event 2 ----------------- event data:   0xdb 0x00 0x14 0x45 0x33 0x0c 0xa0 0x0    0x00 0x00 0x00 0x00 0x40 0x1f 0xad 0xc0         0x00 0x00 0x00 0x04 STS = HAB_FAILURE (0x33) RSN = HAB_INV_ASSERTION (0x0C) CTX = HAB_CTX_ASSERT (0xA0) ENG = HAB_ENG_ANY (0x00) --------- HAB Event 3 ----------------- event data:         0xdb 0x00 0x2c 0x45 0x33 0x18 0xc0 0x00         0xca 0x00 0x24 0x00 0x02 0xc5 0x1d 0x00         0x00 0x00 0x0d 0x4c 0x40 0x20 0x00 0x00         0x00 0x13 0xe0 0x10 0x40 0x33 0xe0 0x10         0x00 0x01 0x01 0x30 0x00 0x97 0x00 0x00         0x00 0x00 0xaa 0x70 STS = HAB_FAILURE (0x33) RSN = HAB_INV_SIGNATURE (0x18) CTX = HAB_CTX_COMMAND (0xC0) ENG = HAB_ENG_ANY (0x00) --------- HAB Event 4 ----------------- event data:         0xdb 0x00 0x2c 0x45 0x33 0x18 0xc0 0x00         0xca 0x00 0x24 0x00 0x02 0xc5 0x1d 0x00         0x00 0x00 0x0d 0x4c 0x40 0x20 0x00 0x00         0x00 0x13 0xe0 0x10 0x40 0x33 0xe0 0x10         0x00 0x01 0x01 0x30 0x00 0x97 0x00 0x00         0x00 0x00 0xaa 0x70 STS = HAB_FAILURE (0x33) RSN = HAB_INV_SIGNATURE (0x18) CTX = HAB_CTX_COMMAND (0xC0) ENG = HAB_ENG_ANY (0x00) Re: Secure Boot on i.MX8M Plus 4Gb board failed to get correct HAB Status Hello, The detailed description of the event data is located in HAB4_API.pdf, please check in the link below: https://community.nxp.com/pwmxy87654/attachments/pwmxy87654/MCX/481/1/HAB4_API.pdf Re: Secure Boot on i.MX8M Plus 4Gb board failed to get correct HAB Status i am using i.MX 8M Plus SMARC board from iWave. I have question that there some different steps or some modification Re: Secure Boot on i.MX8M Plus 4Gb board failed to get correct HAB Status It seems that you haven't signed the part of "u-boot-imx8mp-iwg40m-4gb.imx" @Suraj_Roy  Re: Secure Boot on i.MX8M Plus 4Gb board failed to get correct HAB Status i have the signed using Steps for Single Secure Boot for Android BSP and Android Security Guide for Keys generation document

Request for S32DS for Power v1.2 installation package Hello everyone, I'm currently working on an MPC5744 automotive ECU development project and need to use S32DS for Power v1.2 for Simulink code generation. However, I can't find the download link for this specific version (v1.2) on the official NXP website or other channels. Could anyone help with a valid download link for S32DS for Power v1.2.Thanks a lot for your help.🥺 Re: Request for S32DS for Power v1.2 installation package Hi @demonster  Could you please verify whether you are able to download the IDE from the following link? S32 Design Studio for Power v1.2 - Windows/Linux BR, VaneB Re: Request for S32DS for Power v1.2 installation package Hi @VaneB  I would like to download the S32 Design Studio for Power V1.2 too, but when I go to the link you provided above, it says "Our records indicate that you have previously requested an Evaluation version for this product. If you would like to purchase the full product please visit us at NXP or contact your sales representative." I purchased the MPC5775B-EVB a year ago, but didn't get the time to use it for my experiment until now. How can i extend the evaluation period?  Thanks! Re: Request for S32DS for Power v1.2 installation package Hi @flyingbear  Please try the steps in the link below: How to extend my CodeWarrior Evaluation Software If this does not fix it, please create a support ticket using your company email, and the team in charge will help you out from there. Re: Request for S32DS for Power v1.2 installation package Thank you @VaneB  I got it downloaded by following the instructions. 

i.MX8M Plus 4Gb 板上的安全启动无法获得正确的 HAB 状态 我已经按照了 PDF " Android 单一安全启动步骤 电路板支持包 " 和 Android 网络安全密钥生成指南中的确切步骤，但是刷新之后我无法实现安全启动，因为 HAB 状态不正确，需要做些什么才能启用安全启动过程？ 这些都是我为进行安全启动所遵循的所有步骤，还附上了屏幕截图： 1. 在启用 IMX_HAB 的情况下版本镜像 准备好版本环境并在 /android_build 目录中运行以下命令 导出 aarch32_gcc_cross_compile=/opt/arm-GNU-Toolchain-12.3.rel1-x86_64-arm-none-eabi/bin/arm-none-none-eabi/bin/arm-None-EABI- export aarch64_gcc_cross_compile=/opt/arm-GNU-GNU-Toolchain-12.3.rel1-x86_64-aarch64-none-linux-GNU-bin/aarch64-none-linux-GNU- export CLANG_PATH=/opt/prebuilt-android-clang export LIBCLANG_PATH=/opt/prebuilt-android-clang/clang-r510928/lib 导出路径=/opt/prebuilt-Android-Kernel-版本-tools/Linux-x86/bin：$PATH export PATH=/opt/prebuilt-android-rust/linux-x86/1.73.0b/bin:$PATH export PATH=/opt/prebuilt-android-clang-tools/linux-x86/bin:$PATH 2。版本了要签名的图像 我在 ./vendor/nxp-opensource/uboot-imx/configs/ 目录下的 imx8mp 下列文件中启用了 CONFIG_IMX_HAB=y 的配置。 imx8mp_iwg40m_4gb_android_defconfig imx8mp_iwg40m_4GB_android_dual_defconfig imx8mp_iwg40m_4gb_android_uuu_defconfig imx8mp_iwg40m_osm_4gb_android_defconfig imx8mp_iwg40m_osm_4gb_android_uuu_defconfig imx8mp_iwg40m_0sm_4gb_usbotg_android_defconfig 然后又制作了镜像版本 source 版本/envsetup.sh 午餐 iwg40m_8mp-trunk_staging-userdebug 。/imx-make.sh-j4 2 > & 1 | tee build-log.txt 3.生成密钥和证书 从恩智浦官方网站下载代码签名工具 (CST)。使用以下命令解压缩软件包：tar zxvf cst-3.1.0.tgz 生成 HABv4 PKI 树。工具包解压缩后，进入 ${CST} /keys/ 目录，执行以下命令：。/hab4_pki_tree.sh 然后根据输出结果输入一些参数。 你想使用现有的 CA 密钥吗（是/n）？: n 你想使用椭圆曲线密码学 (y/n) 吗？: n 输入 PKI 树的密钥长度（以位为单位）：2048 输入 PKI 树的持续时间（年）：5 应该生成 多少超级根密钥？4 您希望 SRK 证书设置 CA 标志吗？(y/n)? 生成 AHAB SRK 表和 eFuse 哈希值。进入${CST}/crts/目录，执行以下命令： ../linux64/bin/srktool -h 4 -t SRK_1_2_3_4_table.bin -e\ SRK_1_2_3_4_fuse.bin -d sha256 -c \ SRK1_sha256_2048_65537_v3_ca_crt.pem,\SRK2_sha256_2048_65537_v3_ca_crt.pem,\ SRK3_sha256_2048_65537_v3_ca_crt.pem,\ SRK4_sha256_2048_65537_v3_ca_crt.pem 成功执行上述命令后SRK 表及其 SHA256 值分别生成并保存在${CST}/crts/ 下的两个文件中。 f.转存 SRK 哈希值。在代码签名工具 (CST) 中将目录更改为 crts/。执行以下命令转储 SRK 哈希值： hexdump -e '/4"0x"' -e '/4"% X"" \n"' SRK_1_2_3_4_fuse.bin 4.使用 UUU defconfig 配置 csf 文件并签名 将目录 android_build/vendor/nxp-opensource/uboot-imx/doc/imx/habv4/csf_examples/mx8m/ 中的 csf 文件模板复制到目录 /cst/linux64/bin/ cp~/android_build/vendor/nxpopensource/ubootimx/doc/imx/habv4/csf_examples/mx8m/csf_spl.txt /cst-3.4.1/linux64/bin cp~/android_build/vendor/nxpopensource/ubootimx/doc/imx/habv4/csf_examples/mx8m/csf_fit.txt /cst-3.4.1/linux64/bin cp~/android_build/vendor/nxpopensource/ubootimx/doc/imx/habv4/csf_examples/mx8m/csf_fit_fdt.txt /cst-3.4.1/linux64/bin 复制要签名的镜像文件进行单次启动： cp ~/android_build/out/target/product/imx8mp_iwg40m/u-boot-imx8mp-iwg8mp-iwg8mp-iwg.imx /cst-3.4.1/linux64/bin cp ~/android_build/out/target/product/imx8mp_iwg40m/u-boot-imx8mp-iwg40m/u-boot-imx8mp-iwg40m/u-boot-imx8mp-iwg40m/m-4gb-uuu.imx /cst-3.4.1/linux64/bin 要配置每个 CSF 文件的偏移量和区块：它们可以从版本日志-make_android.txt 中获取，并从从 build_log.txt 获得的区块地址配置每个 csf 文本文件 Csf_spl_uuu.txt Csf_fit_uuu.txt Csf_fit_fdt.txt 签名芨芨草和合身： ./bin/cst -i csf_spl_uuu.txt -o csf_spl_uuu.bin ./bin/cst-i csf_fit_uuu.txt -o csf_fit_uuu.bin dd if=csf_spl_uuu.bin of=u-boot-imx8mp-iwg40m-4gb.imx seek=$ ((0x2de00)) bs=1 conv=notrunc dd if=csf_fit_uuu.bin of=uu-boot-imx8mp-iwg40m-4gb-uuu.imx seek=$ (0x58c20)) bs=1 conv=notrunc 签名 fit_fdt。 /bin/cst-i csf_fit_fdt_uuu.txt -o csf_fit_fdt_uuu.bin dd if=csf_fit_fdt_uuu.bin of=u-boot-imx8mp-iwg40m-4gb-uuu.imx seek=$ ((0x5ac20)) bs=1 conv=notrunc 复制镜像： 使用 /cst/版本/linux64/bin 中的密钥对镜像进行签名 后，再次将镜像复制回 /android_build 的闪存目录中。 刷新设备： 5。HAB 事件测试并关闭设备 刷新板 后，HAB 事件显示为： iWAVE-G40 > hab_status 已禁用 安全启动 HA B 配置：0xf0，HAB 状态：0x66 --------- HAB 事件 1 ----------------- 事件数据： 0xdb 0x00 0x14 0x45 0x33 0x0c 0xa0 0x00 0x00 0x00 0x00 0x40 0x1f 0xbd 0xc0 0x00 0x00 0x00 0x20 STS = HAB_FAILURE (0x33) RSN = HAB_INV_ASSERTION (0x0C) CTX = HAB_CTX_ASSERT (0xA0) ENG = HAB_ENG_ANY (0x00) --------- HAB Event 2 ----------------- 事件数据： 0xdb 0x00 0x14 0x45 0x33 0x0c 0xa0 0x0 0x00 0x00 0x00 0x40 0x1f 0xad 0xc0 0x00 0x00 0x00 0x04 STS = HAB_FAILURE (0x33) RSN = HAB_INV_ASSERTION (0x0C) CTX = HAB_CTX_ASSERT (0xA0) ENG = HAB_ENG_ANY (0x00) --------- HAB Event 3 ----------------- 事件数据： 0xdb 0x00 0x2c 0x45 0x33 0x18 0xc0 0x00 0xca 0x00 0x24 0x00 0x02 0xc5 0x1d 0x00 0x00 0x00 0x0d 0x4c 0x40 0x20 0x00 0x00 0x00 0x13 0xe0 0x10 0x40 0x33 0xe0 0x10 0x00 0x01 0x01 0x30 0x00 0x97 0x00 0x00 0x00 0x00 0xaa 0x70 STS = HAB_FAILURE (0x33) RSN = HAB_INV_SIGNATURE (0x18) CTX = HAB_CTX_COMMAND (0xC0) ENG = HAB_ENG_ANY (0x00) --------- HAB Event 4 ----------------- 事件数据： 0xdb 0x00 0x2c 0x45 0x33 0x18 0xc0 0x00 0xca 0x00 0x24 0x00 0x02 0xc5 0x1d 0x00 0x00 0x00 0x0d 0x4c 0x40 0x20 0x00 0x00 0x00 0x13 0xe0 0x10 0x40 0x33 0xe0 0x10 0x00 0x01 0x01 0x30 0x00 0x97 0x00 0x00 0x00 0x00 0xaa 0x70 STS = HAB_FAILURE (0x33) RSN = HAB_INV_SIGNATURE (0x18) CTX = HAB_CTX_COMMAND (0xC0) ENG = HAB_ENG_ANY (0x00) Re: Secure Boot on i.MX8M Plus 4Gb board failed to get correct HAB Status 你好 事件数据的详细说明见 HAB4_API.pdf、请查看下面的链接： https://community.nxp.com/pwmxy87654/attachments/pwmxy87654/MCX/481/1/HAB4_API.pdf Re: Secure Boot on i.MX8M Plus 4Gb board failed to get correct HAB Status 我使用的是 iWave 的 i.MX 8M Plus SMARC 主板。我有一个问题，是否有一些不同的步骤或一些修改？ Re: Secure Boot on i.MX8M Plus 4Gb board failed to get correct HAB Status 看来你还没签过 " u-boot-imx8mp-iwg40m-4gb.imx " 的部分 @Suraj_Roy Re: Secure Boot on i.MX8M Plus 4Gb board failed to get correct HAB Status 我已经使用安卓单一安全启动步骤 电路板支持包 和 Android 密钥安全指南生成文档签名了

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