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GUIガイドでメモリ使用量を確認する こんにちは。GUI ガイドのプロジェクトが使用するメモリの量を確認しようとしています。アプリケーションでこれに簡単にアクセスする方法はありますか?iMX91プロセッサを使用しています。ありがとう! Re: look at memory usage in gui guider こんにちは、 GUI Guider v1.10.1 ユーザー ガイドを参照して、「メモリ モニター」機能を確認することをお勧めします。 よろしくお願いいたします。
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imx8ulp-evk: Yocto 5.2 (L6.12.49) build failure with tensorflow-lite-vx-delegate / litert-vx-delegat Hello, I am building imx-image-full for i.MX8ULP EVK using NXP Yocto 5.2 (kernel L6.12.49) and encounter build failures related to tensorflow-lite-vx-delegate and litert-vx-delegate. Both packages fail during the download/verify step when fetching kleidiai from Arm GitLab, resulting in a SHA256 checksum mismatch. The issue is reproducible for: tensorflow-lite-vx-delegate (2.19.0) litert-vx-delegate (1.2.0) It appears that the upstream kleidiai archive content has changed while keeping the same commit hash, causing the checksum defined in the recipes to be invalid. Full build logs for both packages are attached below. Questions: Is this a known issue in Yocto 5.2? Is there an official fix or updated checksum? Thanks in advance. i.MX8ULP Yocto Project Re: imx8ulp-evk: Yocto 5.2 (L6.12.49) build failure with tensorflow-lite-vx-delegate / litert-vx-del $ bitbake tensorflow-lite-vx-delegate -c cleansstate $ bitbake tensorflow-lite-vx-delegate -c patch $ cd build/tmp/work/armv8a-poky-linux/tensorflow-lite-vx-delegate/2.19.0/sources-unpack/tfgit $ patch -p1 <0001-Fix-source-sha256-mismatch-issue-for-KleidiAI.patch $ bitbake tensorflow-lite-vx-delegate Re: imx8ulp-evk: Yocto 5.2 (L6.12.49) build failure with tensorflow-lite-vx-delegate / litert-vx-del I ran into the same tensorflow-lite build failure related to kleidiai on Yocto for the frdm-imx93 board. Here is my solution: cd sources/meta-imx patch -Np1 -i 0001-Fixed-KleidiAI-sha256-mismatch.patch This solution does not patch tensorflow itself. I think this is a clearer solution. Re: imx8ulp-evk: Yocto 5.2 (L6.12.49) build failure with tensorflow-lite-vx-delegate / litert-vx-del Thank you for the suggestion. Instead of modifying the downloaded source directly, I applied the workaround properly via a custom meta layer. After applying this change, the build issue of tensorflow-lite-vx-delegate is resolved successfully. However, litert-vx-delegate still fails with the same kleidiai SHA256 checksum mismatch during the download step. Do you have any suggestion for litert-vx-delegate, or is there a separate fix planned for this package? Re: imx8ulp-evk: Yocto 5.2 (L6.12.49) build failure with tensorflow-lite-vx-delegate / litert-vx-del Please refer to the attached patch.
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[IMX8MP][DWE] 广角鱼眼畸变校正 引擎的澄清 摘自 IMX8MPRM,第 1 版,2021 年 6 月: 广角鱼眼畸变校正 引擎不能用作独立组网 (SA) 模块。 1.这是硬件限制(共享时钟控制等)吗? 2.这是软件限制吗,因为用户空间栈(isp-imx)不支持这种用例? 2.是否可以使用 isi_0 或 isp_0 将 RAW8 GRAYSCALE 转换为与 dwe 兼容的格式? Re: [IMX8MP][DWE] Dewarp Engine clarification 我还想同时使用正常视频和去噪视频。您能帮我解决这个问题吗? Re: [IMX8MP][DWE] Dewarp Engine clarification 来自 iMX8MP_CAMERA_DISPLAY_GUIDE.pdf 图 17(见下文)。看来广角鱼眼畸变校正输出是图像信号处理器的单独输出,人们应该能够与访问 /dev/video0 设备节点上的 ISP 输出并行访问该输出。 这种理解是否正确?如果是,我该如何访问 广角鱼眼畸变校正 的输出?我已经激活了广角鱼眼畸变校正 但我只能看到 /dev/video0 设备节点。  欢迎使用 广角鱼眼畸变校正 的任何用法示例。 谢谢   Re: [IMX8MP][DWE] Dewarp Engine clarification 我已经给您发了邮件,并给出了详细答复,请查看您的邮箱 Re: [IMX8MP][DWE] Dewarp Engine clarification 我还想同时使用正常视频和去噪视频。您能帮我解决这个问题吗?
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在线客服微【xins4698】圣淘沙公司注册游戏账号网址以及下载账号官网 在线客服微【xins4698】圣淘沙公司注册游戏账号网址以及下载账号官网 LPC Marketing LPC11xx LPC12xx lpc13xx lpc15xx LPC51Uxx LPC546xx LPC54xxx LPC55xx LPC800
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溦【xins4698】华纳国际万宝路公司申请会员上下分直属流程 溦【xins4698】华纳国际万宝路公司申请会员上下分直属流程 LPC Marketing LPC11xx LPC12xx LPC51Uxx LPC546xx LPC54xxx LPC55xx LPC800
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Can you select multiple controls and modify their properties in a unified way? As the question, with version 1.10.0 actually verified that it is not possible to modify the properties uniformly by selecting multiple controls. This is a very effective feature when modifying the properties of multiple controls in a unified way, if not, can it be added to the next version? Thanks for the reply. Re: 能否选中多个控件统一修改属性 Hi @xiaowan  Thanks for your information. I will report your suggestions to the GUI GUider team. BR Harry
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Encountering a Bus Error while flashing software with Trace32.   Hello, I encountered a bus error when refreshing the S32K324 chip using the trace32 script, as shown in the image above. Could you please tell me what's going on? Is the chip damaged or locked? How can I solve this?  Re: Encountering a Bus Error while flashing software with Trace32. Hello, Are those 2 different issues? Are you able to perform system up? From the screenshot it seems like you are able to attach with reset = system.up. So I see the issue in accessing the memory. Here’s the short list of memory‑access–related solutions: Connect under reset to stop the application from blocking memory access. Full erase before flashing to remove problematic or protected flash content. Update TRACE32 to avoid flash‑driver memory‑access bugs. Fix clock configuration (e.g., oscillator mismatch) that can cause BusFault and block memory. Check C40/HSE security states and perform mass erase if memory access is restricted. Use HardFault/BusFault handler to identify which memory address is being blocked. Disable watchdogs early, as resets can interrupt flash algorithms and break memory access. best regards, Peter Re: Encountering a Bus Error while flashing software with Trace32. Hello, the first screenshot shows the issue that occurred when I ran the first data.load instruction, and the second screenshot shows the issue that occurred when I ran the second data.load instruction. I have flashed the built-in example routines of TRACE32, and the development version can be flashed normally. Thanks for your support. Re: Encountering a Bus Error while flashing software with Trace32. Hello, Ok. It seems that either you are using wrong programming scripts or your flash is corrupt. Try to separately erase flash, then verify it is erased. Then program the data into it. Buss errors can be cause by ECC faults in flash. I am attaching mine programming script so you can test it also. Best regards, Peter
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S32K396-BGA-DC1 ethernet connectivity Looking into using Ethernet on S32K396 and investigating the options of getting connected. We bought S32K396-BGA-DC1 with S32X-MB under the assumption that we would be able to use the T1S PHY that is available on S32X-MB, but S32K396-BGA-DC1 by default wires the PHY signals to a separate PHY connection and not the MB connectors, which coincidentally also destroys many of the provided examples such as SPI etc. It is not entirely obvious where the strapping resisitors on the S32K396-BGA-DC1 board is for rewiring to use the MB connection instead. Only gerbers is provided under design resources, and it appears to be missing net & component information making it unnecessarily hard to navigate the board design. Is there any more easily digestable design resource for the board? Alternatively, which PHY boards are available that works with the PHY connector on S32K396-BGA-DC1? Re: S32K396-BGA-DC1 ethernet connectivity Yes I meant 100BASE-T1. I have managed to locate the resistors. Just very time consuming when having to to search the board visually with no searchable metadata. Availability of the TJA1103-SDBR board is a bit low. I assume TJA1104-SDBR would work as well even if we are not using MACSEC. Re: S32K396-BGA-DC1 ethernet connectivity Hello @Henrik-Wires , Just to clarify that there's no T1S PHY on S32X-MB. There's 100BASE-T1 TJA1103. Yes, S32K396's EMAC is routed to the SABRE connector by default. Regarding PCB, there's no more files available. However, strapping resistors can be located thanks to white labels on PCB. Alternatively, https://www.nxp.com/part/TJA1103-SDBR fits the SABRE connector on S32K396-BGA-DC1 . TJA1103-SDBR needs to be in rev-RMII mode to generate clock on TXC -> add jumper 2-3 to CONFIG4. Best regards, Pavel Re: S32K396-BGA-DC1 ethernet connectivity Hello @Henrik-Wires , Yes, TJA1104-SDBR should work as well as TJA1103-SDBR. Best regards, Pavel Re: S32K396-BGA-DC1 ethernet connectivity Thanks for the reminder to check CONFIG. The default config as delivered is "different".
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i.MX95 VPU H265 のレイテンシとパフォーマンス (v4l2h265enc/v4l2h265dec) こんにちは、 現在、 i.MX95 で H265 デコード → エンコード パイプラインを評価しています が、同様のワークロードと構成を使用して、 i.MX8MP と比較して 、 レイテンシと安定性が大幅に低下していること がわかりました 。 コンテキスト i.MX8MP では 、以下を使用します: imxvpudec_h265 vpuenc_hevc 私は次のことを達成できます: 非常に低いエンドツーエンドのレイテンシ(≈ 10 ミリ秒) 複数のストリームで安定した動作 目に見えるフリーズやアーティファクトなし i.MX95 では 、以下を使用します: v4l2h265dec v4l2h265enc 私は観察します: 1回のデコード→エンコードパイプラインのレイテンシは約90ミリ秒 4 台のカメラ ストリームを同時に 実行するとフリーズや視覚的なアーティファクトが発生する テストパイプライン この問題を再現するために、次のパイプラインで IP カメラ (H265 over RTSP) を使用しました。 test-launch "( rtspsrc location=rtsp://10.42.0.85 drop-on-latency=true latency=0 buffer-mode=4 ! rtph265depay ! h265parse config-interval=1 ! v4l2h265dec ! v4l2h265enc ! rtph265pay name=pay0 pt=96 )" このパイプラインは 1 台のカメラでは正常に動作しますが、 4 台のカメラに拡張すると、フリーズやアーティファクトが発生し始めます。 質問 i.MX95 上の H265 VPU パイプラインの遅延が i.MX8MP 上よりも大幅に大きいのはなぜですか? i.MX95 の v4l2h265dec と v4l2h265enc 間で DMABUF ゼロコピーは完全にサポートされていますか? そうでない場合、追加のレイテンシと帯域幅の圧力を説明できる暗黙的なメモリコピーはありますか? 現在の i.MX95 VPU ドライバーには、次のような既知の制限がありますか? 低レイテンシ操作 マルチストリームデコード+エンコード 内部バッファリング深度 i.MX95 のレイテンシを最小限に抑えるために推奨される V4L2 コントロールまたは io モード (キャプチャ/出力 io モード) はありますか? i.MX95 VPU ドライバーは、FUTURE BSP リリースで i.MX8MP と同等のパフォーマンスを達成することが期待されていますか? それとも、レイテンシが高くなることはデザイン上のトレードオフなのでしょうか? ゴール 私の目標は 、i.MX8MP で実現可能なものと同様の 、リアルタイムで低レイテンシのビデオプロセッシング(デコード → 処理 → エンコード) です。 再開まで今しばらくお待ちください。 Re: i.MX95 VPU H265 latency and performance(v4l2h265enc/v4l2h265dec) こんにちは、 この問題を再現するために、i.MX8MP および i.MX95 でどのバージョンの BSP を使用していますか? 8MP と 95 の両方で同じ GST パイプライン (デコーダー/エンコーダー要素以外) を使用していますか? 私の知る限り、i.MX95 で高レイテンシを引き起こす既知の制限はありません。 i.MX95 では、エンコーダーは mmap と dmabuf をサポートしており、デコーダーとエンコーダー間のコピーなしで dma-buf を転送するパイプラインを作成できます。 IP カメラは B フレームなしでエンコードしますか?次に、デコード フレームの並べ替えを無効にすると、レイテンシが短縮されます。これをチェックしてください。以下のv4l2コントロールを使用してフレームの並べ替えを無効にすることができます。 「 v4l2h264dec extra-controls="デコード、display_delay_enable=1、display_delay=0" 」 以下のコマンドを使用して、すべての v4l2 コントロールを一覧表示できます。 v4l2-ctl -l -d よろしくお願いします。 Re: i.MX95 VPU H265 latency and performance(v4l2h265enc/v4l2h265dec) カーネルのバージョン: imx95: 6.6.101-0 imx8mp: 6.6.84-0 はい、同じ gstreamer パイプラインです。 IP カメラは B フレームなしでエンコードします。コマンドを試しましたが、問題は解決しませんでした。画面にはまだアーティファクトがあり、レイテンシも大きいです。しかし、質的に言えば、フリーズは解除されるようです。 「」 v4l2-ctl -l -d /dev/v4l/by-path/プラットフォーム-4c480000.vpu-video-index0 ユーザーコントロール min_number_of_capture_buffers 0x00980927 (int) : min=1 max=32 step=1 default=1 value=1 flags=read-only thumbnail_mode 0x00981901 (bool) : デフォルト=0 値=0 フラグ=書き込み専用 コーデックコントロール h264_profile 0x00990a6b (メニュー): 最小=0 最大=4 デフォルト=0 値=0 (ベースライン) hevc_profile 0x00990b67 (メニュー) : min=0 max=0 default=0 value=0 (メイン) display_delay 0x00990b8d (int) : 最小=0 最大=0 ステップ=1 デフォルト=0 値=0 display_delay_enable 0x00990b8e (bool) : デフォルト=0 値=0 「」 「」 v4l2-ctl -l -d /dev/v4l/by-path/platform-4c480000.vpu-video-index1 ユーザーコントロール horizontal_flip 0x00980914 (bool) : デフォルト=0 値=0 vertical_flip 0x00980915 (bool) : デフォルト=0 値=0 回転 0x00980922 (int) : 最小=0 最大=270 ステップ=90 デフォルト=0 値=0 フラグ=レイアウト変更 min_number_of_output_buffers 0x00980928 (int) : min=1 max=32 step=1 default=1 value=1 flags=read-only コーデックコントロール video_gop_size 0x009909cb (int) : 最小=0 最大=2047 ステップ=1 デフォルト=30 値=30 video_bitrate_mode 0x009909ce (メニュー) : min=0 max=1 default=1 value=1 (固定ビットレート) flags=update video_bitrate 0x009909cf (int) : 最小=1 最大=1500000000 ステップ=1 デフォルト=2097152 値=2097152 frame_level_rate_control_enable 0x009909d7 (bool) : デフォルト=1 値=1 h264_mb_level_rate_control 0x009909da (bool) : デフォルト=1 値=1 スライス内のMBS数 0x009909dc (int) : 最小値=0 最大値=262143 ステップ=1 デフォルト=1 値=1 slice_partitioning_method 0x009909dd (メニュー): min=0 max=1 default=0 value=0 (シングル) force_key_frame 0x009909e5 (ボタン) : 値=0 フラグ=書き込み専用、書き込み時に実行 intra_refresh_period 0x009909ec (int) : 最小=0 最大=2160 ステップ=1 デフォルト=0 値=0 intra_refresh_period_type 0x009909ed (メニュー) : min=0 max=1 default=1 value=1 (Cyclic) h264_i_frame_qp_value 0x00990a5e (int) : 最小=0 最大=51 ステップ=1 デフォルト=30 値=30 h264_p_frame_qp_value 0x00990a5f (int) : 最小値=0 最大値=51 ステップ=1 デフォルト=30 値=30 h264_b_frame_qp_value 0x00990a60 (int) : 最小=0 最大=51 ステップ=1 デフォルト=30 値=30 h264_minimum_qp_value 0x00990a61 (int) : 最小値=0 最大値=51 ステップ=1 デフォルト=8 値=8 h264_maximum_qp_value 0x00990a62 (int) : 最小値=0 最大値=51 ステップ=1 デフォルト=51 値=51 h264_8x8_transform_enable 0x00990a63 (bool) : デフォルト=1 値=1 h264_cpb_buffer_size 0x00990a64 (int) : 最小=0 最大=18750000 ステップ=1 デフォルト=0 値=0 h264_entropy_mode 0x00990a65 (メニュー): 最小=0 最大=1 デフォルト=1 値=1 (CABAC) h264_i_frame_period 0x00990a66 (int) : 最小=0 最大=2047 ステップ=1 デフォルト=0 値=0 h264_level 0x00990a67 (メニュー): 最小=0 最大=16 デフォルト=14 値=14 (5) h264_loop_filter_alpha_offset 0x00990a68 (int) : 最小値=-6 最大値=6 ステップ=1 デフォルト=0 値=0 h264_loop_filter_beta_offset 0x00990a69 (int) : 最小値=-6 最大値=6 ステップ=1 デフォルト=0 値=0 h264_loop_filter_mode 0x00990a6a (メニュー): min=0 max=2 default=0 value=0 (有効) h264_profile 0x00990a6b (メニュー): 最小=0 最大=4 デフォルト=4 値=4 (高) vertical_size_of_sar 0x00990a6c (int) : 最小=0 最大=65535 ステップ=1 デフォルト=0 値=0 horizontal_size_of_sar 0x00990a6d (int) : 最小=0 最大=65535 ステップ=1 デフォルト=0 値=0 aspect_ratio_vui_enable 0x00990a6e (bool) : デフォルト=0 値=0 vui_aspect_ratio_idc 0x00990a6f (メニュー): 最小=0 最大=17 デフォルト=0 値=0 (未指定) h264_constrained_intra_pred 0x00990a7f (int) : 最小値=0 最大値=1 ステップ=1 デフォルト=0 値=0 h264_chroma_qp_index_offset 0x00990a80 (int) : 最小=-12 最大=12 ステップ=1 デフォルト=0 値=0 hevc_minimum_qp_value 0x00990b58 (int) : 最小値=0 最大値=51 ステップ=1 デフォルト=8 値=8 hevc_maximum_qp_value 0x00990b59 (int) : 最小値=0 最大値=51 ステップ=1 デフォルト=51 値=51 hevc_i_frame_qp_value 0x00990b5a (int) : 最小=0 最大=51 ステップ=1 デフォルト=30 値=30 hevc_p_frame_qp_value 0x00990b5b (int) : 最小=0 最大=51 ステップ=1 デフォルト=30 値=30 hevc_b_frame_qp_value 0x00990b5c (int) : 最小=0 最大=51 ステップ=1 デフォルト=30 値=30 hevc_profile 0x00990b67 (メニュー) : min=0 max=0 default=0 value=0 (メイン) hevc_level 0x00990b68 (メニュー) : 最小=0 最大=8 デフォルト=7 値=7 (5) hevc_loop_filter 0x00990b6c (メニュー): 最小=0 最大=2 デフォルト=1 値=1 (有効) hevc_loop_filter_beta_offset 0x00990b6d (int) : 最小値=-6 最大値=6 ステップ=1 デフォルト=0 値=0 hevc_loop_filter_tc_offset 0x00990b6e (int) : 最小=-6 最大=6 ステップ=1 デフォルト=0 値=0 hevc_refresh_type 0x00990b6f (メニュー) : 最小=0 最大=2 デフォルト=2 値=2 (IDR) hevc_num_of_i_frame_b_w_2_idr 0x00990b70 (int) : 最小=0 最大=2047 ステップ=1 デフォルト=0 値=0 hevc_constant_intra_prediction 0x00990b72 (int) : 最小値=0 最大値=1 ステップ=1 デフォルト=0 値=0 hevc_strong_intra_smoothing 0x00990b76 (int) : 最小値=0 最大値=1 ステップ=1 デフォルト=1 値=1 hevc_tmv_prediction 0x00990b79 (int) : 最小=0 最大=1 ステップ=1 デフォルト=1 値=1 prepend_sps_and_pps_to_idr 0x00990b84 (int) : 最小値=0 最大値=1 ステップ=1 デフォルト=1 値=1 frame_skip_mode 0x00990b86 (メニュー) : min=0 max=2 default=0 value=0 (無効) average_qp_value 0x00990b91 (int) : 最小値=0 最大値=51 ステップ=1 デフォルト=0 値=0 フラグ=読み取り専用 「」 Re: i.MX95 VPU H265 latency and performance(v4l2h265enc/v4l2h265dec) BSP バージョンは次のとおりです: imx8mp: lf-6.6.52-2.2.0 imx95: lf-6.6.52-2.2.1 よろしくお願い申し上げます。 Re: i.MX95 VPU H265 latency and performance(v4l2h265enc/v4l2h265dec) わかりました。また、上で述べた B フレームの質問も確認してください。 よろしくお願いします。 Re: i.MX95 VPU H265 latency and performance(v4l2h265enc/v4l2h265dec) はい、IP カメラは B フレームなしでエンコードします。コマンドを試しましたが、問題は解決しませんでした。画面にはまだアーティファクトがあり、レイテンシも大きいです。しかし、質的に言えば、フリーズは解除されるようです。 Re: i.MX95 VPU H265 latency and performance(v4l2h265enc/v4l2h265dec) こんにちは、 確認ですが、IPカメラはBフレームなしでエンコードします(IPのみ)。デコーダーにdisplay_delay_enable=1、display_delay=0を適用しました。これによりフリーズは解消されたものの、レイテンシは約90ミリ秒のままとなっている。 ボトルネックを特定するために、このパイプラインでGStreamerの要素レイテンシトレーサーを使用しました。 「`」 rtspsrc location=rtsp://... drop-on-latency=true latency=0 buffer-mode=4 ! rtph265depay ! h265parse config-interval=1 ! v4l2h265dec extra-controls="decode,display_delay_enable=1,display_delay=0" capture-io-mode=4 output-io-mode=4 ! v4l2h265enc extra-controls="encode,video_bitrate_mode=1,video_bitrate=2097152,frame_level_rate_control_enable=0,video_gop_size=30" capture-io-mode=4 output-io-mode=4 ! h265parse config-interval=1 ! rtph265pay name=pay0 pt=96 「`」 要素ごとのレイテンシ結果(640x480 @ 30fps、シングルストリーム): v4l2h265enc: 約67ミリ秒 v4l2h265dec 約2ミリ秒 その他の要素はすべて1ms未満 エンコーダーだけで約67ミリ秒(約2フレーム周期)を占める。これはどの実行においても一貫している。デコーダーは2ミリ秒程度で正常に動作します。 私は以下のことを試しました: frame_level_rate_control_enable=0 エンコーダとデコーダの両方で capture-io-mode=4 および output-io-mode=4 (DMABUF) を使用する 要素間のキューバッファリングを最小限に抑える(max-size-buffers=1) これらのいずれもエンコーダーのレイテンシを大幅に短縮するものではない。 私の質問はエンコーダーに焦点を当てたものでした。 Wave6エンコーダーは、出力前に内部で2フレームを保持することが想定されていますか?この内部バッファリングを減らす方法はありますか(デコーダ側のdisplay_delay=0のように)? output-io-mode=5 (DMABUF_IMPORT) はエンコーダー上で動作し、アップストリームからのゼロコピーを実現しますか?これはレイテンシの改善に役立ちますか? Wave6で低レイテンシ/ゼロ遅延エンコードモードを有効にするためのV4L2制御パラメータまたはドライバパラメータはありますか? i.MX8MPでは、vpuenc_hevcは同じワークロードで約10ミリ秒を実現します。i.MX95におけるv4l2h265encのレイテンシギャップは、今後のBSPリリースで改善される見込みですか? ご協力ありがとうございます。
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i.MX95 VPU H265 延迟和性能(v4l2h265enc/v4l2h265dec) 你好 我目前正在 i.MX95 上评估 H265 解码 → 编码流水线。 i.MX95上的 延迟和稳定性与 i.MX8MP相比,在类似的工作负载和配置下,延迟和稳定性明显更差。 上下文 关于 i.MX8MP使用 imxvpudec_h265 vpuenc_hevc 我能够实现: 极低的端到端延迟(≈ 10 毫秒) 多数据流的稳定运行 无明显的冻结或人工痕迹 关于 i.MX95使用 v4l2h265dec v4l2h265enc 我观察到了: 单个解码 → 编码流水线的 ~90 毫秒延迟 运行时出现冻结和视觉假象 4 路同步摄像机数据流 测试管道 为了重现这个问题,我使用了 IP 摄像机(通过 RTSP 传输 H265),其管道如下: test-launch "( rtspsrc location=rtsp://10.42.0.85 drop-on-latency=true latency=0 buffer-mode=4 ! rtph265depay ! h265parse config-interval=1 ! v4l2h265dec ! v4l2h265enc ! rtph265pay name=pay0 pt=96 )" 该流水线在使用单台摄像机时工作正常,但当扩展到 4 个摄像头就会出现冻结和伪影。 问题 为什么 i.MX95 上的 H265 VPU 管线比 i.MX8MP 上的潜伏性更高? i.MX95 上的 v4l2h265dec 和 v4l2h265enc 之间是否完全支持 DMABUF 零拷贝? 如果没有,是否存在隐式内存拷贝,可以解释额外的延迟和带宽压力? 目前的 i.MX95 VPU 驱动程序是否存在已知的限制? 低延迟运行 多流解码 + 编码 内部缓冲深度 是否有推荐的 V4L2 控件或 io 模式(捕获/输出 io模式)来最大限度地减少 i.MX95 的延迟? 在未来的电路板支持包版本中,i.MX95 VPU驱动程序是否有望达到与i.MX8MP相同的性能,还是更高的延迟是一种固有的设计权衡? 目标 我的目标是 实时、低延迟的视频处理(解码 → 处理 → 编码),类似于 i.MX8MP 可实现的功能。 感谢您的支持。 Re: i.MX95 VPU H265 latency and performance(v4l2h265enc/v4l2h265dec) 你好 你在 i.mx8MP 和 i.MX95 上使用哪个电路板支持包 版本来重现这个问题? 您是否在 800 万像素和 95 万像素上使用相同的 GST 管道(除解码器/编码器元件外)? 据我所知,i.MX95 没有导致高延迟的已知限制。 在 i.MX95 上,编码器支持 mmap 和 dmabuf,这可以在解码器和编码器之间建立一个传输 dma-buf 的流水线,而无需复制。 网络摄像机编码时是否没有 B 帧?这样我们就可以禁用解码帧重排,从而减少延迟。请检查这一点。您可以使用以下 v4l2 控件禁用帧重排 " v4l2h264dec extra-controls="decode,display_delay_enable=1,display_delay=0" " 您可以使用以下命令列出所有 v4l2 控制: v4l2-ctl -l -d 此致 Re: i.MX95 VPU H265 latency and performance(v4l2h265enc/v4l2h265dec) 内核版本 imx95: 6.6.101-0 imx8mp:6.6.84-0 是的,这是同一个 gstreamer 管道。 网络摄像机不对 B 帧进行编码。我执行了你的命令,但并没有解决问题。屏幕上仍有伪影,延迟也很高。不过,从质量上讲,它似乎消除了冻结现象。 ``` v4l2-ctl -l -d /dev/v4l/by-path/platform-4c480000.vpu-video-index0 用户控制 min_number_of_capture_buffers 0x00980927 (int) : min=1 max=32 step=1 default=1 value=1 flags=read-only thumbnail_mode 0x00981901 (bool) : default=0 value=0 flags=write-only 编解码器控制 h264_profile 0x00990a6b (menu) : min=0 max=4 default=0 value=0 (Baseline) hevc_profile 0x00990b67 (menu) : min=0 max=0 default=0 value=0 (Main) display_delay 0x00990b8d (int) : min=0 max=0 step=1 default=0 value=0 display_delay_enable 0x00990b8e (bool) : default=0 value=0 ``` ``` v4l2-ctl -l -d /dev/v4l/by-path/platform-4c480000.vpu-video-index1 用户控制 horizontal_flip 0x00980914 (bool) : default=0 value=0 vertical_flip 0x00980915 (bool) : default=0 value=0 rotate 0x00980922 (int) : min=0 max=270 step=90 default=0 value=0 flags=modify-layout min_number_of_output_buffers 0x00980928 (int) : min=1 max=32 step=1 default=1 value=1 flags=read-only 编解码器控制 video_gop_size 0x009909cb (int) : min=0 max=2047 step=1 default=30 value=30 video_bitrate_mode 0x009909ce (menu) :min=0 max=1 default=1 value=1 (恒定比特率) flags=update video_bitrate 0x009909cf (int) : min=1 max=1500000000 step=1 default=2097152 value=2097152 frame_level_rate_control_enable 0x009909d7 (bool) :default=1 value=1 h264_mb_level_rate_control 0x009909da (bool) : default=1 value=1 number_of_mbs_in_a_slice 0x009909dc (int) : min=0 max=262143 step=1 default=1 value=1 slice_partitioning_method 0x009909dd (menu) :min=0 max=1 default=0 value=0 (Single) force_key_frame 0x009909e5 (button) : value=0 flags=write-only, execute-on-write intra_refresh_period 0x009909ec (int) :min=0 max=2160 step=1 default=0 value=0 intra_refresh_period_type 0x009909ed (menu) : min=0 max=1 default=1 value=1 (Cyclic) h264_i_frame_qp_value 0x00990a5e (int) :min=0 max=51 step=1 default=30 value=30 h264_p_frame_qp_value 0x00990a5f (int) : min=0 max=51 step=1 default=30 value=30 h264_b_frame_qp_value 0x00990a60 (int) :min=0 max=51 step=1 default=30 value=30 h264_minimum_qp_value 0x00990a61 (int) : min=0 max=51 step=1 default=8 value=8 h264_maximum_qp_value 0x00990a62 (int) :min=0 max=51 step=1 default=51 value=51 h264_8x8_transform_enable 0x00990a63 (bool) : default=1 value=1 h264_cpb_buffer_size 0x00990a64 (int) : min=0 max=18750000 step=1 default=0 value=0 h264_entropy_mode 0x00990a65 (menu) : min=0 max=1 default=1 value=1 (CABAC) h264_i_frame_period 0x00990a66 (int) : min=0 max=2047 step=1 default=0 value=0 h264_level 0x00990a67 (menu) :min=0 max=16 default=14 value=14 (5) h264_loop_filter_alpha_offset 0x00990a68 (int) : min=-6 max=6 step=1 default=0 value=0 h264_loop_filter_beta_offset 0x00990a69 (int) :min=-6 max=6 step=1 default=0 value=0 h264_loop_filter_mode 0x00990a6a (menu) : min=0 max=2 default=0 value=0 (Enabled) h264_profile 0x00990a6b (menu) :min=0 max=4 default=4 value=4 (High) vertical_size_of_sar 0x00990a6c (int) : min=0 max=65535 step=1 default=0 value=0 horizontal_size_of_sar 0x00990a6d (int) :min=0 max=65535 step=1 default=0 value=0 aspect_ratio_vui_enable 0x00990a6e (bool) : default=0 value=0 vui_aspect_ratio_idc 0x00990a6f (menu) :min=0 max=17 default=0 value=0 (Unspecified) h264_constrained_intra_pred 0x00990a7f (int) : min=0 max=1 step=1 default=0 value=0 h264_chroma_qp_index_offset 0x00990a80 (int) :min=-12 max=12 step=1 default=0 value=0 hevc_minimum_qp_value 0x00990b58 (int) : min=0 max=51 step=1 default=8 value=8 hevc_maximum_qp_value 0x00990b59 (int) :min=0 max=51 step=1 default=51 value=51 hevc_i_frame_qp_value 0x00990b5a (int) : min=0 max=51 step=1 default=30 value=30 hevc_p_frame_qp_value 0x00990b5b (int) : min=0 max=51 step=1 default=30 value=30 hevc_b_frame_qp_value 0x00990b5c (int) : min=0 max=51 step=1 default=30 value=30 hevc_profile 0x00990b67 (menu) : min=0 max=0 default=0 value=0 (Main) hevc_level 0x00990b68 (menu) : min=0 max=8 default=7 value=7 (5) hevc_loop_filter 0x00990b6c (menu) :min=0 max=2 default=1 value=1 (Enabled) hevc_loop_filter_beta_offset 0x00990b6d (int) : min=-6 max=6 step=1 default=0 value=0 hevc_loop_filter_tc_offset 0x00990b6e (int) :min=-6 max=6 step=1 default=0 value=0 hevc_refresh_type 0x00990b6f (menu) : min=0 max=2 default=2 value=2 (IDR) hevc_num_of_i_frame_b_w_2_idr 0x00990b70 (int) :min=0 max=2047 step=1 default=0 value=0 hevc_constant_intra_prediction 0x00990b72 (int) : min=0 max=1 step=1 default=0 value=0 hevc_strong_intra_smoothing 0x00990b76 (int) : min=0 max=1 step=1 default=1 value=1 hevc_tmv_prediction 0x00990b79 (int) :min=0 max=1 step=1 default=1 value=1 prepend_sps_and_pps_to_idr 0x00990b84 (int) : min=0 max=1 step=1 default=1 value=1 frame_skip_mode 0x00990b86 (menu) : min=0 max=2 default=0 value=0 (Disabled) average_qp_value 0x00990b91 (int) : min=0 max=51 step=1 default=0 value=0 flags=read-only ```` Re: i.MX95 VPU H265 latency and performance(v4l2h265enc/v4l2h265dec) 电路板支持包 版本是: imx8mp: lf-6.6.52-2.2.0 imx95: lf-6.6.52-2.2.1 谢谢 Re: i.MX95 VPU H265 latency and performance(v4l2h265enc/v4l2h265dec) ok 还请确认我上面提到的 B 框架问题。 此致 Re: i.MX95 VPU H265 latency and performance(v4l2h265enc/v4l2h265dec) 是的,网络摄像机编码时没有 B 帧。我试过你的命令,但没有解决问题。屏幕上仍有伪影,延迟也很高。不过,从质量上讲,它似乎消除了冻结现象。 Re: i.MX95 VPU H265 latency and performance(v4l2h265enc/v4l2h265dec) 你好 确认:网络摄像机编码时没有 B 帧(仅限 I-P)。我在解码器上应用了 display_delay_enable=1,display_delay=0。这有助于消除冻结现象,但延迟时间仍为约 90 毫秒。 为了隔离瓶颈,我在这条流水线上使用了 GStreamer 元素延迟跟踪器: ``` rtspsrc location=rtsp://... drop-on-latency=true latency=0 buffer-mode=4!rtph265depay!h265parse 配置间隔=1!v4l2h265dec extra-controls= " 解码,display_delay_enable=1,display_delay=0 " 捕获-io-mode=4 output-io-mode=4!v4l2h265enc extra-controls= " 编码,video_bitrate_mode=1,video_bitrate=2097152,frame_level_rate_control_enable=0,video_gop_size=30 " 捕获-io-mode=4 输出 io-mode=4!h265parse 配置间隔=1!rtph265pay name=pay0 pt=96 ``` 每个元素的延迟结果(640x480 @ 30fps,单流): V4L2H265enc: ~67 ms V4L2H265DEC ~2 ms 所有其他元素< 1 ms 仅编码器就占了约 67 毫秒(约 2 个帧周期)。这在各次运行中是一致的。解码器在 ~2 毫秒时没有问题。 我已经试过了: frame_level_rate_control_enable=0 编码器和解码器上的 capture-io-mode=4 和 output-io-mode=4 (DMABUF) 元素之间的最小队列缓冲(max-size-buffers=1) 这些方法都不能明显减少编码器的延迟。 我的问题主要集中在编码器上: Wave6 编码器在输出之前是否需要在内部保留 2 个帧?有没有办法减少这种内部缓冲(类似于解码器端的 display_delay=0)? 输出-io-mode=5(DMABUF_IMPORT)对编码器是否有效,以实现上游零拷贝?这对延迟有帮助吗? 是否有 V4L2 控制或驱动程序参数来启用 Wave6 的低延迟/零延迟编码模式? 在 i.MX8MP 上,vpuenc_hevc 在相同工作负载下的运行时间约为 10 毫秒。在未来的 BSP 版本中,i.MX95 上与 v4l2h265enc 的延迟差距有望改善吗? 感谢您的帮助。
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RDDRONE-BMS772 Please ask questions about the RDDRONE-BMS772 board and software here Re: RDDRONE-BMS772 Hi @xete , It seems that the IC is powered and working. A 4S battery (both LiPo or LiFePO4)  is indeed in the correct supply range. That cannot be the issue. Maybe a full disconnect (battery, programmer, serial interface) could help? It could be a connection issue.  Can you try a slower programming speed?  Long wires and pin converters could impact the maximum programing speed. You now use 1000kHz, "1000", can you try "100"? 100kHz programming speed? If you would be able to upload a picture of the setup, that might show an issue. Or provide the voltages on these programmer pins. It would be interesting to know if the MCU is kept in reset or what VTref is. Kind regards,  Cis Re: RDDRONE-BMS772 Hi @cisvmierlo , Thank you for the quick reply. I was powering the BMS with a 4S battery. I was also using 3.3V TTL to USB to look at the serial output. The BMS was in the NORMAL state based on the LCD Screen and Serial. It was connected to a J Link Compact Plus according to the pinout below. Do let me know if you require any other info/suggestions for troubleshooting Re: RDDRONE-BMS772 Hi @xete , Could you explain more about your setup in which you face an issue? How did you power the RDDRONE-BMS772? What is the status of the RGB LED on the RDDRONE-BMS772? A picture of your setup would be helpful to be able to assist you in your problem with programming. Kind regards, Cis Re: RDDRONE-BMS772 I am trying to flash firmware on to the BMS. However, I am facing this error when attempting to connect via SWD. Re: RDDRONE-BMS772 Yes, we are currently testing the next release candidate of the open source BMS772 reference SW that includes DroneCAN support. Re: RDDRONE-BMS772 We would like to use the RDDRONE-BMS772 in our drone batteries.  My question is, if there already is a PX4 integration based on UAVCAN? Is there any work which we can pick up? Thanks in advance Jan Re: RDDRONE-BMS772 After this voltage drop of the charger, will the charger stay off? No at this point the charger will stay on. So it would restart the charge process if the current draw stopped. In the future we will implement a controllable charger to disable upon full charge. Or will it have a lower voltage than your battery and the charger is protected against sinking the current? No the charger is slightly higher in voltage to achieve full charge but it is also protected against reverse current. Would it be feasible to increase the voltage level in which the BMS determines the charger has been disconnected? This way it may prevent the brown out of the computer. Then it would go back into charge state and protect itself from overcharging. I will also intergrade a UPS as an alternative solution to the problem. Thanks for your help 🙂  Re: RDDRONE-BMS772 Hi All, I am wondering is there anyway to read the type of fault code from the CLI? I can read the state (bms get state => FAULT) but is there a way to receive the type of fault e.g. over voltage? If not do you have some guidance on the best way to implement that in the firmware?  Thanks for your help, Lewis   Re: RDDRONE-BMS772 Hi Lewis, From reading your story I'm assuming the BMS is in the charge-complete state. With the power disabled to stop the battery from overcharging.  When your system draws more current than the still attached battery charger can provide, the voltage will drop.  In the charge-complete state, there will not be a current flowing from the battery, as the power switch is open. The BMS will check the output voltage too see if the charger is disconnected.  When the charger has this voltage drop and this drop is low enough for the BMS to think the charger is disconnected, it will go the SLEEP state, but it will first set the MCU in very low power run (VLPR) mode and other peripherals in lower power modes as well before closing the power switch. After this voltage drop of the charger, will the charger stay off? Or will it have a lower volage than your battery and the charger is protected against sinking the current? Kind regards, Cis van Mierlo Re: RDDRONE-BMS772 Thank you for your reply Cis van Mierlo, that was very helpful. I was able to get the functionality I needed by using an N-Channel, P-Channel Mosfet with and RC timer to momentarily pull the wake pin low if a charger voltage is connected.  Another thing I am looking into is the time it takes for the BMS to wake from sleep state due to over current detection (i-sleep-oc). The issue I am facing that after a full charge the BMS output will be disabled to stop overcharging, if our robot then draws more current then the charger can supply the BMS will detect this and enable the output. However attaching the scope I have measured a switch time of the BMS of about 300-800ms. This delay is a problem as it causes a brown out for the raspberry pi.  I am wondering if there is a way to reduce this time? Maybe by updating the frequency it checks the output current to wake? If I can reduce the time I can the look into smoothing the voltage drop. Thanks again for your help. Lewis. Re: RDDRONE-BMS772 Hi Lewis, Indeed, the BMS goes to deep sleep to preserve any charge left in the battery. Meaning that this will be the lowest power mode (±100uA).  The only way that this is feasible, is to turn off the VCC_3V3_SBC, which is used to power the MCU. Meaning that the MCU will be off. So, setting an interrupt won't help with waking up from this mode. The only to wake up from this is mode is to either re-apply a voltage to the BMS or to pull down the SBC's (U3) wake pin (pin 12). Maybe use J22 to pull down the wake pin (keep in mind that the voltage on this connector is between the battery voltage and 0V). For example, you could use an external switch or signal controlled from your other system to pull this low. Another solution would be to send the "bms reset" command over de CLI (UART) when you receive the undervoltage fault and the BMS is counting down before going into the deep sleep mode. This will reset the timer. You could also reconfigure the timeout time for the BMS to go to deep sleep and even disable it. To do this, see t-fault-timeout in chapter 8.2.2 (page 18) in https://github.com/NXPHoverGames/RDDRONE-BMS772/blob/main/BMS772_releaseNotes_5.0.pdf  Hopefully this will help, kind regards, Cis van Mierlo Re: RDDRONE-BMS772 Hi All, We are facing an issue with the integration of the NXP BMS into our ROV system and hoping for some guidance on the changes I should make to the firmware to resolve the issue. The problem is we occasionally will deplete a battery during an ROV flight underwater, and the vehicle becomes unrecoverable as the BMS will go into deep sleep. Following an under voltage fault the BMS will enter deep sleep to reduce any further draw on the battery, part of this means turning off the UART communications. If we apply voltage to the BMS it will remain in deep sleep until the physical reset button is pushed. The issue is that the robot is deployed under the water, so physically pushing the button won't work and we aren't able to communicate via UART as it has gone into deep sleep. So I am seeking any advice on how I might be able to overcome this problem. The goal would be to still have the BMS enter deep sleep mode to prevent further discharge of the battery however to be able to wake the battery via a UART command or if charge voltage is detected. I was thinking I could attach an interrupt to the UART RX pin before entering deep sleep, which will reset the fault during wake up. Is this a feasible solution and if so is it possible for you to point me in the direction of the firmware I could do this? Thank you for your help, Lewis Re: RDDRONE-BMS772 Thank you that solution worked well for us. Re: RDDRONE-BMS772 Hi @lmiles-sosub, The purpose of the gate check is to make sure the gate driver is able to turn off the power. It there would be something wrong with this or other components and it is not able to turn off the power, this could result in a safety issue, hence the self-test.  I get that for your purpose, this is not ideal. Feel free to disable this check in your software for your purpose if you think this is safe. Keep in mind that it will not check if the power can be switched off. Plus I would advise you to still turn off the power in that part of the code, you could either replace the part with the below piece of code or add compile switches (#ifdef #else #endif) so you could easily go back to the original state. This part needs to be replaced or put in an compile switch: https://github.com/NXPHoverGames/RDDRONE-BMS772/blob/main/src/batManagement.c#L608-L672  This is the piece of code I would advice you to still add: // still turn off the gate batManagement_setGatePower(GATE_OPEN); cli_printfWarning("SELF-TEST GATE: TURNED OFF!\n"); I hope this answers your question, kind regards, Cis van Mierlo Re: RDDRONE-BMS772 Hi All, We are testing the use of the BMS in an ROV system with a charger that constantly supplies power to the ROV and the battery will provide power for peak loads above the chargers power capacity.  We are having some issues when the battery reaches its under voltage protection (enters fault mode) and are trying to recover the BMS from fault state to be able to charge the battery.  Ideally the BMS would shut off output but would still allow a charge current to enter the battery, without needing to be reset. Currently we are resetting the BMS remotely through the CLI to remove the fault however to power the system we must have the charger on, which then results in the self test failing and suggesting to remove the charger. My question is around the functionality of the charger having to be disconnected for the gate self test. What is the purpose of it and would there be a critical issue if I were to disable it in the firmware? Thanks for your help. Lewis Re: RDDRONE-BMS772 Hi @suvasis , The .brd layout file of the RDDRONE-BMS772 has been added to the design files and could be downloaded. Please see https://www.nxp.com/design/designs/smart-battery-management-for-mobile-robotics:RDDRONE-BMS772 Kind regards, Cis van Mierlo Re: RDDRONE-BMS772 Hi @cisvmierlo, I tried rebooting and re powering the BMS it didn't help. I will try going into DEEP_SLEEP. Thanks for your help. Regards, Prince Re: RDDRONE-BMS772 Hi @Prince1, Have you tried rebooting the MCU with the "reboot" command? Another thing you could try to reset the communication errors (as they are remembered) go to DEEP_SLEEP and back to NORMAL state? Otherwise you could try to re-power the BMS power to solve the problem. Kind regards, Cis van Mierlo Re: RDDRONE-BMS772 Hi @suvasis,  I've asked the team if they could upload the board file (.brd) as well to nxp.com. Be aware that this could take a couple days. The schematic file (.DSN) is already included. Kind regards, Cis van Mierlo Re: RDDRONE-BMS772 Hi, Tera term is throwing few errors when connected with BMS as shown in images attached herewith. "Couldn't do measurements and also Failed to update measurements" Please help in resolving them? Thanks, Prince Re: RDDRONE-BMS772 hi, I am trying to redesign the PCB to a smaller form factor for my drone. The following document https://www.nxp.com/design/designs/smart-battery-management-for-mobile-robotics:RDDRONE-BMS772 generally provides schematic and fabrication files but those link does not contain the source file of the PCB. can anyone include the source file for the PCB?   Can anyone help me? thanks. suvasis Re: RDDRONE-BMS772 Hi @dmorvay, I think it would be possible to multiplex the I2CS to the PTA2/PTA3 pins. I would check the S32K-RM chapter 52: Low Power Inter-Integrated Circuit (LPI2C) for this. But then you need to make the correct changes in the code, I do not know if the SDK supports this. Kind regards, Cis van Mierlo Re: RDDRONE-BMS772 Hello @dmorvay, Regarding the second question, the MBD Toolbox for S32K14x is built on top of the SDK for S32k14x. Unfortunately, it seems that the 4-wire mode is not supported for LPI2C by the SDK, therefore MBD toolbox doesn't support it either. Best regards, Bancila Sorin Re: RDDRONE-BMS772 Hi @cisvmierlo , Thank you for this information. I am still unsure about the answer to my first question - Can PTA2/PTA3 (J23) be configured as an I2C slave? Are there any limitations on this I/O that it always has to be configured as a master?  Re: RDDRONE-BMS772 Hi @dmorvay,  I'm not familiar with the MBDT example and what is supported in that toolbox. For a C / C++ example I would advise you to take a look into the NuttX RTOS SW example. In this example you can get the BMS data via I2C by reading the correct I2C addresses as stated in Table 6. SMBus variable list (Of chapter 7.5 How to use SMBus).  This example is located here: https://github.com/NXPHoverGames/RDDRONE-BMS772  It will need the NuttX RTOS sources as well: https://github.com/apache/nuttx  See the RDDRONE-BMS772 board in the NuttX repository: https://github.com/apache/nuttx/tree/master/boards/arm/s32k1xx/rddrone-bms772  And the S32K1xx architecture specific logic:  https://github.com/apache/nuttx/tree/master/arch/arm/src/s32k1xx  I hope this helps you! Kind regards, Cis van Mierlo Re: RDDRONE-BMS772 Hi @cisvmierlo  Two more questions based on your answer... 1. Can PTA2 and PTA3 (connector J23) be configured as an I2C slave? On the software side, it seems to be possible, but want to make sure everything checks out in both hardware and software. 2. How do you configure LPI2C0_SCLS and LPI2C0_SDAS? Do you have any references on how to configure this in C code and/or through Model Based Development? I am currently using Model Based Development, but I do not see any peripherals with LPI2C0_SCLS and LPI2C0_SDAS. Additionally, the I2C configuration block only has the options for PTA2/PTA3 or PTB6/PTB7. I am not exactly sure how to activate this output.  Re: RDDRONE-BMS772 Hi @dmorvay , The connector J18 can be used for SMBUS / I2CS.  The SMBUS_SCL and SMBUS_SDA lines are connected to this connector. These lines are connector to PTA0 and PTA1, which support the LPI2C0_SCLS and /LPI2C0_SDAS peripheral. Kind regards, Cis van Mierlo Re: RDDRONE-BMS772 Hi @cisvmierlo  Another question regarding I2C communication: when configuring the BMS772 as a slave, should the pins for SDA/SCL be PTB6 and PTB7 respectively or PTA2 and PTA3 respectively? Looking at the schematics, it seems like it is actually neither of these two options, but instead PTA0 and PTA1. Hence, I am slightly confused on how to setup the board as a slave for I2C communication.  Re: RDDRONE-BMS772 Hello, The PSMNR70-30YLH MOSFETS that are recommended by NXP documentation unfortunately are not available to buy in the sites I tried. This is an issue because I can not test with safety the board.  I read in this community I can find it in Nexperia but the minimun quantity to order is 1500. I tried to look for another equivalent one but I cannot find it with the same characteristics. I don't know the tolerance or how much the MOSFET can differ. The MOSFET characteristics recommended by NXP are below. What other characteristics are tolerated or what other suitable characteristics can you recommend, please?  N-channel 30 V 0.82 mΩ, 300 A logic level MOSFET in LFPAK56 using NextPowerS3 technology Thank you very much Re: RDDRONE-BMS772 Thank you so much @cisvmierlo . I think there was an issue with the reset signal. Now it's working, so thank you! Re: RDDRONE-BMS772 Hi @DaveNXP , Do you have access to an oscilloscope? And could you measure the if there are pulses on the MCU reset line? Kind regards, Cis van Mierlo Re: RDDRONE-BMS772 Thank you for your answer, I already tried with the J2 connector(it is placed) thought JTAG lines, with the reset jumper and without it. And I still cannot connect to the target. What could I do? How could I check the Reset line is properly connected and the signal is ok. Thank you very much @cisvmierlo  Re: RDDRONE-BMS772 Hi @DaveNXP , Could you check de reset line of the debugger? If it is correctly connected to the MCU? Or if J2 is placed, maybe use this 2x5 connector to program the board via that programming header? If J2 is not placed, maybe you could solder a 2x5 pin header in to program the board via that route. Kind regards, Cis van Mierlo Re: RDDRONE-BMS772 Does anybody know how to factory reset the RDDRONE BMS board(or awaken it)? The board may be in deep sleep or in a state I cannot get it out. At first I could connect to the core (Cortex-M4 identified) but after this, when I tried to flash the firmware, I cannot connect to the target anymore(log copied in previous post). So I cannot send any command with J-Link Commander. The voltage of the J-Link debugger is 3.3V. I pressed the physical button while board powered but nothing changed and it does not wake up. This happened to the two RDDRONE boards I bought. Please, any help would be really appreciated. Thank you! @cisvmierlo @iaingalloway  Re: RDDRONE-BMS772 Hi, thank you for your answer. I tried pushing the SW1 button. I tried with the reset jumper and without it. I tried generating a reset pulse with a signal generator following the electrical specifications in the s32k1xx datasheet. https://www.nxp.com/docs/en/data-sheet/S32K-DS.pdf I checked all the voltages. If I connect the FTDI cable some garbage slash noise appears in the Tera Term console when I turn on and off the switch power supply. Re: RDDRONE-BMS772 When you use JLINK software and a debugger to connect to the BMS, one of the first things JLINK.exe prints out is the voltage on the MCU/debug port. It's possible that even with external power 22v or whatever, coming in to the BMS board, that the actual power supply feeding the MCU is not turned on. There is a tiny physical button on the BMS which may wake up the MCU power supply. https://nxp.gitbook.io/rddrone-bms772/user-guide/getting-to-know-the-hardware/board-organization Re: RDDRONE-BMS772 Hi Cis van Mierlo The debugger provides 3,3V. And the output of the power supply connected to the RDDRONE board input is 22,2V. I do not understand very well what the problem may be and what changes and tests I should do. I don't know any button to press or way to start it up again. I would really appreciate any help for this. Thank you. Kind regards. Re: RDDRONE-BMS772 Hi @DaveNXP, Could you check if the voltage is OK according to the debugger? Maybe the SW put the system in deep sleep and a button press is needed to start it up again. Kind regards, Cis van Mierlo Re: RDDRONE-BMS772 Thanks for the answer cisvmierlo, The thing is that at first I could correctly connect to the the core on the RDDRONE-BMS772 board, but after this first flash I cannot connect to core on the board anymore. So, I cannot send this 'h' command you recommend. Do you have any other ideas? Re: RDDRONE-BMS772 Hi @DaveNXP , It seems that you can connect to the core, but not erase nor flash it. Could you try to restart the J-Link commander and halt the core with the 'h' command? Kind regards, Cis van Mierlo Re: RDDRONE-BMS772 Hi, I have a problem with the RDDRONE-BMS772 board. I soldered the hardware "configuration pads" as recommended in the RDDRONE-BMS772 manual for a 6s battery. https://nxp.gitbook.io/rddrone-bms772/user-guide/getting-started-with-the-rddrone-bms772/configuring-the-hardware Then, I connected the RDDRONE-BMS772 board to a 22.2V power supply for the first time, the onboard LED turned on. I followed the steps in this guide from the "NXP Gitbook": https://nxp.gitbook.io/nxpmobilerobotics/flashing-guide/flashing-hovergames-boards/windows but after trying to flash the firmware bin file downloaded from the official github: https://github.com/NXPHoverGames/RDDRONE-BMS772 with the recommended J-LINK  debugger and I connected the cables as seen here: https://nxp.gitbook.io/hovergames/rddrone-fmuk66/connectors/debug-interface-dcd-lz/dcd-lz-breakout-board The flash failed (log below), and I cannot connect to the RDDRONE-BMS772 board anymore. Furthermore, the LED does not turn on either. I am trying to re-flash it, but I cannot get J-Link commander to connect to the RDDRONE-BMS772 anymore. If I try to access the board using an FTDI cable, I do not get any serial connection using Putty either. I am a bit confused as I do not understand if the problem is that the CPU is halted, or the CPU is in a RESET loop, the CPU waiting for a RESET signal, the CPU is "locked" and I have to unlock it, or if it is something else. Any help would be highly appreciated. This is the log I got from the J-Link Commander console, in case it is helpful: Type "connect" to establish a target connection, '?' for help J-Link>connect Please specify device / core. : S32K144 Type '?' for selection dialog Device> Please specify target interface: J) JTAG (Default) S) SWD T) cJTAG TIF>s Specify target interface speed [kHz]. : 4000 kHz Speed>1000 Device "S32K144" selected. Connecting to target via SWD InitTarget() start SWD selected. Executing JTAG -> SWD switching sequence. InitTarget() end - Took 55ms Found SW-DP with ID 0x2BA01477 DPIDR: 0x2BA01477 CoreSight SoC-400 or earlier Scanning AP map to find all available APs AP[2]: Stopped AP scan as end of AP map has been reached AP[0]: AHB-AP (IDR: 0x24770011) AP[1]: JTAG-AP (IDR: 0x001C0000) Iterating through AP map to find AHB-AP to use AP[0]: Core found AP[0]: AHB-AP ROM base: 0xE00FF000 CPUID register: 0x410FC241. Implementer code: 0x41 (ARM) Found Cortex-M4 r0p1, Little endian. FPUnit: 6 code (BP) slots and 2 literal slots CoreSight components: ROMTbl[0] @ E00FF000 [0][0]: E000E000 CID B105E00D PID 000BB00C SCS-M7 [0][1]: E0001000 CID B105E00D PID 003BB002 DWT [0][2]: E0002000 CID B105E00D PID 002BB003 FPB [0][3]: E0000000 CID B105E00D PID 003BB001 ITM [0][4]: E0040000 CID B105900D PID 000BB9A1 TPIU Initializing 61440 bytes work RAM @ 0x1FFF8000 Reset: Halt core after reset via DEMCR.VC_CORERESET. Reset: Reset device via AIRCR.SYSRESETREQ. Memory zones: Zone: "Default" Description: Default access mode Cortex-M4 identified. J-Link>erase No address range specified, 'Erase Chip' will be executed 'erase': Performing implicit reset & halt of MCU. Reset: Halt core after reset via DEMCR.VC_CORERESET. Reset: Reset device via AIRCR.SYSRESETREQ. Erasing device... ****** Error: Failed to erase sectors. J-Link: Flash download: Total time needed: 1.490s (Prepare: 0.603s, Compare: 0.000s, Erase: 0.885s, Program: 0.000s, Verify: 0.000s, Restore: 0.002s) ****** Error: Failed to restore target. RAMCode never stops ERROR: Erase returned with error code -5. J-Link>loadbin "C:\Documents\RDDRONE-BMS772-main\Binary\nuttx.bin" 0x0 'loadbin': Performing implicit reset & halt of MCU. Reset: Halt core after reset via DEMCR.VC_CORERESET. Reset: Reset device via AIRCR.SYSRESETREQ. Reset: SYSRESETREQ has confused core. Found SW-DP with ID 0x2BA01477 DPIDR: 0x2BA01477 CoreSight SoC-400 or earlier AP map detection skipped. Manually configured AP map found. AP[0]: AHB-AP (IDR: Not set) AP[0]: Skipped. Could not read CPUID register Attach to CPU failed. Executing connect under reset. DPIDR: 0x2BA01477 CoreSight SoC-400 or earlier AP map detection skipped. Manually configured AP map found. AP[0]: AHB-AP (IDR: Not set) AP[0]: Skipped. Could not read CPUID register Could not find core in Coresight setup Reset: Using fallback: VECTRESET. Reset: Halt core after reset via DEMCR.VC_CORERESET. Reset: Reset device via AIRCR.VECTRESET. Reset: VECTRESET has confused core. Reset: Using fallback: Reset pin. Reset: Halt core after reset via DEMCR.VC_CORERESET. Reset: Reset device via reset pin Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?). Reset: Reconnecting and manually halting CPU. Found SW-DP with ID 0x2BA01477 DPIDR: 0x2BA01477 CoreSight SoC-400 or earlier AP map detection skipped. Manually configured AP map found. AP[0]: AHB-AP (IDR: Not set) AP[0]: Skipped. Could not read CPUID register Attach to CPU failed. Executing connect under reset. DPIDR: 0x2BA01477 CoreSight SoC-400 or earlier AP map detection skipped. Manually configured AP map found. AP[0]: AHB-AP (IDR: Not set) AP[0]: Skipped. Could not read CPUID register Could not find core in Coresight setup CPU could not be halted Reset: Core did not halt after reset, trying to disable WDT. Reset: Halt core after reset via DEMCR.VC_CORERESET. Reset: Reset device via reset pin Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?). Reset: Reconnecting and manually halting CPU. Found SW-DP with ID 0x2BA01477 DPIDR: 0x2BA01477 CoreSight SoC-400 or earlier AP map detection skipped. Manually configured AP map found. AP[0]: AHB-AP (IDR: Not set) AP[0]: Skipped. Could not read CPUID register Attach to CPU failed. Executing connect under reset. DPIDR: 0x2BA01477 CoreSight SoC-400 or earlier AP map detection skipped. Manually configured AP map found. AP[0]: AHB-AP (IDR: Not set) AP[0]: Skipped. Could not read CPUID register Could not find core in Coresight setup CPU could not be halted Reset: Failed. Toggling reset pin and trying reset strategy again. Found SW-DP with ID 0x2BA01477 DPIDR: 0x2BA01477 CoreSight SoC-400 or earlier AP map detection skipped. Manually configured AP map found. AP[0]: AHB-AP (IDR: Not set) AP[0]: Skipped. Could not read CPUID register Attach to CPU failed. Executing connect under reset. DPIDR: 0x2BA01477 CoreSight SoC-400 or earlier AP map detection skipped. Manually configured AP map found. AP[0]: AHB-AP (IDR: Not set) AP[0]: Skipped. Could not read CPUID register Could not find core in Coresight setup Reset: Halt core after reset via DEMCR.VC_CORERESET. Reset: Reset device via AIRCR.SYSRESETREQ. Reset: SYSRESETREQ has confused core. Found SW-DP with ID 0x2BA01477 DPIDR: 0x2BA01477 CoreSight SoC-400 or earlier AP map detection skipped. Manually configured AP map found. AP[0]: AHB-AP (IDR: Not set) AP[0]: Skipped. Could not read CPUID register Attach to CPU failed. Executing connect under reset. DPIDR: 0x2BA01477 CoreSight SoC-400 or earlier AP map detection skipped. Manually configured AP map found. AP[0]: AHB-AP (IDR: Not set) AP[0]: Skipped. Could not read CPUID register Could not find core in Coresight setup Reset: Using fallback: VECTRESET. Reset: Halt core after reset via DEMCR.VC_CORERESET. Reset: Reset device via AIRCR.VECTRESET. Reset: VECTRESET has confused core. Reset: Using fallback: Reset pin. Reset: Halt core after reset via DEMCR.VC_CORERESET. Reset: Reset device via reset pin Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?). Reset: Reconnecting and manually halting CPU. Found SW-DP with ID 0x2BA01477 DPIDR: 0x2BA01477 CoreSight SoC-400 or earlier AP map detection skipped. Manually configured AP map found. AP[0]: AHB-AP (IDR: Not set) AP[0]: Skipped. Could not read CPUID register Attach to CPU failed. Executing connect under reset. DPIDR: 0x2BA01477 CoreSight SoC-400 or earlier AP map detection skipped. Manually configured AP map found. AP[0]: AHB-AP (IDR: Not set) AP[0]: Skipped. Could not read CPUID register Could not find core in Coresight setup CPU could not be halted Reset: Core did not halt after reset, trying to disable WDT. Reset: Halt core after reset via DEMCR.VC_CORERESET. Reset: Reset device via reset pin Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?). Reset: Reconnecting and manually halting CPU. Found SW-DP with ID 0x2BA01477 DPIDR: 0x2BA01477 CoreSight SoC-400 or earlier AP map detection skipped. Manually configured AP map found. AP[0]: AHB-AP (IDR: Not set) AP[0]: Skipped. Could not read CPUID register Attach to CPU failed. Executing connect under reset. DPIDR: 0x2BA01477 CoreSight SoC-400 or earlier AP map detection skipped. Manually configured AP map found. AP[0]: AHB-AP (IDR: Not set) AP[0]: Skipped. Could not read CPUID register Could not find core in Coresight setup CPU could not be halted CPU could not be halted ****** Error: Failed to halt CPU. CPU could not be halted Downloading file [C:\Documents\RDDRONE-BMS772-main\Binary\nuttx.bin]... CPU could not be halted ****** Error: Failed to restore target. RAMCode never stops Failed to erase sectors. Unspecified error -1 J-Link> Re: RDDRONE-BMS772 Hi @dmorvay , The I2C voltage level is 3.3V. This is the MCU voltage domain as well. But there is 5V on the board which can be used to supply a display with 5V. The schematic of the RDDRONE-BMS772 can be downloaded from the NXP webpage (click on design files or scroll down to the design resources): https://www.nxp.com/design/designs/smart-battery-management-for-mobile-robotics:RDDRONE-BMS772  Kind regards, Cis van Mierlo Re: RDDRONE-BMS772 Hi @cisvmierlo, I appreciate the information! I will try again on the display. For reference, what is the I2C transmission voltage on the BMS772? Is it 5V or 3.3V I2C? I don't want to hook up a 5V I2C (say Arduino) and then damage the board if it is 3.3V.  Re: RDDRONE-BMS772 Hi @dmorvay, Great that soldering the correct jumpers solves the cell voltage issue!  For the OLED display, as I said I'm not familiar with the Model Based Design Toolbox examples.  Maybe they mean the RGB-LED which is on the board with the LED example? The display delivered with the kit should support 3.3V. But if you are interested in an BMS example project written in C with the NuttX RTOS (this includes the display to showcase battery values), see the example here:  https://github.com/NXPHoverGames/RDDRONE-BMS772 PS: This is a graphical display, not a textual display. So each character needs to be drawn according to a specific font that is used. Kind regards, Cis van Mierlo Re: RDDRONE-BMS772 @cisvmierlo That seemed to do the trick! It appears that I failed to read that portion of the documentation about soldering those jumpers.  Another question regarding the OLED screen, I tried building and flashing the LED example onto the board, but the screen would not turn on. Is there anything special I need to do there? I was reading 3.3V on J23 between VCC and GND, but when I plugged the screen in, it would not turn on. Any suggestions? I didn't get a chance to check the D34 and D35 diodes today, but do those need to be moved if I am reading 3.3V?  Re: RDDRONE-BMS772 Hi @dmorvay,  I do not have experience with the Model-Based Development toolbox yet, so in this regard I can not check it.  For the HW: Could you confirm that the soldered jumpers are SJ6, SJ10, SJ11 and SJ12 for 3S? And the cell voltage filters are correctly in place:  Kind regards, Cis van Mierlo Re: RDDRONE-BMS772 Hello, I was experimenting with the BMS772 this evening and was trying to display cell voltages. I have a 3s setup and for some reason one cell is consistently reading higher than the others. I confirmed via a multimeter that the cells are all roughly the same value. I tried this with two different battery packs as well. See my attached screenshot for more information. Notice, the BMS is consistently reading ~0.7 greater than the others. I am using Model-Based Development with a J-Link Debugger in FreeMaster. Any advice would be appreciated! Re: RDDRONE-BMS772 Hi, Does BMS772 board support Pixhawk Cube Orange Autopilot? I have successfully communicated with other UAVCAN devices such as Zubax ESC, Packet digital MPPT. links given below. But it didn't work with BMS772. https://packetdigital.com/power-products/maximum-power-point-tracker/ https://files.zubax.com/products/com.zubax.telega/Zubax_Myxa_Datasheet.pdf Also, Does BMS772 board support classical CAN (CAN 2.0) protocol? If yes, I would like to test it with Microchip's CAN bus analyzer. Please clarify. Thanks in advance.. Re: RDDRONE-BMS772 This isn't helpful according to your question, but the code was developed using a segger jlink family device. If you are a student and this is non-commercial use, you can use one of the lower cost jlink-edu from suppliers like Adafruit. Re: Request for Register Map for NXP RDDrone-BMS772 The best reference for what is implemented is by referring to the actual code. Which is published and open source. Re: Request for Register Map for NXP RDDrone-BMS772 The Smart Battery System Specification ended up being helpful. The spec sheet can be found here: http://sbs-forum.org/specs/sbdat110.pdf Request for Register Map for NXP RDDrone-BMS772 Request for Register Map for NXP RDDrone-BMS772 Hi all, I recently purchased the NXP RDDrone-BMS772 battery management system for my project, and I am having trouble communicating with the device via I2C. I have been trying to read the registers of the device, but without a register map, it's difficult to know which registers to access. I was wondering if someone could please provide me with a register map for the RDDrone-BMS772, or point me in the direction of where I could find one. I believe that having a register map would greatly help me to communicate with the device and extract the information that I need. Thank you for your help in advance. Best regards, Re: RDDRONE-BMS772 Hi @cisvmierlo, Thanks for your help. I could solve Under voltage fault problem. Now I want to see DroneCAN / UAVCAN messages / parameters sent by BMS in some software tool. Do you have some software GUI tool to see CAN messages from BMS? I tried to see messages with DroneCAN GUI tool with BMS772 connected to Orange Cube Autopilot. But I am not successful. Mission planner software didn't recognize BMS in SLCAN mode. Where as Cube orange detects other UAVCAN devices such as Zubax ESC, Packet digital MPPT. Also, Should I change DroneCAN static node ID to other than 255 for it to work? NXP's UCAN based nodes are not available for purchase in India. Also, please clarify whether Over current, output short circuit protection is available on BMS? Please clarify the above. Thanks again for your great support. ... Re: RDDRONE-BMS772 Hi @Prince1, Great that the communication issue has been resolved! For the other questions: "Yes, CLI shows "Cell under voltage detected!" and display shows 11.26V although fluke instrument measures 11.7V."  The display shows v-out. Which is measured via a resistor divider on the output with 1% tolerance. Meaning that you could have a 0.946V difference on 26V, just because of the resistor tolerances. So it could be that this is a little off with the actual value. In the current SW example there is no option to fine tune this measurement. What you could do is: look at v-batt or add all the cell voltages together (which is the most precise). Vtot = v-cell1 + v-cell2 + ..  "1. It looks if cell voltages < 3.8V, it goes to Deep_Sleep. Will it happen even if load is connected on J5? I mean, if load is connected disconnecting the battery at 3.8V is too early when cell cutoff voltage is 3V." So the default cell under voltage (for a LiPo battery) is set at 3V. You could check this setting via the UART interface via:  bms get v-cell-uv You could set the cell under voltage you think is suitable with: "bms set v-cell-uv x.xV" After setting parameters, do not forget to save it to flash with "bms save". For more information on which parameters there are, please have a look at chapter 8.2 of BMS772_releaseNotes_5.0.pdf. But I would check the cell voltages via the UART connection, so you can see which cell has a problem.  You can use: "bms get all" (gets all parameters),  "bms show all 1" (updates the battery values), "bms show top 1" (updates the battery values without scrolling). "2. Is it possible to reduce the voltage measurement error in BMS?" As stated in the beginning, there is no parameter for correcting the v-out voltage.  But feel free to adjust the SW yourself so for example v-batt is displayed on the display instead of v-out. Kind regards,  Cis van Mierlo Re: RDDRONE-BMS772 Hi @cisvmierlo , Thanks a lot. You solved my problem. After rectifying J19 connections, CLI and Display worked. Yes, CLI shows "Cell undervoltage detected!" and display shows 11.26V although fluke instrument measures 11.7V. 1. It looks if cell voltages < 3.8V, it goes to Deep_Sleep. Will it happen even if load is connected on J5? I mean, if load is connected disconnecting the battery at 3.8V is too early when cell cutoff voltage is 3V. 2. Is it possible to reduce the voltage measurement error in BMS? Kindly answer the above questions. Thanks.. Re: RDDRONE-BMS772 Hi @Prince1, I think I found the issue with the communication on BMS1.  The black wire is connected to J19 pin 1, which is 3.3V and not connected to ground. For ground, you need to connect the black wire to J19 pin 7 (other side of the connector).  Light blue is now connected to J19 pin 5 (SWD_CLK) and yellow is now connected to J19 pin 6 (RST_N). I think you need to swap the connections on the connector J19. I will come back on the other PCB later. Kind regards, Cis van Mierlo Re: RDDRONE-BMS772 Hi @CisvanMierlo, I have attached images of two BMSes, 1st one: LED blinks in red for 1 min before going to Deep_Sleep. 2nd one: has over heat issue and LED doesn't turn ON. Though I have used 5 pin cell terminal connector, I have not connected 4S pin (5th pin open) / wire. So, 5 pin connector is used for 3S battery. Voltages are correct at JP1 connector. Today I charged battery to 11.7V and tested still same result. Thanks.. Re: RDDRONE-BMS772 Hi @Prince1, Only with a cell under voltage detection it will go to deep-sleep after 1 min. Maybe there is something with the cell connections. could you perhaps share images of this board as well (top and bottom)? Kind regards, Cis van Mierlo Re: RDDRONE-BMS772 Hi Cis van Mierlo, BMS default V-cell-UV may be 3V, but my all battery cell voltages are beyond 3.8V and 3S pack voltage is 11.5V. I think under voltage is not the reason for BMS going into Deep_Sleep. Please mention what could be other reasons for BMS LED blinking in red for 1min and then going into Deep_Sleep. D34 is placed, D35 not placed. Still Display doesn't turn on. Display pin numbers are connected as suggested. I will share the images of other BMS board with over heating issue. Thanks.. Re: RDDRONE-BMS772 Hi @Prince1, "BMS LED is blinking in red colour and then goes OFF after around 1min. I think it goes to SLEEP." This indicates that there is a cell under-voltage detected (based on default battery technology: LiPo). When this happens, the BMS goes to DEEP_SLEEP after t-fault-timeout (60s default) in order to preserve the battery with its lowest power mode.  In that DEEP_SLEEP state the MCU (and SBC) is turned off, so no communication is possible after that 1 min. The button is press (or a re-power) is the only thing to wake the BMS from the DEEP_SLEEP state. So it could be that there is no communication because the BMS entered the DEEP_SLEEP. Or there would be something with the connection.  For the display to turn on during initialization, could you maybe check that D34 is placed instead of D35? For the other BMS setup, the SBC overheating and LED not turning on, indicates that there might be a short on the 3.3V domain (shorted to gnd). Could you maybe show both of your boards (top and bottom side)? Kind regards, Cis van Mierlo Re: RDDRONE-BMS772 Hi GeraldP, I have done the following on a new BMS, SJ6, 10, 11, 12 are shorted for 3S configuration. 3S LiPo battery is connected to J4 and their cell balancing wires connected to JP1 pins 5, 4, 1 of FTDI USB UART are connected to pins 2, 3, 7 of J19 respectively and then connected to PC 115k2 8n1, Parity: None, Flow: None configured in COM port properties and Tera Term The result is as follows, BMS LED is blinking in red colour and then goes OFF after around 1min. I think it goes to SLEEP. BMS output voltage at J5 is zero (load is not connected) Tera Term window displays blank screen and doesn't take keyboard input Display connected to J23 doesn't turn ON Kindly help me in sorting out above issues. I tried the same things on another BMS, in which LED doesn't turn ON and SBC chip is getting over heated. Thanks.. Re: RDDRONE-BMS772 Does anyone know where can I purchase other suitable debugger for NXP RDDRONE-BMS apart from J-Link or PEMicro ?? Thank you. Re: RDDRONE-BMS772 Hi GeraldP, Thanks for your help. I will try the way you suggested. Re: RDDRONE-BMS772 Hi @Prince1, the SW will just report an error and power out will be not enabled if you have a battery connected that has different cell numbering than configured. Battery needs to be connected to be able to configure the BMS. So the way to setup the BMS is: - connect your UART adapter and open terminal SW with 115k2 8n1 serial port setting. - Connect balancer and main power connector of battery to the BMS - see bootup sequence First start-up - RDDRONE-BMS772 (gitbook.io) - configure the bms via command line Command Line Interface (CLI) - RDDRONE-BMS772 (gitbook.io)     bms set  Parameters of the BMS - RDDRONE-BMS772 (gitbook.io) - finish with bms save if you type reboot the BMS will reboot with correct settings and will activate output in case no errors. Re: RDDRONE-BMS772 Hi, I have PL2303HX USB To TTL(Serial) Converter which provides 3.3V on Tx, Rx and GND. https://robu.in/product/pl2303-pl2303hx-usb-ttl-module-5-pin/   With this Can I attempt software reconfiguration? PL2303HX will be inserted in USB port and its TX, RX, GND pins are connected to respective pins in J19 port. Do I need to connect battery also to BMS (to J4) to power it's circuit? If so, 4S or 3S battery? As in my BMS, 4S cell terminal connector is soldered in JP1 and SJ3, SJ7, SJ11 and SJ12 are connected, but its factory default configuration in software is 3S. So, I am confused. Thanks.. Re: RDDRONE-BMS772 Hi @Prince1,  Yes you only need to connect GND, TX and RX as seen in this screenshot: Keep in mind that a USB-TTL-3V3 is used, this ensures 3.3V logic level on the RX and TX pins. Kind regards, Cis van Mierlo Re: RDDRONE-BMS772 Hi iaingalloway, Thanks for your reply. I want to change the BMS configuration from default 3S to 4S and also change battery chemistry through serial console. Is FTDI type USB-UART cable connected to JST GH 7 pin connector (only Tx, Rx, GND pins) is sufficient for this? I am also trying to get J link EDU mini debugger to update firmware, but it's lead time is 40 weeks. So, Just trying to update configuration parameters as of now. Thanks.. Re: RDDRONE-BMS772 I know this is now an old post, but I've cross posted and  asked the model based design team to have a look here. https://community.nxp.com/t5/Model-Based-Design-Toolbox-MBDT/RDDRONE-BMS771-MBDT-question/m-p/1586198#M7996 Re: RDDRONE-BMS772 Note also there has been some work done in NuttX/PX4 on CAN bootloaders. But these are incomplete at this time. Re: RDDRONE-BMS772 I wanted to note that there are also additional GPIO on the board that were allocated for this type of function to be added in the future as per a proposed DroneCode standard. There were some other potential for added features here, including identifying the battery to the vehicle etc. In addition to code needing to be written, These are located on a separate header and would need to be asserted on plugging in the battery to a drone or vehicle.  You will need to refer to the schematics on NXP.com for the details. I am referring to the header J21 here:     Re: RDDRONE-BMS772 Note that if you want to just use the serial console to see what is going on internally (and not reprogram and debug the board) Then you can buy any FTDI type USB-UART cable (or use a PC with a UART) to connect a serial console to the BMS772. Normally this is broken out on the DCD-LZ board so it can be plugged in easily. Here is the type of cable you would buy at Amazon or Digikey or whereever: https://www.digikey.com/en/products/detail/ftdi-future-technology-devices-international-ltd/TTL-234X-3V3/6823715 You would then use a JST-GH connector to attach to the RX TX and GND pins of the DCD-LZ interface on the BMS - do NOT connect the power from the FTDI cable to the DCD-LZ: The pinout is shown here: https://nxp.gitbook.io/hovergames/rddrone-fmuk66/connectors/debug-interface-dcd-lz/dcd-lz-breakout-board#pinout Re: RDDRONE-BMS772 Thank you @cisvmierlo. Very useful information. Re: RDDRONE-BMS772 Note you will need a 0.50" header to solder into J2 if you want to use it. Re: RDDRONE-BMS772 J2 is a socket for a standard 10/9 pin debug header that will work with any Segger JLINK device. You can also make a cable to plug into the DCDLZ port and connect to a FTDI 3v3 USB2UART cable. https://www.amazon.com/Pre-Crimped-Connectors-Pixhawk2-Pixracer-Silicone/dp/B07PBHN7TM/ref=sr_1_3?crid=GL7B8ZZMTG79&keywords=jst-gh&qid=1673558988&sprefix=jst-gh%2Caps%2C147&sr=8-3 As noted, these items are included with some of the other development kits and can be re-used here.  Re: RDDRONE-BMS772 Hi @Prince1,  Let me check internally about the availability of this adapter board. Here is some more information about the DCD-LZ adapter board, including the schematic:  https://nxp.gitbook.io/hovergames/rddrone-fmuk66/connectors/debug-interface-dcd-lz/dcd-lz-breakout-board  I do know that they are usually part of a kit, I did find this UCAN board where you have the option to buy the KIT-UCANS32K1SIC. This kit includes 2x DCD-LZ adapters, 2x FTDI-USB cable and 1x Segger Jlink mini EDU debugger (program and debug) as well. Link to the KIT-UCANS32K1SIC: https://www.nxp.com/products/interfaces/can-transceivers/can-signal-improvement/can-sic-evaluation-board:UCANS32K1SIC  Kind regards, Cis van Mierlo Re: RDDRONE-BMS772 Hi @Airobot-Dynamics,  In the following NXP community page it is stated that the documentation and software is available on DocStore. It also explains how to get access to DocStore. So I believe the A1007 is available under NDA only. Link to the NXP community page: https://community.nxp.com/t5/Other-NXP-Products/OM67201UL-driver-A1007/m-p/1447573  If you are looking to build something yourself, I would recommend to look at the common available NXP IoT Security and Authentication Portfolio: https://www.nxp.com/iotsecurity For example, the SE050 or SE051 is a greatly supported device, with lots of use cases already implemented. If you would like to develop on a board with an SE050 and a similar MCU (S32K146 instead of S32K144). The UCANS32K146 might be an interesting product. Link to the SE050: https://www.nxp.com/products/security-and-authentication/authentication/edgelock-se050-plug-trust-secure-element-family-enhanced-iot-security-with-high-flexibility:SE050  Link to the UCANS32K146: https://www.nxp.com/design/development-boards/automotive-development-platforms/s32k-mcu-platforms/s32k146-uavcan-v1-and-mavcan-development-system:UCANS32K146  I hope this answers your questions, kind regards, Cis van Mierlo Re: RDDRONE-BMS772 A1007 Secure Authenticator Hi community, I have just started developing with the BMS772. However, I can not find any information on the A1007 IC. I can not even find this IC on the NXP site of any of our usual suppliers, Digi-Key etc.  Is this IC obsolete?  If so, are there any suggested alternative. Thanks Re: RDDRONE-BMS772 Hi, Thanks for your quick reply. Unfortunately, I couldn't find distributor to purchase DCD-LZ adapter in India. I don't have a hover games kit as well. Can you suggest any alternative adapter which is widely available? Thanks. Re: RDDRONE-BMS772 Hi @Prince1, Indeed you would need to configure the software accordingly. This can be done as followed: 1. Hook up the DCD-LZ adapter to the BMS772 board using the 7-pins JST-GH cable.  2. Hook up the DCD-LZ adapter to a laptop or PC with a FTDI USBUART-3V3 cable.  3. Connect to the BMS772 over a serial interface, like PuTTY or TeraTerm (115200 Baud). 4. Type "bms help" to get the help for the Command Line Interface (CLI). 5. Type "bms get all" to get all the parameters and the values associated with those parameters. 6. Change the variable you would like to change, in this case n-cells to 4, type: "bms set n-cells 4"  7. To make sure the parameters are saved to flash, type: "bms save"  8. After the new parameter settings, you could either press the button or type: "bms reset" to reset the fault. The CLI is very useful as it will indicate what caused the error.  Here are some useful links to get started: A link about setting up the CLI: https://nxp.gitbook.io/rddrone-bms772/user-guide/getting-started-with-the-rddrone-bms772/using-the-command-line-interface-cli  A link about using the CLI: https://nxp.gitbook.io/rddrone-bms772/software-guide-nuttx/command-line-interface-cli  A link with a list of parameters: https://nxp.gitbook.io/rddrone-bms772/software-guide-nuttx/untitled-1  Chapter 7 of the release notes (rev. 5) is useful as well as this contains a picture of the DCD-LZ adapter with the 7-pins JST GH cable and the USB-TTL-3V3 cable connected to it. Chapter 8 includes the parameters of the BMS772. I would recommend the update the software to the latest binary.  The latest binary can be found at: https://github.com/NXPHoverGames/RDDRONE-BMS772/tree/main/Binary  Instructions can be found in chapter 7 of the release notes, on the code repository or on the gitbook: https://nxp.gitbook.io/rddrone-bms772/user-guide/getting-started-with-the-rddrone-bms772/flashing-firmware-to-the-rddrone-bms772  Keep in mind that after programming, you need to re-configure the parameters again as these get overwritten. I hope this helps, kind regards, Cis van Mierlo Re: RDDRONE-BMS772 Hi, I bought a new RDDRONE-BMS772 board and want to use it for 4S LiPo battery pack. I have soldered Cell terminal connector and Solder jumper pins (SJ) for 4S. After connecting to 4S pack, When I measured the output voltage it is 0V. I don't know why. Shall I do any configuration change(for 4S) in the software also? If so, how? Please reply. Thanks in advance. Re: RDDRONE-BMS772 Hi @Ch_Han, When the BMS is in the DEEP_SLEEP state it needs to limit the power the BMS is using itself, in order to preserve the battery the most. This is done by setting the components powered by the battery in a deepsleep / sleep state as well and by disabling the voltage domains (3.3V and 5V are turned off), amongst others, powering off the microcontroller, which is supplied by this 3.3V. To initiate a wake for the SBC (to turn on the 3.3V again which will power the microcontroller), I believe the SW has only configured that the wake pin of the SBC, issues an SBC wake. To do that, the button needs to be pressed or J22 needs to be shorted. But I do believe a wake-up via CAN could be enabled in the SW, as the SBC is in a sleep state and still powered by the battery. This is however not enabled by the current SW example and I do not know the HW requirements for this. If you would like to add this functionality, you could check the datasheet of the SBC and the sbc.c and sbc.h files of the public BMS SW example for this board. The datasheet of the SBC can be found here: https://www.nxp.com/products/power-management/pmics-and-sbcs/mini-sbcs/mini-high-speed-can-system-basis-chip:UJA1169ATK  Kind regards, cisvmierlo Re: RDDRONE-BMS772 Thank you for your answer. Then if the battery is in storage with the BMS in DEEPSLEEP state, can the BMS detect when the output is connected to go back to NORMAL or is the only way out of DEEPSLEEP by pushing the button? Regards, Re: RDDRONE-BMS772 Hi @OGUZ1, I wanted to let you know that the RDDRONE-BMS772 board is now supported in the NXP Model-Based Design Toolbox (MBDT) for S32K1xx - version 4.3.0. Here is the Product Release Announcement: https://community.nxp.com/t5/NXP-Model-Based-Design-Tools/NXP-Model-Based-Design-Toolbox-for-S32K1xx-MCUs-version-4-3-0/ta-p/1549163  The NXP MBDT includes an integrated Simulink ® -embedded target supporting NXP MCUs for direct rapid prototyping and built-in support for software- and processor-in-the-loop (SIL and PIL) development. https://www.nxp.com/design/automotive-software-and-tools/model-based-design-toolbox-mbdt:MBDT  Kind regards! Re: RDDRONE-BMS772 Hi @Ch_Han, Please see https://github.com/NXPHoverGames/RDDRONE-BMS772/ for the release notes. This describes the state machine of the BMS example software. The SLEEP state is not for storage, as in this example the output power is still enabled in this SLEEP state. For storage, the BMS should indeed go to the DEEPSLEEP state, where the output power is disabled (power switch is open) and the current is as little as possible. In chapter 8 of the release notes, the parameters are described to control the BMS. If you set parameter self-discharge-enable to 0. You could go to the DEEPSLEEP state without discharging the battery cells to storage voltage. Keep in mind that this might not be good for the battery cells if they are at a high voltage for a long time. In the self-discharge state, the BMS will use the balancing current to discharge all the cells to be less than the set storage voltage (with margin). In SLEEP state, the switch is always closed in this example, enabling the output power. Thus, it could detect a load by measuring current. I usually work with a lab power supply to charge the batteries. PS: You could develop your own software or adapt the SW for your needs based on the open source example on https://github.com/NXPHoverGames/RDDRONE-BMS772/. Hopefully this answers your questions, kind regards, cisvmierlo Re: RDDRONE-BMS772 Hello @iaingalloway @cisvmierlo , I plan to use the BMS772 with 6s LiPo batteries, and have questions concerning the charge and discharge. 1- Is there a way to store the batteries without discharging? I see that before going into DEEPSLEEP state where the gates are open, the BMS must go through a SELF-DISCHARGE state; or if the BMS is in SLEEP state the gates are closed which also leads to discharging. 2- What is the physical process of the self-discharge? 3- Has measuring the impedance through CAN been thought of to detect if an output is connected? For example to know if gates should be open or closed in SLEEP state. 4- Is there a recommended charger to charge the batteries with a limited current? Or at least which one do you use usually? Thank you. Re: RDDRONE-BMS772 Hi @vikrantj, Since you are doing this for a school project, I think you are able to buy a J-Link EDU (mini). This is a cheaper version of the normal J-Link meant for educational purposes. Here is a guide on how to use the J-Link EDU (mini) to flash the RDDRONE-BMS772: https://nxp.gitbook.io/nxpmobilerobotics/flashing-guide/flashing-hovergames-boards.  Would this help you? Kind regards, Cis van Mierlo  Re: RDDRONE-BMS772 Hello @vikrantj, I did not have the chance to use this board yet. But having a look at the schematic, the easiest way to flash this board directly from Simulink without using a JTAG all the time is to use the RAppID bootloader, over the UART. Of course, you have to flash the bootloader once using a JTAG but once you have the bootloader written in the flash memory, you can use the Serial, directly from Simulink. You can find a suitable bootloader in the toolbox, under tools\BootLoader\RBF_Files the  S32K144_S32DS_UART1_CAN0.rbf which uses the pins PTC6 and PTC7 over the DCD-LZ. And here, you can use an external USB2Serial converter. Also, the CAN0 can be used to deploy the code on the board, but you need to use the RAppID bootloader app, and a compatible CAN tool. Let me know if Serial is a good option for you. Regards, Marius Re: RDDRONE-BMS772 Hello,  I am using the RDDRONE-BMS772 to build a 3s li-ion cell cycler. I wanted to be able to flash the program to the S32K on the board using a CAN bus. I was wondering if there is any way to do this. Or is using a debugger the only way to flash the program? If there are any other alternatives you could suggest I would appreciate it. This is for a school project and hence I need to keep the costs (and the complexity) low.  @OGUZ1 , @iaingalloway, @mariuslucianand  I would love to know your thoughts about this. Re: RDDRONE-BMS772 Hi, @cisvmierlo  Thank you very much for your reply. Yes, I'm using SPI0 but I can't see any effect. I always read something like 2.7Volt from pin V2. I always read 3.3 volts from V1 pin. I still read the same values when I press the reset button. I couldn't figure out what it means. I tried all the configurations. Vbat and Wake pins are the same value in SBC. When I press reset, the Wake pin drops to 0. 3.3 volts is always going to the SBCWake pin of the processor. @mariuslucianand @constantinrazva Re: RDDRONE-BMS772 Hi @OGUZ1,  Sorry I do not have experience using MBDT in Matlab / Simulink. For the help with the model based design toolbox and SBC 5V problems. @mariuslucianand could you help @OGUZ1 further with this? It could be that the UJA1169 configuration might be meant only for the S32K144 evb board, which could be different than what should be used on the RDDRONE-BMS772. For example, on the S32k144 evb LPSPI1 is used to communicate with the SBC. While on the RDDRONE-BMS772 LPSPI0 is used. Could you verify that the correct SPI bus 0 is used to communicate with the SBC? According to @constantinrazva the SBC driver is located in the external devices. Could you verify that you are using this SBC block? If you are interested to see how to set the SBC using C code, here is an example: https://github.com/NXPHoverGames/RDDRONE-BMS772/blob/main/src/sbc.c This enables the 5V in normal operation of the SBC.  For the display, we have example code how to use the display with the NuttX RTOS. See https://github.com/NXPHoverGames/RDDRONE-BMS772/blob/main/src/display.c.  It uses the characters and drivers from this NuttX RTOS. The display itself is a SSD1306 I2C display that works at both 5V and 3.3V. I believe there are many C examples of how to work with this kind of display.  For example: https://github.com/adafruit/Adafruit_SSD1306  For MATLAB maybe these sources would be able to help as well: https://nl.mathworks.com/matlabcentral/fileexchange/50766-ssd1306-hex-bitmap-creator?s_tid=srchtitle or https://nl.mathworks.com/matlabcentral/answers/512483-how-to-control-ssd1306-128x32-oled-display-in-matlab  Kind regards and have a nice weekend, Cis van Mierlo Re: RDDRONE-BMS772 Hi, @iaingalloway @cisvmierlo  I want to run the screen via Matlab/Simulink. Can you share any example with me? I can see the battery values with Matlab/Simulink. I want to use CAN communication but I still can't get 5V from SBC. I still could not get 5V output from SBC. Are you interested in me? Best Regards! Re: RDDRONE-BMS772 Hi @OGUZ1, Please see https://github.com/NXPHoverGames/RDDRONE-BMS772/ for the NuttX RDDRONE-BMS772 BMS example. Documentation, source code, binary and a manual can all be found at that website. It uses the POSIX compliant RTOS NuttX. That example contains the things like SSD1306 display support and configured SBC for 5V. If Matlab/Simulink, FREEMASTER or something else is used to re-program the boards, there might be different software running on the microcontroller and thus it won't have the correct behavior and functions. You are free to re-program this board/microcontroller with the software you want (or make!), but make sure that what you program is what you are looking for. If you would like to create your software, you could create it based on sources from https://github.com/NXPHoverGames/RDDRONE-BMS772/. This could help you get started with NXP components like the SBC (UJA1169), the BCC (MC33772B) or the NTAG5 boost NFC chip. If you want to program the NuttX BMS example, there is already a binary on that website/repository which you could easily program using the J-Link commander application (for windows (or JLinkExe on Linux)) and a J-Link programmer. Re: RDDRONE-BMS772 Hi , @iaingalloway @cisvmierlo  I programmed the RDDRONE - BMS772 board with Matlab/Simulink. I see all values in FreeMaster. I have a few questions... 1) I want to run the SSD1306 screen on the card. I changed the D34 and D35 diodes. 3.3Volt appears on the screen, but it does not work. Could you help ? 2) We give 1 to the Gate leg of the power mosfets of the card from the software and we get the output voltage. Why do we still get output voltage when we give logic 0 from the software? (We tested it with the load connected.) 3)Although we operate the SBC in normal mode, we cannot get 5V output. We only get 3V3. We are using sbc_uja1169_s32k_config. Although we activate the V2/VEXT config section in the regulator section, we cannot get output from V2. What is the reason of this? Can you help us? Re: RDDRONE-BMS772 Hi @Prince1, First of all, best wishes for this new year! My apologies for the late response, we had some time off. To answer your questions: The BMS772 comes with pre-installed example software, but you might want to update it to the latest version. But keep in mind that it is a development platform with open source example software. This software is opensource and provided for development purposes and not warranted for end use. You will still need to ensure that the hardware and software meets your needs. Currently we have not tested the BMS with multiple packs in parallel. It could be that the hardware could accommodate it, but the software and state machine would need to be reviewed for correct operation in parallel configuration. There is a self-test build in which will test if the MOSFET can be switched off during startup. This to ensure the MOSFET and its control circuitry is fully functional and can be used for HW/SW OC/OV/temp protections (see SW release documentation). What happens to the batteries depend on the scenario, is it charging or discharging, does it need to connect or disconnect the batteries using the MOSFET. Plus the BMS is not the same as a battery charger. An externally controlled constant current (CC) constant voltage (CV) source is still required to charge the batteries. Currently the BMS has on-board balance resistors plus FETs inside the installed BCC chip to balance the cells, a command from the MCU to the BCC enables or disables balancing for each individual cell. I hope this answers your questions! Re: RDDRONE-BMS772 Hi, We want to use RDDRONE-BMS772 for solar drone with 20 Nos. of 4S battery packs in parallel. Please clarify the following queries, 1. Can RDDRONE-BMS772 board be used readily or any software to be uploaded before using? 2. Can we connect 20 nos. of BMS772 in parallel to charge 20 no. battery packs (each pack has 4S cells)? If yes, any additional protection to be provided externally? 3. Is there any inbuilt protection to prevent MOSFET failure in BMS772? If not, what happens to batteries when MOSFET fails? 4. Are external MOSFETs required for Active cell balancing? How active cell balance works in BMS772? Thanks in advance. Re: RDDRONE-BMS772 Hi @coryjfowler  We're actively investigating the issue. We needed to get some of the current build of boards from the warehouse in order to determine what is going on with this latest board build. A workaround will be provided shortly while we determine the root cause. Thank you for your patience. @cisvmierlo  Re: RDDRONE-BMS772 Can I get some help with my V 4.0 REV D board and the issue with the NFC chip that causes a full stop of the BMS application?  Last reply to the Github issue was 3 days ago.  I was anticipating a reply this morning, but no such luck. https://github.com/NXPHoverGames/RDDRONE-BMS772/issues/6  Re: RDDRONE-BMS772 Hi KarenRdz! Yes that is possible. J19 combines the JTAG debugger pins together with the UART pins, the UART pins are needed for the CLI. There is a DCD-LZ breakout board which lets you connect your JTAG debugger to the JTAG debugger pins (like J2) of that breakout board and separates the UART to FTDI pinout. This could be connected to J19 of the BMS. See https://nxp.gitbook.io/hovergames/rddrone-fmuk66/connectors/debug-interface-dcd-lz/dcd-lz-breakout-board for more detail on the breakout board. Connector J2 is only a 10 pins JTAG connector, without UART pins. You could use J2 to program/debug the board and use J19 for the CLI. As an alternative to that, connector J21 has another UART bus on it. Since the code is publicly available and it uses the NuttX RTOS, it could easily be changed in using the other UART bus for the CLI. You could select LPUART0 as serial console in the menuconfig of NuttX (in Device Drivers -> Serial Driver Support -> Serial console). So then you could use J2 for programming/debugging and J21 for the CLI if you configure it. Re: RDDRONE-BMS772 Hi! I have a question, is it posible to use the CLI if the J-link debugger is on the J2 port? Or is there another way to obtain the information on the J2 whitout using the CLI? Thank you! Re: RDDRONE-BMS772 Yes - sorry to hear that. I also looked, and you are correct, there doesn't seem to be global availability. This is an active and good part, it is just caught up in the global chip shortage. Here are some (not so great) options: - Contact Nexperia directly. You only need a few correct? Sometimes there are samples they have on hand. - Look through Nexperia.com for close alternatives? - Buy an additional BMS-772 and take the parts off one to add to the other? Re: RDDRONE-BMS772 Due to the chip shortage the PSMNR70-30YLH mosfet is no more available in the market. What to do with that, is there any other mosfet we can use with that model. Please reply me soon as we need this product as soon as possible.  Re: RDDRONE-BMS772 Hi Anuj, The FRDM33772BSPIEVB is an evaluation board for the battery cell controller. This is without microcontroller, switches, safety measures and etc. The RDDRONE-BMS772 is a mobile robotics reference design including microcontroller, power switch, (working and available) example software, hardware overcurrent circuit and more. For more information about the RDDRONE-BMS772 see: https://nxp.gitbook.io/rddrone-bms772/ For the example software see: https://github.com/NXPHoverGames/RDDRONE-BMS772 The RDDRONE-BMS772 as populated is rated for 60A continues DC current. With 4 pairs of MOSFETs and 4 heatsinks it is rated at 90A maximum DC current (continues) and this includes the layout and copper used. On the RDDRONE-BMS772 there is a hardware overcurrent circuit at 545A which will act within 20us. Which means a peak current of 545A is allowed for 20us without damaging the board. Higher currents or currents for a longer amount of time might be possible, but has not been tested. Going over the maximum rated currents or the specified time will be of own risk. Keep in mind batteries should always be handled with care. Re: RDDRONE-BMS772 We are working with solar drone which requires a lot of power.  This product seems very nice but i am confused on the maximum rating. We have 6s configuration Lipo battery which is 22 volt, and the motor can require a huge burst current and continuous current(90A for minutes).  I see that the maximum rating for this is 90A DC, Is this value continuous maximum rating or burst maximum rating. What is the burst current and time limit for the burst current. Can you please suggest me which can be better for me this one or the other BMS FRDM33772BSPIEVB.  Hope i get a very fast reply.  Re: RDDRONE-BMS772 The BMS772 does the self balancing. You will need to control the overall current provided to charge the battery. You should also provide some power steering/isolation otherwise with the two batteries in parallel, the higher charged one will attempt to charge the lower charged one. Also - what is not clear above - are you making one pack or two separate pluggable packs. You CAN parallel individual cells in one large one (and use a single BMS) if you wish, but that does not seem to be how you have described it. So one BMS per pack is needed. The BMS is approximately the size of a 3S 4000mA/h hobby LiPo - Sorry i do not have exact dimensions.  Re: RDDRONE-BMS772 Thanks for the update and quick reply. I'll be sure to keep an eye on this thread. Looking for the same issue. Bumped into your thread. alaskasworld.com Re: RDDRONE-BMS772 Hi there, we have a drone battery that consists of 2 x 7000mAh 6S lithium polymer batteries. These two packs are going to be connected in parallel to achieve 14000mAh 6S.  What I did is made a housing to incubate the two packs and connected them to a single 10 pin robust male connector and in the UAV size there is a female connector . The plan is to make the drone battery like cartridge so we can slide it in UAV to click in and go on and when battery need recharging we take out the cartridge and connect it to the charger with same pin type used on UAV. The question is are we able to use you BMS 772 to achieve a self balancing cartridge when recharging? if so how would we do that? Do we need two boards or one only? And how to connect it to the batteries? and what’s the dimensions of that board please? best regards  Falcon  Re: RDDRONE-BMS772 Hello @SH , This depends on what you would like to test.  If you would like to have voltages on cell measurement tabs. Without charging or (passively) balancing the cells. You can easily add some resistors over your voltage supply to mimic the cell voltages and measure them with the BMS772. For example you have a lab power supply and you would like to test a 3S battery (3 cells in series) setup.  You can set the lab power supply to 12V attach them to the power in + and power in - of the BMS. Parallel to that you add a voltage divider with 3 resistors of for example 1kΩ in series from power + to power -.  You can add the 4 balance wires to these resistor (+, - and the 2 in between resistors) to connect to the balance lead connector JP1.  Make sure to solder the BMS for 3S configuration according to the release notes on github: RDDRONE-BMS772/BMS772_releaseNotes_6.0.pdf at main · NXP-Robotics/RDDRONE-BMS772 · GitHub I would suggest to download this release note PDF as the viewer is clipping the document. There should be ~4V per "cell" in this setup.  You should be able to start up the BMS772 in normal mode when you power on the lab power supply (current limit could be set to 100mA without a load).  As long as the BMS and power supply is able to handle it and configured for it, you can add a load to the output of the BMS772 as well.  I hope this helps! Kind regards, Cis   Re: RDDRONE-BMS772 Hello, I am using the BMS-772 for a university project and do not have access to the battery cell emulator. I was wondering how design a resistor setup on breadboard to mimic the battery cells for purely testing purposes temporarily.  Thank you for any help, Shane. Re: RDDRONE-BMS772 HI @cisvmierlo , Thank you for your help. Lowering the clock speed solved the issue. Re: RDDRONE-BMS772 Hello again, Thank you for your help. I have a second BMS-772 board and have soldered the 3 cell connector to the board and I am using a three cell configuration with resistors mimicking cells. However, the CLI always gives me 0v for the 3rd cell and therefore an undervoltage error. There is voltage across the 3rd resistor. I got some solder across the cell setup pads on the bottom of the board but removed most of it. What could be the issue here? Thank you again for any help, Shane Re: RDDRONE-BMS772 Hi @Shane93 , Thank you for reaching out for a question on the RDDRONE-BMS772. And thank for sharing the helpful images! Would it be possible to verify the solder connections to make sure the BMS is configured for 3S? From the image it looks like SJ2 is connected, while SJ12 and SJ10 might not be connected? If you have a multimeter with resistance measurement, you are able to check with (with resistors removed and the board not powered).  Here you can find more information on the solder jumpers for the cell configuration (3S): https://nxp.gitbook.io/rddrone-bms772/board-user-guide/getting-started-with-the-rddrone-bms772/configuring-the-hardware#cell-terminal-connection  Another thing that I notice is that you are using a bread board and Dupont jumper wires. Keep in mind that these are known to have bad connections. I do understand that for debugging this might be easy to do. But a bad connection because of the breadboard and / or the wires could also be a problem. From what I can see in the image, the way you connect it is OK.  I'm also curious about your settings. If you type in the CLI / UART command window the following command: bms get all  What do you see? I would like to see the n-cells you have configured for example as default this is 6 cells.  You can find which commands to look at in the Chapter 6 Getting started / quick start guide of the release notes (page 9 of 59): RDDRONE-BMS772/BMS772_releaseNotes_6.0.pdf at main · NXP-Robotics/RDDRONE-BMS772 · GitHub  Chapter 6.4.1: The most important BMS variables lets you know what to configure when you start with a BMS. Like n-cells. You can change n-cells to 3 (in your case) with the command: bms set n-cells 3 That should make sure the BMS doesn't check the other 3 cells that are not present in your setup. I hope this helps! Kind regards,  Cis van Mierlo   Re: RDDRONE-BMS772 Hi @cisvmierlo  Thank you for all your help. The solder pads seem to be connected, when I run a "bms get all" I get this return. However, measuring across the 3 resistors gives me the natural step down of 12v, 8v, 4v, 0v.  Thank you, Shane   Re: RDDRONE-BMS772 @cisvmierlo  Thank you very much for you help. Two of the surface mount resistors had lifted on the back of the board causing an error in the cell reading circuit. The issue is resolved now thank you again. I have one final question you might be able to assist with. I am building my own custom CAN interface using NI-XNET with Cyphal CAN. Can you tell me how the CAN frames are structured and the addresses? Also is it possible to turn off the output voltage by controlling the MOSFET's over CAN? Thank you, Shane Re: RDDRONE-BMS772 Hi @Shane93, Good that you have found this issue with 2 SMD resistors and thank you for sharing this information. I believe both CyphalCAN and DroneCAN information can be found in the release notes.  It will mention which messages are implemented.  There is no direct message in either protocol that can turn off the power switch.  With DroneCAN, you can easily change settings and might be able to create an error in which the BMS will turn off the power. For example, changing the overtemperature setting.  You should be able to change the setting back to a "good" value and reset the fault.  This has been tested with DroneCAN.  But if you are creating your own custom CAN interface, you can add this feature yourself.  I hope this helps. Best regards, Cis
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[ls1046ardb] 将 DDR4 DIMM 更换为其他 DIMM (2GB),然后启动失败。 我用其他 DIMM 交换了 DDR4 DIMM。 (该 DIMM 可用于一般 Ubuntu PC,并可通过 memtest86) 然后启动顺序失败,并显示以下错误消息。 错误:板参数不匹配。 错误:匹配板计时失败。   在 cal_board_params() 函数中,我发现 pdimm->的 rc 值为 0x01,然后修改了以下参数。 static const struct rc_timing rce[] = { {U(1600), U(8), U(7)}, {U(1867), U(8), U(7)}, {U(2134), U(8), U(9)}, {} }; static const struct board_timing udimm[] = { {U(0x01), rce, U(0x01020304), U(0x06070805)}, // add this line {U(0x04), rce, U(0x01020304), U(0x06070805)}, {U(0x1f), rce, U(0x01020304), U(0x06070805)}, };     但是启动顺序失败。 似乎无法启动 BL31,并且失败了。 注意:BL2:正在启动 BL31 信息: 入口点地址 = 0xfbe00000 信息: SPSR = 0x3cd // 不再有日志...   我认为应使用 QCVS(CodeWarrior)配置 rce 和 udimm 参数,但却出现了以下错误。 创建新的"QorIQ 配置项目" 选择"DDR 内存控制器配置" 选择 " 从内存文件 " 中,选择 SPD 二进制文件作为 " 输入文件 " "导入" 按钮 错误信息"请检查导入文件中的 DDR 数据速率值!" 。   我的方法正确吗? 如何通过 QCVS 创建正确的参数? Re: [ls1046ardb] Exchange DDR4 DIMM to other DIMM(2GB), then boot failed. 您需要使用 QCVS DDrV 工具连接到定制板进行验证和优化,以获得优化的 DDR 初始化参数并将其用于 ATF 软件。 请参阅 DDRv 用户手册https://www.nxp.com/docs/en/user-guide/QCVS_DDR_User_Guide.pdf 客户需要根据自定义板创建 DDR QCVS 项目。 如果在客户板上使用 DIMM,则目标上有 SPD,请在创建 QCVS DDR 项目时在 DDR 配置面板中选择 “读取 SPD”。 然后使用 QCVS DDrV 工具连接到目标板,进行进一步的优化和验证。 验证成功后,请单击 Project->Generate Processor Expert Code(生成处理器专家代码),以获取文件 ddr_init1.c 中的优化 DDR 控制器配置参数、并用它来修改 ATF 源代码 plat/nxp/soc-ls1046a/ls1046ardb/ddr_init.c。 Re: [ls1046ardb] Exchange DDR4 DIMM to other DIMM(2GB), then boot failed. 感谢您的评论。 我可能误解了... QCVS 无法读取 512 字节的 SPD 二进制文件吗? 不是来自 DDR DIMM 中的 SPD。 我现在没有 JTAG 硬件。 致以最诚挚的问候, Narita Re: [ls1046ardb] Exchange DDR4 DIMM to other DIMM(2GB), then boot failed. JTAG 硬件是必要的,你需要将 QCVS DDrV 工具连接到目标板上,通过 JTAG 进行优化和验证以获得优化参数。 Re: [ls1046ardb] Exchange DDR4 DIMM to other DIMM(2GB), then boot failed. 谢谢。 我会拿到 CodeWarrior TAP 然后试着发表你的评论。 致以最诚挚的问候, Narita
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シードメリットは初期のコンテンツのパフォーマンスにどのように影響しますか? こんにちは、みんな。 私は、新しいトピックに関するコンテンツを早期に公開することで、認知度が高まり、長期的なトラフィックのメリットが得られるということを学んできました。 プラットフォームや検索エンジンは、トピックが競争的になる前に、早期の高品質な投稿に報酬を与えるという考えのようです。この戦略の中盤では、シードメリットが重要な役割を果たし、クリエイターに早期かつ関連性があるというだけで有利になります。 これが実際の状況でどの程度実用的であるか興味があります。コンテンツ作成者はどのようにして、急上昇中のトピックを常に早期に特定できるのでしょうか。また、トピックがピークに達する前に対応する価値があるかどうかを判断するのに役立つシグナルは何でしょうか。
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For S32G274A multicore scenario, bl2_w_dtb.s32 is flashed into QSPI FLASH, How to build & flash FIP For multicore scenario, bl2_w_dtb.s32 is flashed into QSPI FLASH, FIP image is meant to be flashed info eMMC. 1>Is it sdcard type fip image that should be flashed? 2>Where should FIP image go? RAW area or first partition of eMMC? 3>How to build such ATF images? Re: For S32G274A multicore scenario, bl2_w_dtb.s32 is flashed into QSPI FLASH, How to build & fl Hello, @wansp  Thanks for your reply. 1. Yes, the booting image struct changed a lot since BSP42, on BSP46, sorry that you may have to obey the rules that mentioned in the BSP46.0 UM for flashing the image to the QSPI/SD. 2. I have checked the code in TFA of BSP46, seems the settings you mentioned is deprecated. BR Chenyin Re: For S32G274A multicore scenario, bl2_w_dtb.s32 is flashed into QSPI FLASH, How to build & fl BSP46 is really brand-new. It seems that BSP42 & BSP46 are dealing with FIP's eMMC flashing differently (RAW data access vs. by partition), which may make BSP upgrade hard. For BSP42, I prefer make both BL2 & FIP in QSPI. Since they are similar, can the be the same copy? Am I using the right ATF compile commands? Is FIP_QSPI_OFFSET still valid for BSP46? Re: For S32G274A multicore scenario, bl2_w_dtb.s32 is flashed into QSPI FLASH, How to build & fl Hello, @wansp  1. For BSP before BSP43(say BSP42), the A53 bootloader(TFA/uboot) would be built to a standalone image(fip.bin, images for SD/eMMC boot), in this case, the same binary should be flashed to both SD card/emmc and QSPI for booting from M7 bootloader(multicore boot specified in AN13750). The building command could be the same mentioned in BSP42.0 UM for SD boot building. 2. For BSP 43 and later, the A53 bootloader(TFA/uboot) would be built to generate two images(bl2 and fip), in this case, the bl2 should be flashed to the QSPI, while the fip one could be flashed to the eMMC/SD as specified by the BSP46.0 UM. The building command could be also the same mentioned in BSP46.0 UM for SD boot building. 3. The AN13750 is based on very early version BSP, the steps/tips/descriptions for booting are still referenceable, but some details for certain version software operation may be outdated, I suggest following the corresponding BSP UM for different scenarios. BR Chenyin Re: For S32G274A multicore scenario, bl2_w_dtb.s32 is flashed into QSPI FLASH, How to build & fl BSP46 UM seems easier to understand. I drew two diagrams for two scenarios: 1>BL2 in QSPI, FIP in EMMC 2>both BL2 & FIP in QSPI Am I using the right ATF compile commands? For both BL2 & FIP in QSPI case, does any compile option exist to declare its offset in QSPI FLASH? Re: For S32G274A multicore scenario, bl2_w_dtb.s32 is flashed into QSPI FLASH, How to build & fl Hello, @wansp  Thanks for the confirmaiton. 1. Yes 2. It is different for BSP42 and BSP46, on BSP42, there is only fip file existed, which would be flashed to /sdx; on BSP46, there would be both bl2 and fip binaries, the fip would be flashed to /sdx1. 3. For building the fip images, you may directly following the specific BSP UM to manually built, but note that for multi-core boot purpose(as AN13750 suggested), the tfa part may need to be built with the following modification: BR Chenyin Re: For S32G274A multicore scenario, bl2_w_dtb.s32 is flashed into QSPI FLASH, How to build & fl Two versions are in consideration: BSP42 & BSP46 It seems that they are different: 1>BSP46 user manual has this: make CROSS_COMPILE=/path/to/your/toolchain/dir/bin/aarch64-none-linux-gnu- \ ARCH=aarch64 PLAT= BL33= \ FIP_LOCATION=mmc the FIP is flashed to partition 0 & MBR partition scheme is required. as a common data partition, it may be influenced by operations on other partitions, which may hurt reliability. 2>in BSP42 user manual, parameter FIP_MMC_OFFSET seems for this purpose: make CROSS_COMPILE=/path/to/your/toolchain/dir/bin/aarch64-none-linux-gnu- \ ARCH=aarch64 PLAT= BL33= \ FIP_MMC_OFFSET=0x5400 since absolute offset is used, it seems to be using RAW area. But how to flash the original image into the RAW area? Re: For S32G274A multicore scenario, bl2_w_dtb.s32 is flashed into QSPI FLASH, How to build & fl Hello, @wansp  Thanks for your post. May I know which version BSP you are referring to ? BR Chenyin Re: For S32G274A multicore scenario, bl2_w_dtb.s32 is flashed into QSPI FLASH, How to build & fl BSP46 UM tells: “The accepted values for FIP_LOCATION are: mmc, qspi or memory." If FIP_LOCATION=qspi, BL2 should know where to find FIP. If FIP_QSPI_OFFSET is deprecated, I think BSP46 should provide similar mechanism or has some unspoken default settings. Re: For S32G274A multicore scenario, bl2_w_dtb.s32 is flashed into QSPI FLASH, How to build & fl Hello, @wansp  From my understanding, the default building commands, like: make CROSS_COMPILE=/path/to/your/toolchain/dir/bin/aarch64-none-linux-gnu- \ ARCH=aarch64 PLAT= BL33=  FIP_ALIGN=64  could generate correct bl2 and fip images for multicore boot. You may flash the bl2 part to the QSPI, and replace the FIP part of the default SD/mmc image with the newly generated one, then the bootloader is able to find the correct M7 application and A53 bootloader(bl2) and bring them up. If there are still issues, feel free to share all logs for your steps and console prints, we will help to check them. BR Chenyin
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S32DS 牌照消失 S32DS 许可证丢失,需要激活,但旧激活码无效。如何解决这个问题? Re: S32DS licence disappear 请参考此页面和我的个人资料许可证状态。 Re: S32DS licence disappear DS 3.5 ,我的执照状态。 Re: S32DS licence disappear 你好 能否请您提供试图安装的 S32DS 版本? 顺祝商祺! Peter Re: S32DS licence disappear Ds 3.5 Re: S32DS licence disappear 你好、 我检查了您的账户,您的许可证是有效的。您尝试过离线激活吗? https://community.nxp.com/t5/S32-Design-Studio-Knowledge-Base/HOWTO-Activate-S32-Design-Studio/ta-p/1128340 Re: S32DS licence disappear 是的,我试过. 结果和其他信息,请参考我的其他回复。 我找不到我的驾照 . @jiri_kral Re: S32DS licence disappear 我使用了其他激活有效代码,也显示了该错误。请参考我的其他回复。 @jiri_kral @petervlna Re: S32DS licence disappear 我的个人资料中没有许可证激活码,请查看。 Re: S32DS licence disappear 你好 这个问题是否仍然有效,或者你是否设法让它运行了? 顺祝商祺! Peter
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iMX8QM 上の Jailhouse(lf-6.6.52_2.2.0 搭載) こんにちは、NXPチームの皆様、 i.MX Linux リリースノート RN00210、Rev. LF6.6.52_2.2.0 — 2025 年 1 月 6 日 には 、jailhouse がすべての i.MX 8M、8ULP、 i.MX 93、 i.MX 95 をサポートしていることが記載されています。iMX8Quad Max はリストに含まれていません。 meta-freescale( https://github.com/Freescale/meta-freescale/tree/scarthgap ) は jailhouse を構築するためのレシピを提供しています。MACHINE_FEATURES が jailhouse と互換性のあるマシンには imx8qm が搭載されていません。搭載されているのは imx95、imx93、imx8mm、imx8mn、imx8mp、imx8ulp のみです。これは上記のi.MX Linux リリースノート RN00210 と一致しています。 しかしながら、jailhouseのソースコード( https://github.com/nxp-imx/imx-jailhouse/tree/lf-6.6.52_2.2.0/configs/arm64 ) にはimx8qm SoC用のコードが含まれています 。jailhouseはimx8qm SoC上で動作可能のようです。一部のドキュメントやコミュニティチケットによると、jailhouseはカーネル5.4と4.9で動作していたようです。 私の質問は、jailhouse が LF6.6.52 でもまだ動作するのか、それとも検証されていないだけなのかということです。 ありがとう。 Re: Jailhouse on iMX8QM with lf-6.6.52_2.2.0 こんにちは@Benjamin_Huさん、 NXP サポートにお問い合わせいただきありがとうございます。 UG10170によれば、現在の BSP では、そのプロセッサに対して jailhouse 機能は正式にサポートされていません。 公式にサポートされているプロセッサは次のとおりです。 i.MX 8Mシリーズ i.MX 8M ミニ LPDDR4 EVKB i.MX 8M ナノ LPDDR4 EVK i.MX 8M Plus LPDDR4 EVK i.MX 9シリーズ i.MX 93 EVK i.MX 943 EVK i.MX 95 15x15 LPDDR4x EVK i.MX 95 19x19 LPDDR5 EVK よろしくお願いいたします。 チャビラ
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グリーンVIP 1.3.0GVP_RTU_1_C1_VM2 の生成に失敗しました こんにちは、専門家さん。 GVP_RTU_1_C1_VM2 の元のプロジェクトを開くと、以下のようなエラーが表示されています しかし、.mexからファイルを見ると、それが /RTOS_R52/Os/OsCounter_0 です。しかし、GUI インターフェースでは何も参照できません。ご協力いただけませんか?ありがとう! BR、 キャサリン グリーン_VIP Re: GreenVIP 1.3.0 GVP_RTU_1_C1_VM2 generation failed こんにちは@Catherine 、 問題を追跡するために Jira チケットを作成しました。GreenVIP チームができるだけ早く返信します。 Re: GreenVIP 1.3.0 GVP_RTU_1_C1_VM2 generation failed こんにちは@Catherine 、 この問題をリクエストしたお客様はいますか? よろしくお願いします、 ラドゥ
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Failed to transfer int data to float data Hello: ‘nvm_calib->par_p1’ data is int16 (7002), ‘nvmdata_buff’ is a float. After assignment, it becomes 14229, which should be 7002.0. MCUXpress IDE V24.12; RW612 sdK25.09; frdmrw612 wifi_httpsrc。 May I ask how to set it up! Re: Failed to transfer int data to float data Hi, Could you please tell me how to reproduce this using the example? Is the issue related to the example itself, or is it coming from a custom implementation?   Regards, Daniel.
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Where does the clock for the RW612 LCDIC come from and how many HZ can the SPI 8080 run to respectively?
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QNXがNXPに登場 こんにちは、サポートチームの皆様 評価ボード S32G-VNP-RDB3 で QNX イメージを起動することに関する質問があります。QNX ソフトウェア センターから参照イメージを入手できます。 QNX BSPビルドプロセスの出力は.uiです。ファイル。 すでに Linux Yocto BSP パッケージが動作しており、これをビルドして SD ブートを使用しました。これは.sdカードです正常に起動しているイメージ。Linux イメージ ファイルの代わりに QNX イメージを使用しようとしましたが、起動しません。 以下の質問があります:- QNX を起動するには、Linux Yocto ビルドから u-boot または ATF に変更を加える必要がありますか? 起動するには QNX イメージ形式に何か変更が必要ですか? PS: QNX ビルドから生成された生のファイルのブートも試みました。起動もしませんでした。 Re: QNX bring up in NXP Silicon Signalsで試してみるといいでしょう Re: QNX bring up in NXP こんにちは@shebin 、 QNX は NXP 製品ではないため、それに関する情報はあまりありません。そうは言っても、役に立つかもしれないアプリケーション ノートがあります: AN14355 は、 S32G3 製品ページでいつでも入手できます。このドキュメントの目的は、QNX で PFE を使用する方法を説明することですが、uboot と ATF を設定してフラッシュする方法、および SD カードを設定する方法を説明するセクションがいくつかあります。セクション4「前提条件」 、 「5「コンポーネント」」 、および5.2.4「準備された SD カードのサンプル パーティション」を確認してください。確実に動作させるために、ドキュメントに記載されているコンポーネント バージョンを使用することを強くお勧めします。 一部の手順は PFE のコンポーネントを構成するためのものであるため、スキップできる可能性があります。 この情報で問題が解決したかどうかお知らせください。
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