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プラグイン設定ダイアログが失敗しました CAN 通信の構成が完了すると、「プラグイン構成ダイアログが失敗しました」というプロンプトが表示されます。接続文字列を手動で指定してみてください。」 Re: The plugin configuration dialog failed こんにちは、 この問題が解決されるまでは、こちらで説明されている回避策をご覧ください。 よろしくお願いいたします。 ミハル

Request for Reference Documentation for SE052 Security IC with Raspberry Pi CM5 Dear NXP Support Team, We are currently developing a custom PCB for our project, in which we are using the NXP SE052 Security IC for secure communication and secure storage of certificates. Our host platform is the Raspberry Pi Compute Module 5 (CM5). We would like to understand the proper integration method and software support required to interface the SE052 security IC with the CM5 platform. Could you please provide the following: Reference documentation or application notes for integrating the SE052 Security IC with Raspberry Pi platforms (especially CM5). Any available reference design, hardware schematics, or recommended interface configuration (I2C / T=1 over I2C). Software support details such as middleware, drivers, or examples compatible with Linux running on Raspberry Pi. Any guidance or best practices for implementing secure certificate storage and secure communication using SE052 with embedded Linux systems. Your guidance and relevant documentation will help us correctly implement the SE052 in our custom hardware design. Thank you for your support. Best regards, Urvisha Andani Re: Request for Reference Documentation for SE052 Security IC with Raspberry Pi CM5 Hi @urvisha , Please kindly refer to the following for details: Reference documentation or application notes for integrating the SE052 Security IC with Raspberry Pi platforms (especially CM5). Get started with EdgeLock SE05x support package  EdgeLock SE05x Quick start guide with Raspberry Pi  Any available reference design, hardware schematics, or recommended interface configuration (I2C / T=1 over I2C). OM-SE052ARD: Development Board for EdgeLock SE052F Secure Element | NXP Semiconductors  https://www.nxp.com/webapp/Download?colCode=AN14262 Moving from EdgeLock SE050F to EdgeLock SE052F  https://www.nxp.com/webapp/Download?colCode=UM11225 Software support details such as middleware, drivers, or examples compatible with Linux running on Raspberry Pi. We have plug&trust MWs available : Full version: https://www.nxp.com/webapp/Download?colCode=SE05x-PLUG-TRUST-MW&appType=license mini version: GitHub - NXP/plug-and-trust: Plug & Trust middleware to use secure element SE050 · GitHub  nano version: GitHub - NXPPlugNTrust/nano-package · GitHub  PKCS#11 support: GitHub - NXPPlugNTrust/se05x-pkcs11: This is the pkcs11 Plugin Interface for Se05x using the mini-pkg. · GitHub  Any guidance or best practices for implementing secure certificate storage and secure communication using SE052 with embedded Linux systems.  1. securely storing certs inside the SE: Refer to demos from the MW:se05x_GetCertificate ,se05x_InjectCertificate   2. Always enable platformSCP to secure communication between the host and SE. Refer to chapter 5 of https://www.nxp.com/docs/en/application-note/AN12570.pdffordetails. SE052F has platformSCP enabled by default, so you just need to rotate the default keys to your own defined keys for the mass production. The default keys can be found in https://www.nxp.com/docs/en/application-note/AN14277.pdf Refer to the  rotation of Platform SCP03 keys demo from MW for details. 3. Use Development Boards + Adapter for Early Bring-Up OM-SE052ARD: Development Board for EdgeLock SE052F Secure Element | NXP Semiconductors  OM-SE050RPI Product Information | NXP Semiconductors    Hope that helps,   Have a great day, Kan ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. -------------------------------------------------------------------------------

S32K394 SAF - sCheck MemMap セクション こんにちは、チームの皆さん 私はSW32K3_SAF_1.0.5_D2503を使用しています。私の質問は 1.sCheck の場合、このシリーズの MCU には AES_ACCEL ペリフェラルがないため、S32K394 の MemMap でセクション「s32_saf_bss_sram_10」をマップする方法。 2. SAF に通知する構成が不足しています。このペリフェラルセクションは無視してください。 さらに詳しい情報が必要な場合は、お知らせください。 ご回答をお待ちしています。 Re: S32K394 SAF - sCheck MemMap Section こんにちは、 セクション SRAM_10 は、実際には ETPU SDM メモリに配置されます。ユーザーマニュアルにはバグが含まれており、すでにチームに修正が報告されています。 （チケットID：SRTDCS3-1604）

How to define the array on BOARD_SDRAM? Hello. MIMXRT1064-EVK Please tell me how to assign the array to BOARD_SDRAM? My own code doesn't seem to work, it's still on SRAM_DTC, please advise! Thank you! #define SDRAM_BASE_ADDRESS (0x80000000) uint8_t mySdramBuffer[1000] __attribute__((at(SDRAM_BASE_ADDRESS))); Re: 如何定义数组在BOARD_SDRAM上？ Hi @haitao178. Thank you for your interest in the NXP RT product line and we are pleased to be of service to you. If you are using SDRAM, you need to be careful to enable the DCD enable setting. If you are using MCUXPresso IDE, please add macro definition to enable DCD (XIP_BOOT_HEADER_DCD_ENABLE=1)   I hope the above helps you Best Regards MayLiu 回复： 如何定义数组在BOARD_SDRAM上？ Hi MayLiu. Thank you for your support. Already added macro definitions in DCD but still BOARD_SRAM is not allocated after compilation, please help to see the reason for this, the code is as below:   回复： 如何定义数组在BOARD_SDRAM上？ Hi @haitao178. I have tested and verified that it is possible to correctly define arrays on BOARD_SDRAM, and I suggest you to follow the steps below to test and verify: HW: MIMXRT1170-EVKB IDE: MCUXPresso IDE 1: Add macro definition XIP_BOOT_HEADER_DCD_ENABLE=1 2: Add code, please refer to the project screenshot below. I am using RT1170 development board, your development board can still be referenced. Best Regards MayLiu 回复： 如何定义数组在BOARD_SDRAM上？ You're welcome, and if you have any questions in the future, feel free to ask them in the NXP community. 回复： 如何定义数组在BOARD_SDRAM上？ Sorry, failed to paste the picture. The code is as follows: code: #define SDRAM_BASE_ADDRESS (0x80000000) uint8_t mySdramBuffer[4096] __attribute__((at(SDRAM_BASE_ADDRESS))); int main(void) { FRESULT error; DIR directory; /* Directory object */ FILINFO fileInformation; UINT bytesWritten; UINT bytesRead; const TCHAR driverNumberBuffer[3U] = {SDDISK + '0', ':', '/'}; volatile bool failedFlag = false; char ch = '0'; BYTE work[FF_MAX_SS]; mySdramBuffer[4000] = 0x99; ...... log: Memory region Used Size Region Size %age Used PROGRAM_FLASH: 80224 B 4 MB 1.91 % SRAM_DTC: 16192 B 128 KB 12.35 % BOARD_SDRAM: 0 B 30 MB 0.00 % SRAM_ITC: 0 B 128 KB 0.00 % SRAM_OC: 0 B 768 KB 0.00 % NCACHE_REGION: 0 B 2 MB 0.00 % Finished building target: KL_Osram_Demo.axf 回复： 如何定义数组在BOARD_SDRAM上？ Thanks to MayLiu!

S32N55 RTD Dio driver limitation Hi , Here is a driver limitation in RTD_DIO_UM(Version-SW32N_RTD_R21-11_1.8.0): After testing, FSS_GPIO1_19 (FCCU_ERRSTT1) can be toggled by the DIO module in the RTU0 project. Could you please provide more details regarding this limitation? Alternatively, is this limitation outdated and should it be removed? BR Alex S32N55 AUTOMOTIVE-RTD    RTD Re: S32N55 RTD Dio driver limitation Hi @Alex_Liu, The dev team said that: "this issue is a hardware limitation - TKT0638320. So, they skipped testing process and noted about this limitation in Dio_UM." From my point of view, to clarify this limitation, you should contact the S32N55 hardware team. Best regards, Dan Re: S32N55 RTD Dio driver limitation Hi @DanNguyenDuy  I’ve checked with the colleagues who are familiar with this ticket, and confirmed that the hardware limitation has already been fixed on the B0 sample. You can find more details in the Design PDM. Since the hardware bug has been resolved, could you please help remove the corresponding limitation description from the DIO UM? Thanks BR Alex Re: S32N55 RTD Dio driver limitation Hi @Alex_Liu, Thank you for your information. Unfortunately, I can't access your link. Could you capture information and contact points from hardware team to help me confirm this? Based on this information, I can raise a ticket to RTD for requesting update Dio_UM file. Best regards, Dan Re: S32N55 RTD Dio driver limitation Hi @DanNguyenDuy  I catch the information as below:   It shows you can double check with Rob Rand. Or you can get more details with Rares Vasile, who belongs to FSS software team. BR Alex Re: S32N55 RTD Dio driver limitation Hi @Alex_Liu, Thank you for your information. I raised a "change request" ticket (ARTDCANG-1641)to RTD team for requesting update about this hardware limitation in Dio_UM. Best regards, Dan

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