关于 LPC552x 的 SPI 我正在使用LPC552x系列。 我计划将 GPIO 用作 SPI 并连接到 Flash ROM。 我想将两个设备连接到 Flash ROM。因此，我想在 LPC552x 未进行通信时将其 SPI 设为高阻抗，以便 IO 信号不会在电路板上发生冲突。 不使用SPI通信时，是否可以将输出信号IO设置为高阻态？ 回复：关于LPC552x的SPI 嗨，哈利 谢谢您的回复。 我也会检查样品。 回复：关于LPC552x的SPI 嗨，哈利 谢谢您的回复。 很高兴听到当 SPI 不活动时它可以是 GPIO。 您能否给我一个具体的示例（程序代码）来动态更改程序中的 SPI 和 GPIO 设置？

FreeRtos パッケージの RTD3.0 へのアップデート こんにちは 現在、S32K148を使用しており、新しいRTD3.0.0にアップグレードする予定です。 しかし、FreeRtos PackageはリリースノートでRTD2.0.0をサポートしていると述べています。 しかし、サンプルプロジェクトはEvalb上で正常にビルドされ、実行されているようです。DS3.6.1 + RTD3.0 + FreeRtos2.0.0の構成を使用 今後、新しいFreeRtosパッケージはありますか?それとも、サポートされていると頼りにできますか? よろしくお願いします! Re:FreeRtosパッケージのRTD3.0への更新 こんにちは それは素晴らしいことです。感謝！

如何创建现有 RTD 项目的副本 如何在 S32DS for S32 中创建同一工作区中具有不同名称的现有 RTD 项目的副本

LPC845断电 大家好， 我正忙于使用 LPC-845 定制电路板来开发遥控器。 但是，我无法让系统进入设备说明书中规定的消耗电量的模式。 在断电模式下，电流不会低于 500 uA。 因此我拿 LPC845-BRK 板进行测试（没有连接外围设备，并且在 JP1 跳线上很容易测量） 仍然没有运气，尝试了一切（参见附件的源代码）来查看是否忘记了什么。 断电时为 500 uA，深度断电时为 320 uA。 那么我是不是忘记了什么？ 此致， 短剑。

i.MX RT1060 UART FIFO does not work I want to send 120 bytes via UART1 with an i.MX RT1060 (MIMXRT1061CVJ5B) using the FIFO. I've set the TX FIFO to 256 bytes, but it's not working. Is this a processor bug? Re: i.MX RT1060 UART FIFO does not work Hello, As I said, I can't do anything with these bloated examples, because I need complete control over the module, and many important functions aren't included in the API. But I was able to solve it after all: an important control bit "DREQ" wasn't set: Now it's running like crazy 😉 It's a great machine, but the API is completely inadequate... Thanks for your effort. Regards, Mark Re: i.MX RT1060 UART FIFO does not work Hi @Mark16 , Thanks for your reply. The SDK demo provides  API functions that you can call directly, which is more convenient and quicker  than you set set the registers.   I did a test for you, I think you can refer to it. I have send detail information to you Email(   Due to NXP the latest policy, I can not send your code directly, but I can send you picture).   Wish it helps you. If you still have question about it, please kindly let me know. Wish you a nice day! Best Regards MayLiu Re: i.MX RT1060 UART FIFO does not work Hello, I'm not confused. I just want to send 120 bytes over UART1 every 100ms, with minimal overhead, i.e., without interrupts, etc. With a 256-byte FIFO, this would be super easy. With a 4-byte FIFO, it won't work without interrupts or polling. I've been trying to solve it with the famous eDMA for 5 days now, but I've completely failed. I've read the relevant chapters in the manual several times, but a lot remains unclear. The example programs in the SDK and the drivers in "fsl_lpuart_edma," "fsl_edma," etc., are incredibly bloated, deeply nested, and can only be used in a specific way. They're useless for simple, straightforward applications. I have 25 years of professional experience as an embedded programmer, with a wide variety of processors, but I've never experienced anything like this. Please explain to me how to set the registers for UART1 and eDMA to easily send 120 bytes over UART1. Please use "bare metal" style, e.g.: LPUART1->CTRL = ? etc... DMA0->SERQ = ? etc... DMA0->TCD[0].SADDR = ? etc... Re: i.MX RT1060 UART FIFO does not work Hi @Mark16 , Thanks for your reply. The LPUART FIFO size of the RT1060 processor is also 16 bytes. Could you share with me the application requirements for a larger FIFO size?  and could you tell me your point of confusion? I can forward your requirements to the NXP internal team. You mentioned that "using LPUART + DMA " is also an effective transmission method. The NXP SDK demos have  a lot of examples for you to use. Best Regards MayLiu Re: i.MX RT1060 UART FIFO does not work That's a bit disappointing. Now they've built this mega-machine, with amazing features, and then they're skimping on the UART FIFO. Why is that? Even my old LPC2478 had a larger UART FIFO of 16 bytes. I want my money back 😉 Then I guess I'll have to pump the data via eDMA... Re: i.MX RT1060 UART FIFO does not work Hi @Mark16 ， Thanks for your updated information. LPUART TXFIFOSIZE/RXFIFOSIZE size is fixed, you can not modify it. The value in RXWATER and TXWATER must be set to be less than the receive FIFO/buffer and transmit buffer/FIFO size, it means the value in RXWATER and TXWATER must be set to be less than 4  datawords. Best Regards MayLiu Re: i.MX RT1060 UART FIFO does not work Where can i set the value? In the Config Tool? Re: i.MX RT1060 UART FIFO does not work Where can i set the value? In the Config Tool? Re: i.MX RT1060 UART FIFO does not work Hi @Mark16 , Thank you so much for your interest in our products and for using our community. Question: I want to send 120 bytes via UART1 with an i.MX RT1060 (MIMXRT1061CVJ5B) using the FIFO. I've set the TX FIFO to 256 bytes, but it's not working. Is this a processor bug? Answer: This is not a processor bug. In IMXRT1060RM,   The maximum number of transmit/receive datawords that can be stored in the TXFIFOSIZE/RXFIFOSIZE. https://www.nxp.com/webapp/Download?colCode=IMXRT1060RM&location=null I run a  SDK demo on MIMXRT1060-EVK board for you to better understand. The LPUART RXFIFOSIZE / TXFIFOSIZE  value are 4 datawords.  The value in RXWATER and TXWATER must be set to be less than the receive FIFO/buffer and transmit buffer/FIFO size The value you set the TX FIFO to 256 bytes are not correct value, Please set the value based on the MIMXRT1060RM. Wish it helps you. If you still have question about it, please kindly let me know. Wish you a nice day! Best Regards MayLiu

fatal error: Spi.h: No such file or directory "fatal error: Spi.h: No such file or directory" error occurs when building /BMS_K322_M7_0/RTD/include/sbc_spi_external_access.h RTD Information: SW Version: 3.0.0 Build Version: S32K3_RTD_3_0_0_P07_D2306_ASR_REL_4_7_REV_0000_20230629 SBC_FS26 Driver Info: SW Version: 3.0.0 Build Version: S32K3_RTD_3_0_0_P07_D2306_ASR_REL_4_7_REV_0000_20230629 We are not using AUTOSAR, so we are not using MCAL. Re: fatal error: Spi.h: No such file or directory Hi Since you are using non-AUTOSAR, you should not use Spi.h. Try to add USE_IPV_LPSPI in Preprocessor: Best Regards, Robin ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "ACCEPT AS SOLUTION" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. -------------------------------------------------------------------------------

FS26 未进入待机状态且初始化失败 – FS_STATE 您好，NXP 支持人员， 我正在使用您知识库中的以下示例： RTD 示例：使用 S32K3X8EVB 的 FS26 WKUP（带 PGOOD 和 EXTWAKE） 我的目标是将 FS26 和 S32K3X8 控制器置于待机模式。当控制器成功转换到待机状态时，FS26 仍保持相同状态并且不会跟随。 此外，函数调用： eReturnValue |= Sbc_fs26_InitDevice(); 返回not_ok，初始化过程失败。经过调试，我发现 Sbc_fs26_GetDeviceState() 返回 0x14 作为 FS_STATE 值。 根据 FS26 数据表，我找不到任何清楚解释该值含义的文档，特别是位 4 （即 0x14 = 0b10100）。您能否澄清一下 FS_STATE 寄存器中的第 4 位代表什么？数据表的寄存器描述部分没有提及它。 我也看到过这篇相关文章，它似乎涉及了类似的问题，但没有提供明确的解决方案： FS26 FS_STATES 和 SPI 通信 您能否协助完成以下事项： 为什么 FS26 没有与 S32K3X8 一起转换到待机模式？ FS_STATE 值 0x14 表示什么，具体来说位 4 的意义是什么？ Sbc_fs26_InitDevice() 返回 not_ok 的可能原因有哪些？ 如能得到任何指导或说明，我们将不胜感激，尤其是有关未记录的 FS_STATE 位。 回复：FS26 未进入待机状态且初始化失败 – FS_STATE 谢谢您的回复。我检查了建议的解决方案，但仍然显示相同的问题。经过进一步调试，我发现系统正在进入 INVALID_FS 状态，并且没有从外围设备更新任何配置。我检查了默认寄存器值并确定了 SBC_FS26_FS_GRL_FLAGS_ADDR 寄存器，它指示过压故障。检查 SBC_FS26_FS_OVUV_REG_STATUS_ADDR 寄存器后，我发现这是一个 VMON_EXT 过压情况。调整电路连接、改变电阻值后，问题得到解决。系统现在正确转换到 FS_Init 状态，并且其他操作按预期工作。再次感谢您的支持。 回复：FS26 未进入待机状态且初始化失败 – FS_STATE 1. 进入待机模式之前，FS26处于什么状态？您尝试如何将其转换为待机模式？ 我正在使用 S32K358 开发板，其中包括具有默认配置的 FS26。我目前正在测试 NXP 提供的示例代码[帖子中提到的链接]。但是，Sbc_fs26_InitDevice() 函数返回 NO_OK，表明初始化失败。因此，FS26 不会转换到 FS_INIT 或任何其他操作状态。当我读取 FS_STATE 寄存器时，我得到了 0x14。   2. FS_STATE 值 0x14 表示什么，特别是位 4 的意义是什么？ 如果这个值与屏幕截图中显示的表中的任何条目不匹配，它是否仍然具有任何定义的含义？ 另外，当所有记录的 FS 状态似乎都在 3 位之内覆盖时，为什么寄存器要使用 4 位？表中提到了“故障安全状态机的实际状态”，那么第 4 位是否表示特殊故障情况或未记录的状态？ 回复：FS26 未进入待机状态且初始化失败 – FS_STATE 你好 为什么 FS26 没有和 S32K3X8 一起切换到待机模式？[gw]进入待机模式之前，FS26 的模式是什么？您是如何操作它进入待机模式的？ FS_STATE 值 0x14 表示什么，具体来说位 4 的意义是什么？ [gw]如果没有符合您帖子图片中的表格值，则此结果毫无意义。 Sbc_fs26_InitDevice() 返回 not_ok 的可能原因有哪些？[gw]我应该在我的 quesitons1 回复中知道答案。 回复：FS26 未进入待机状态且初始化失败 – FS_STATE @YvanR你能看一看吗？

S32K344 - LPSPI および DMA 構成 NXPのエキスパートの皆さん、こんにちは! 私はEVKのループバックでSPI通信を開発し始めています。 SPI が Tx と Rx (マスターとスレーブの両方) の DMA で構成された例はありますか。 どうもありがとうございます！ 日時:S32K344 - LPSPIおよびDMAの構成 サポートしてくれてありがとう、 このトピックを終了します。3番目の質問については、送信者と受信者を指定できる半二重モードが答えだと思います。 どうもありがとうございます！ 日時:S32K344 - LPSPIおよびDMAの構成 ハード faul ハンドラは、main.c の 220 行目のタイプミスが原因で発生しました。 Lpspi_Ip_AsyncTransmit(&MASTER_EXTERNAL_DEVICE, TxMasterBuffer, RxMasterBuffer, NUMBER_OF_BYTES, TIMEOUT); コールバックでTIMEOUTを変更しましたが、LSPI間でデータが交換されません。 エラーをありがとう、そして申し訳ありません。 Re: S32K344 - LPSPI and DMA configuration 基本的なLPSPI + DMAのサンプルを提供していただきありがとうございます。S32K344MINI-EVBで6.0.0 RTDを使用するように、あなたのプロジェクトを修正しました。lpspi2の代わりにlpspi1を使用しました。lpspi0はArduinoヘッダーを介してlpspi1に接続されています。また、USBデバッグケーブル経由で経過時間を出力するためにlpuart6を追加しました。

LS1046A L1 および L2 キャッシュ ECC ECC は、LS1046A の L1 キャッシュと L2 キャッシュに対してデフォルトで有効になっていますか? この情報はレジスタL2CTLR_EL1に含まれていることは知っていますが、プログラムでこのレジスタにアクセスできるかどうか疑問に思います よろしくお願いいたします Re:LS1046A L1およびL2キャッシュECC こんにちは@Hector_Villarruel 、 ご返信ありがとうございます。L2CTLR_EL1 レジスタは、LS1046A リファレンス マニュアルに付属の ARM® Cortex-A72® MPCore プロセッサ TRM に示されています。いずれにせよ、ECCが常に有効になっていると述べていれば、そのようなレジスタをチェックする必要はなく、解決策としてあなたの返信を受け入れることができます 敬具

How to modify the SRAM in the LD file when installing HSE FW (AB_SWAP) on S32K311? Hello, I am installing HSE FW (AB_Swap) on S32K311 chip. I understand that 48KB SRAM needs to be reserved for HSE firmware use, but S32K311 chip only has 32KB SRAM. How should I allocate SRAM in the ld file? Re: How to modify the SRAM in the LD file when installing HSE FW (AB_SWAP) on S32K311? It is some comment related to old SBAF version. Installing AB_SWAP also updates SBAF so I would not see any issue. Re: How to modify the SRAM in the LD file when installing HSE FW (AB_SWAP) on S32K311? As described in the following figure, in addition, it can also be seen from the ld file of demo "S32K344-HSE_SW-INSTALL" that 48K SRAM is reserved. Re: How to modify the SRAM in the LD file when installing HSE FW (AB_SWAP) on S32K311? Could you point out where this information came from? I don't think HSE would require any portion of system RAM.

Inquiry of usage eMMC for i.MX8ULP I would like to use eMMC to storage boot image for i.MX8ULP Single Boot Mode. I expect that there is certain empty memory region except eMMC region storing boot image. Could I use certain empty memory region as region to storage data of Application? I would like to use eMMC not only  flash memory for saving data but memory for saving boot image simultaneously. Re: Inquiry of usage eMMC for i.MX8ULP Hi, Salas, I have checked what you said. Thanks, Hyunwoo You Re: Inquiry of usage eMMC for i.MX8ULP Hello @hwyou0212  You can check the Yocto user's guide, there is explained how to build a partitioned image for an i.MX8ULP processor: After flashing your built image you will see two partitions, boot and root.  In root partition will be stored your data applications (Linux OS). I hope this can helps to you. Best regards, --... ...-- Salas. 

SBC fault detection hi, experts Now we are working on SBC FS6513, and MCU is S32K324. and regarding the SBC fault detection, I have following questions: 1)what kind of SBC fault shall we detect in normal case? such as self-test fail, communication error, over voltage, under voltage and so on.. 2)how can we detect above fault(DTC report is required), only read DIAG register is enough? 3)is there any fault which will shut off regulator? in this case, MCU will not work. Re: SBC fault detection Hi Witness, for the fault tests description please refer to the Safety Manual attached.  With Best Regards, Jozef Re: SBC fault detection hi，Jozef Thanks so much for your kind reply. I have one another question, how can we test the SBC fault? is there any safety lib code or any other method we can refer?  Re: SBC fault detection Hi Withness, first please let me inform you, that for the the S32K3xx MCU family the recommended SBCs are newer FS26 and FS23. Please refer to this link. To your questions. 1)what kind of SBC fault shall we detect in normal case? such as self-test fail, communication error, over voltage, under voltage and so on. [A] In Normal operation, please check the RSTB, FS0B pins, depending on the WD_IMPACT_1:0 bits setting. If default, then only the RSTB pin. Then you can periodically check all the DIAG registers for faults. 2)how can we detect above fault(DTC report is required), only read DIAG register is enough? [A] Yes, only the DIAG registers are enough for the FS65.  3)is there any fault which will shut off regulator? in this case, MCU will not work. [A] We have FMEDA (Failure Mode Effects and Diagnostic Analysis) reports describing detailly impacts of the faults. Please download the documents from the FS65 product page, under the Secure section. Please also check the Safety Analysis Report.  High temperature fault will shutdown individual regulators. With Best Regards, Jozef

Questions about the internal SRAM of S32G Hi， I recently tested the bootloader to boot multi-core programs and found that the bootloader will move the complete bin file of each M7 core from QSPI to internal SRAM and then execute it. However, I noticed that the internal SRAM of S32G2 is only 8M, and the space allocated to each M7 core in LD is about 1M. Question: If my M7 core program is very large, such as 10M, how should I operate it? thanks， Re: Questions about the internal SRAM of S32G Hi chenyi,     As we know, if multi-core is enabled, it takes a long time for A-core to boot Linux. During the startup of Core A, if Core M collects 100MB of data that requires saving, how should this be handled?      I'm having this problem right now.S32G QSPI issue - NXP Community Re: Questions about the internal SRAM of S32G Hello, @youke  Thanks for your reply. In common,  the 8M of SRAM should be bigger enough to run a M7 application, I suggest checking the code to reduce the size. Regarding to XIP, yes, it is theoretically supported,  but there are no example or some documentations about XIP on S32G. It's not easy and not common to implement XIP from NOR flash on S32G,  the S32G didn't have internal nor flash, so the cpu can not directly access the nor flash. you could use a bootloader to initialize the QSPI controller and DDR controller at first and then let cpu to execute the application stored in Qflash or DDR on running time. I hope it will help.  BR Chenyin Re: Questions about the internal SRAM of S32G hi, 已解决: S32G2xx M7 execute code from external flash ? - NXP Community I saw this document introducing an XIP(eXecute-In-Place) mechanism that can execute code from external flash. Do you have any relevant materials or demos? thanks Re: Questions about the internal SRAM of S32G Hello, @youke  Thanks for you reply. As per my understanding, there is not formal sample/document regarding to this topic, you may reference the ddr init code from A53 side if willing to initialize the DDR for M7 side. Sorry for your inconvenience. BR Chenyin Re: Questions about the internal SRAM of S32G hi， Do you have any relevant demos or materials within NXP? thanks Re: Questions about the internal SRAM of S32G Hello, @youke  Thanks for your reply. Yes, I think both method may work for your situation, but as far as I know , most customers do not use DDR from M core side, it is  one option to solve your specific case. BR Chenyin Re: Questions about the internal SRAM of S32G Hi， What do you mean, if the M core wants to execute a large image, there are two options: 1. M7 first transfers a portion of the code to the internal SRAM for initializing DDR. After initializing DDR, the complete code is transferred to DDR for execution; 2. The M7 core waits first, and after the A core initializes the DDR, it moves the M7 core image to the DDR and executes it; Is that so? Re: Questions about the internal SRAM of S32G Hello, @youke  Thank for the reply. If the large size image is indeed caused by code(for example, large libs linked) and cannot be resized via linker file, then it cannot be directly loaded to the SRAM to run.  if so, I think you may have to initialize the DDR for running the code. But, unlike A53 side, the DDR is not by default enabled from sample code/bootloader from M7 side. BR Chenyin Re: Questions about the internal SRAM of S32G hi, Thank you for your reply Because I have written too much code, the compiled file is very large. Based on your answer, S32G2 does not support M7 core images exceeding 8MB because they cannot be copied to internal SRAM for execution. Is that correct? Re: Questions about the internal SRAM of S32G Hello, @youke  Thanks for your reply. I am not sure why your images are so large, since they have been far larger than the 8M ram size(24 M in total). One possible method is to check the linker file, for example,  edit it to make it to 1-2M size each. Then re-build 3 images, note that do not overlap the address of each other. If the big size of image is because multi-libs linked(large sized libs), then edit the linker file may not work for the case from my understanding. BR Chenyin Re: Questions about the internal SRAM of S32G Hi， We will use three M7 cores to run separate programs here, with each core having an image size of approximately 8M, totaling 24M, Because the internal SRAM of S32G2 is only 8MB, how should I plan the LD file thanks, Re: Questions about the internal SRAM of S32G Hello, @youke  Thanks for your post. In common, the actual size of the M7 image would not be that so big, if so, I suggest modify the linker file to change the address range of each part, thus resize the image.  BR Chenyin

RW612 SDK - Config Tools creates C prototypes without C++ guards I'm currently writing a C++-based program for the RW612.  I have integrated some of the functions in the original board.c into my own Board object, which has a .CPP source file.  I have properly declared the functions inside my own header file: #ifdef __cplusplus extern "C" { #endif /* Configures static voltage compensation and sensors, and in XIP case, change * FlexSPI clock to a stable source before clock tree (such as PLL and Main * clock) update. */ void BOARD_ClockPreConfig(void); /* Updates FlexSPI clock source and set flash to full speed. */ void BOARD_ClockPostConfig(void); /* Configure FlexSPI clock source and divider when using XIP flash. Must run * in RAM. */ AT_QUICKACCESS_SECTION_CODE(void BOARD_SetFlexspiClock(FLEXSPI_Type *base, uint32_t src, uint32_t divider)); /* De-initializes XIP flash. Must run in RAM. */ AT_QUICKACCESS_SECTION_CODE(void BOARD_DeinitFlash(FLEXSPI_Type *base)); /* Initializes XIP flash. Must run in RAM. */ AT_QUICKACCESS_SECTION_CODE(void BOARD_InitFlash(FLEXSPI_Type *base)); #ifdef __cplusplus } // extern "C" #endif However, when I compile, I get an error that both BOARD_ClockPreConfig() and BOARD_ClockPostConfig() have previously been defined with C++ linkage: Errors showing conflicting C/C++ linkageErrors showing conflicting C/C++ linkage I examined clock_config.h to locate the prototypes for those two functions: Function prototypes in clock_config.hFunction prototypes in clock_config.h The problem is that those two prototypes (and the AVPLL config extern declaration) are not placed inside an extern "C" { } declaration.  Several things in clock_config.h do appear within an extern "C" { }, but those items do not, and it throws off the compiler.  This is additionally frustrating because clock_config.h is automatically generated by MCU Config Tools, so I have to either disable re-generation of clock_config.h or manually edit in an extern "C" { } declaration each time I re-generate code. Please fix this defect in MCU Config Tools for the RW612.  Thank you. Dana M. Re: RW612 SDK - Config Tools creates C prototypes without C++ guards Dear @dmarks_ls , Good job! and thanks for you sharing! I will report the issue to internal team. Anyway, fortunately, this did not affect the continuation of your project! In the current situation, you can only proceed according to the method you have adopted. Thanks! Regards, weidong Re: RW612 SDK - Config Tools creates C prototypes without C++ guards No, the compilation issues are resolved because the declarations in the header file are recognized as having C binding in all locations.  I've attached the original header file and my fixed version of the header file.  Please review the Config Tools for RW612 and make sure that any extern declarations, type declarations, and function prototypes are enclosed by an extern "C" { } declaration, thanks. Dana M. Re: RW612 SDK - Config Tools creates C prototypes without C++ guards Dear @dmarks_ls , After   editing in an extern "C" { } in config_clock.h,  Are there any compilation errors in the code? Thanks! Regards, weidong

PCA9509: VIL 0.15V is too low for my application, any option with higher VIL? Hi Team, Originally, I would like to use PCA9509 as voltage translator of 5V<-->3.3V, but when I checked the details, I found VIL of PCA9509 is 0.15V, which is too low for slave 6# in below schematic. Can you kindly recommend an option with higher VIL? For example, 0.8V or higher.  Thank you.    Kind Regards, Boler Re: PCA9509: VIL 0.15V is too low for my application, any option with higher VIL? Hi Guowei, It's great, thanks. Re: PCA9509: VIL 0.15V is too low for my application, any option with higher VIL? HI Boler： You can refer to below: Re: PCA9509: VIL 0.15V is too low for my application, any option with higher VIL? Hi Guowei, Thanks for the quick update. I also notice a similar part PCA9306 as NTS0102 , any difference? Re: PCA9509: VIL 0.15V is too low for my application, any option with higher VIL? Hi Boler If only for  level translating we have lots: NVT2002.NTS0102: Voltage Level Translators (Level Shifters) | NXP Semiconductors NTS0102 | NXP Semiconductors Re: PCA9509: VIL 0.15V is too low for my application, any option with higher VIL? Hi Guowei, I use PCA9509 only for level translating, so I would like to change PCA9509 to a common voltage-level translator, such as TI TCA39306. Can you please advise NXP option in place of TI TCA39306? Thank you. Kind regards, Boler Re: PCA9509: VIL 0.15V is too low for my application, any option with higher VIL? Hi Boler You can consider about PCA9617!

Basics of Bus Fault in S32DS Program Hi team, I was trying to run a simple complementary program on a S32K358 microcontroller using the S32DS IDE. But i'm facing an error called as bus fault in the program. I have attached the highlighted screenshot of the error message below. I ran the same program in an S32K344 evaluation board and there I didn't face such an error. Please explain me this fault and also the solution to this as I'm new to this IDE's programming. It would be really helpful. S32DS-S32PLATFORM #S32K358 #BusFault  Re: Basics of Bus Fault in S32DS Program Hi @abdul_rahman  I sent you a private message Re: Basics of Bus Fault in S32DS Program Hi @VaneB  This is the Lpspi_Ip_UpdateTransferMode() function in my code Lpspi_Ip_StatusType Lpspi_Ip_UpdateTransferMode(uint8 Instance, Lpspi_Ip_ModeType Mode) { Lpspi_Ip_StateStructureType* State; Lpspi_Ip_StatusType Status = LPSPI_IP_STATUS_SUCCESS; #if (LPSPI_IP_DMA_USED == STD_ON) Dma_Ip_LogicChannelTransferListType DmaTcdList[1u]; #endif #if (LPSPI_IP_DEV_ERROR_DETECT == STD_ON) DevAssert(Instance < LPSPI_INSTANCE_COUNT); #endif State = Lpspi_Ip_apxStateStructureArray[Instance]; #if (LPSPI_IP_DEV_ERROR_DETECT == STD_ON) DevAssert(NULL_PTR != State); #endif /* Transfer mode can be changed when no transfers are in progress. */ if (State->Status != LPSPI_IP_BUSY) { State->TransferMode = Mode; #if (LPSPI_IP_DMA_USED == STD_ON) if (TRUE == State->PhyUnitConfig->DmaUsed) { /* Activate TX DMA and RX DMA interrupt in interrupt mode or disable then in polling mode. */ DmaTcdList[0u].Param = DMA_IP_CH_SET_CONTROL_EN_MAJOR_INTERRUPT; switch (State->TransferMode) { case LPSPI_IP_POLLING: /* Disable DMA major interrupt. */ DmaTcdList[0u].Value = 0u; break; case LPSPI_IP_INTERRUPT: /* Enable DMA major interrupt. */ DmaTcdList[0u].Value = 1u; break; default: /* Nothing to do */ break; } (void)Dma_Ip_SetLogicChannelTransferList(State->PhyUnitConfig->TxDmaChannel, DmaTcdList, 1u); (void)Dma_Ip_SetLogicChannelTransferList(State->PhyUnitConfig->RxDmaChannel, DmaTcdList, 1u); } #endif } else { Status = LPSPI_IP_STATUS_FAIL; } return Status; } The below mentioned are the SPI configurations, SpiDriver   SpiGeneral Re: Basics of Bus Fault in S32DS Program Hi @abdul_rahman  It seems that your code fails in the Lpspi_Ip_UpdateTransferMode() function. How do you call this function? Also, could you share the SPI configurations? Re: Basics of Bus Fault in S32DS Program Dear @VaneB, Here is the screenshot of the right side of debug window you requested. What could be the problem? Re: Basics of Bus Fault in S32DS Program Hi @abdul_rahman  Could you share a picture of the Debug tab displayed on the left side of the S32DS during debugging? This tab shows where the code failed. Re: Basics of Bus Fault in S32DS Program Hi @VaneB  In a new custom project file, I'm now experiencing this type of bus and hard fault with the message highlighted as shown, , I haven't connected any peripherals or devices to the custom microcontroller. Do you think that the fault is due to the SPI data not being transmitted/received to the controller? Or is it something else? Re: Basics of Bus Fault in S32DS Program Hi @VaneB  You were right about the failure in the Clock_Ip_init() function. The problem was not with the hardware. The problem was in specifying the right clock frequency in the FXOSC section in the clock configuration tool (which makes the Clock_Ip_init() function). My custom hardware was using 40 MHz oscillator and I was running the code in 16 MHz FXOSC in the clock configuration tool of my program. Once I changed that to 40 MHz and uploaded the code again, the busfault error was gone and the code was running.  Thanks for all the help you have given me sir. I deeply appreciate it. Re: Basics of Bus Fault in S32DS Program Hi @abdul_rahman  From the shared images I deduce that it is a clock problem because the failure occurs in the Clock_Ip_init() function. To verify if this is the case, test the Clock_Ip_Example_S32K358 making the necessary changes to match your HW. Re: Basics of Bus Fault in S32DS Program Hi @VaneB  As per the Hardware Design Guidelines for S32K3xx Microcontrollers the crystal oscillator design of our hardware seems to be correct. What could be other possible hardware/software reason(s) for the BusFault and HardFault errors? Re: Basics of Bus Fault in S32DS Program Hi @abdul_rahman  It seems to be a hardware problem. Since the Hard fault occurs during clock initialization, a possible root cause could be the connections of the EXTAL and XTAL pins, for this you can use as a reference the Hardware Design Guidelines for S32K3xx Microcontrollers. Re: Basics of Bus Fault in S32DS Program Hi @VaneB  I ran the Emios_PWM_Ip example code, that comes with the SDK, on my custom board with the S32K358 controller. I'm still getting the same HardFault error mentioned before. What could be the problem then? Re: Basics of Bus Fault in S32DS Program Hi @VaneB  Yes, you are right. I'm using a custom made board which uses the S32K358. What may the problem then? Re: Basics of Bus Fault in S32DS Program Hi @abdul_rahman  I have flashed your code on my S32K3X8EVB-Q289 and I did not get a bus Fault. Are you using a custom board? Is it necessary to use both Cortex-M7_0_0 (Boot) and Cortex-M7_0_2 files for programming S32K358? No, depends if you want to work with multicore.  Why does the design studio create two files for this processor and only one file for S32K344? Because S32K358 devices have 1 LS core and 1 single core and S32K344 devices have only 1 LS core. So one project is created for each device core. Re: Basics of Bus Fault in S32DS Program Hi @VaneB  I have attached the .zip file of the project that the code is in. I'm using version 4.0.0 of PlatformSDK kit from NXP.  P.S.: Is it necessary to use both Cortex-M7_0_0 (Boot) and Cortex-M7_0_2 files for programming S32K358? Why does the design studio make two files for this processor and only one file for S32K344?? Re: Basics of Bus Fault in S32DS Program Hi @abdul_rahman  BusFault: detects memory access errors on instruction fetch, data read/write, interrupt vector fetch, and register stacking (save/restore) on interrupt (entry/exit). HardFault: is the default exception and can be triggered because of an error during exception processing, or because an exception cannot be managed by any other exception mechanism. If there is no handler for a specific fault, it is escalated to HardFault. As the code works with a S32K344, there could be a configuration problem. If it is possible could you share your project or configurations? Also, which RTD version are you using?  BR, VaneB

Industrial i.MX8QM clock frequencies Hi everyone, We are currently doing tests on the MIMX8QM5CVUFFAB and found some strange behaviour regarding clocks. The first thing we noted is that even though the clock is limited to 1.3 GHz for the Cortex A72 and 1.104 GHz for the Cortex A53, the cpufreq driver allows us to set the higher frequency of 1.6 GHz and 1.2 GHz. The SCFW seems to correctly ignore the higher frequencies but this leads to a missmatch between cpufreq and the actual clock rate: root@apalis-imx8-15556460:~# cat /sys/bus/cpu/devices/cpu4/cpufreq/scaling_cur_freq 1596000 root@apalis-imx8-15556460:~# cat /sys/kernel/debug/clk/clk_summary |grep a72 a72_clk 0 0 0 1296000000 0 0 50000 Y cpu4 no_connection_id root@apalis-imx8-15556460:~# cat /sys/bus/cpu/devices/cpu0/cpufreq/scaling_cur_freq 1200000 root@apalis-imx8-15556460:~# cat /sys/kernel/debug/clk/clk_summary |grep a53 a53_clk 0 0 0 1104000000 0 0 50000 Y cpu0 We would expect that this is either solved by a special cpufreq driver or then by a fdt fixup in U-Boot. However, I can't find any of this solutions in the BSP. Can you confirm that this is currently not implemented? A second clocking issue affects the GPU, even though according to the datasheet the GPU should only run at 625 MHz it runs at 800MHz: root@apalis-imx8-15556460:~# cat /sys/kernel/debug/gc/clk gpu0 mc clock: 797983833 HZ. gpu0 sh clock: 996002801 HZ. gpu1 mc clock: 798002539 HZ. gpu1 sh clock: 995989749 HZ. root@apalis-imx8-15556460:~# cat /sys/kernel/debug/clk/clk_summary |grep gpu gpu_shader1_clk 0 0 0 996000000 0 0 50000 Y 54100000.gpu shader gpu_core1_clk 0 0 0 798000000 0 0 50000 Y 54100000.gpu core gpu_shader0_clk 0 0 0 996000000 0 0 50000 Y 53100000.gpu shader gpu_core0_clk 0 0 0 798000000 0 0 50000 Y 53100000.gpu Here the SCFW does not limit the clock, which seems to be a violation of what is written in the datasheet. My expectation would also be here that there is a fdt fixup in U-Boot to address this but I could not find it. Can you confirm that this is currently not implemented? The version of the SCFW, ATF and U-Boot should be recent enough to properly support the i.MX8QM with the 1.3 GHz limitation: U-Boot 2024.04-34984-g64f00b21ff8 (Dec 04 2024 - 14:42:45 +0100) CPU: NXP i.MX8QM RevB A53 at 1104 MHz at 33C DRAM: 4 GiB Core: 203 devices, 24 uclasses, devicetree: separate MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... OK In: serial Out: serial Err: serial Model: Toradex 0091 Apalis iMX8QM 4GB WB IT V1.1A Serial#: 15556460 Boot: MMC0 Reset cause: POR BuildInfo: - SCFW 83624b99, SECO-FW c9de51c0, IMX-MKIMAGE ca5d6b2d, ATF 616a458 - U-Boot 2024.04-34984-g64f00b21ff8 Best regards, Stefan i.MX 8 Family | i.MX 8QuadMax (8QM) | 8QuadPlus Linux Re: Industrial i.MX8QM clock frequencies current bsp is based on nxp mek board, don't find specific bsp for industrial, you can change the bsp by yourself Re: Industrial i.MX8QM clock frequencies Hi @joanxie  Thanks for the update. Can you point me to the right BSP for the industrial version of the i.MX8? Thanks and best regards Stefan Re: Industrial i.MX8QM clock frequencies the bsp you used isn't for industrial, so the A72 core define 1596000000 as max, you can remove this from a72_opp_table: opp-table-1 linux-imx/arch/arm64/boot/dts/freescale/imx8qm.dtsi at lf-6.6.y · nxp-imx/linux-imx · GitHub you also can refer to this workaround, for the 1.3G imx8qm  [OUTDATED] Workaround for de-rating i.MX 8QM/QP parts before SCFW 1.16.0 releases - NXP Community Re: Industrial i.MX8QM clock frequencies Hi @joanxie  The following versions are used: SCFW: 1.17.0 (83624b99) U-Boot: lf_v2022.04 https://github.com/nxp-imx/uboot-imx/tree/lf_v2024.04 Linux: lf-6.6.y https://github.com/nxp-imx/linux-imx/tree/lf-6.6.y Regards, Stefan Re: Industrial i.MX8QM clock frequencies what bsp version and SCFW version do you test? let me double check it

如何将文本置于 spangroup 的中心？ 中心文本似乎是 spangroup 中缺少的一个选项。如何最好地实现这一目标？ 回复：如何将文本置于 spangroup 的中心？ 如果您的建议放在屏幕下方右侧栏的“自定义”代码按钮中，则有效。 如果放在代码中，它会被覆盖。如果放置在事件中，编译就会崩溃。 回复：如何将文本置于 spangroup 的中心？ 如果在 custom.c 中，则崩溃并作为一个事件。 回复：如何将文本置于 spangroup 的中心？ 似乎每次重新编译代码时，这个手动添加的内容都会丢失。有没有一种方法可以减少代码被破坏的可能？ 图形指南 1.8.1-GA

S32K344-Memory configuration after HSE_B firmware usage feature flag is enabled Hello： I found in the section [32.3.1.2 Configuration details when the HSE_B firmware usage feature flag is enabled] in RM that the Reserved area, Application flash memory area, and Application data flash memory area have all been reduced. What data are stored in these areas after the HSE firmware is installed and used? BestRegards, Simon Re: S32K344-Memory configuration after HSE_B firmware usage feature flag is enabled You'll find out when you download HSE_B Firmware Reference Manual. It is a secure file, so following procedure is needed to follow unless you have already done it before: https://www.nxp.com/docs/en/user-guide/nxp-secure-access-rights-registration.pdf For better understanding you may also see following link: https://www.nxp.com/support/support/secure-access-rights:SEC-ACCESS

MC33774无法给出AIN4~AIN7测量结果的正确值 我正在调试MC33774程序并使用应用模式来测量温度和电压。我们有一个 MCAL 包，我调用这个包中的函数。我发现在恩智浦提供的示例代码中，Bcc_774a_MSR_SetMode 函数被调用了两次。为什么这个寄存器要被写入两次？现在出现了一个很奇怪的问题，MC33774 的 AIN4~AIN7 测量结果总是给出无效值。但是 VC 和 AIN0~AIN3 的测量结果正常，它们属于主数字模块。我尝试读取周期模式测量结果寄存器和应用模式测量结果寄存器，但所有数据都无效（0x8000）。我想知道是否有人可以帮助我解决这个问题。 并且我将MC33774工作时记录的SPI数据上传到附件中。 请帮我解决这个问题。 谢谢