[imx RT105x] Issues Using Dual External Flash on RT105x (Port A1: OK, Port B1: Unresponsive) Hi everyone, I’m currently working with an RT105x microcontroller and two identical 32MB external flash chips. FlashA1 is connected to Port A1 and used for XIP (execute-in-place). FlashB1 is connected to Port B1 and intended for data storage. So far, I’ve: Configured the clock and pin muxing Developed a custom driver to interface with both chips Everything works fine on FlashA1: I can read, write, erase—no issues. However, FlashB1 doesn’t respond to the same operations, even though the setup is mirrored. Has anyone encountered something similar using this dual-flash configuration? Do you have any working examples or tips you could share? I’d be happy to provide more technical details if needed. Best regards, Biagio i.MXRT 105x Re: [imx RT105x] Issues Using Dual External Flash on RT105x (Port A1: OK, Port B1: Unresponsive) The issue is that Port A1 and B1 are connected to the same flexspi interface so access to each one cannot be done simultaneously. To avoid this, please move the instructions that access B1 to RAM so both memories do not collide. Best regards, Omar

TEA19161+19162 & MCU Based CC-CV 2.5kW Charger Concept Hi team, I’m evaluating a 2.5 kW 48 V CC–CV charger concept similar to ST’s reference design (LLC with MCU control): https://www.st.com/en/evaluation-tools/stdes-2kw5ch48v.html Goal Develop the power stage using NXP’s TEA19161 (LLC resonant controller) together with an MCU for telemetry, protection, and CC–CV management. Preliminary targets Input: 390–400 VDC from PFC (or 325–420 VDC if a wider range is preferred) Output: 48 V nominal, up to ≈50 A (≈2.4–2.5 kW) Regulation: CC–CV with smooth transition and fast OCP response Efficiency: ≥92 % peak, ≥93 % at 50–100 % load Topology: Full-bridge LLC with synchronous rectification on the secondary, using the two gate-drive outputs of the TEA19161 to generate the complementary signals required for full-bridge operation, and external stronger drivers to handle the higher gate charge and power level. Key questions 1. CC–CV control concept I plan to implement two op-amp loops on the secondary side: one for voltage sensing and one for current sensing (via a shunt). The MCU will adjust both reference levels dynamically to realize the CC↔CV transition. The combined feedback from these two loops will then drive a single optocoupler back to the TEA19161 for primary-side control. Could you confirm whether this approach is compatible with TEA19161? 2. Power scalability Once reconfigured for full-bridge operation with stronger gate drivers, is it realistic to reach ≈2.5 kW output power using TEA19161 Thanks in advance for your support and any design recommendations for using TEA19161 + MCU in this 2.5 kW CC–CV charger project. Re: TEA19161+19162 & MCU Based CC-CV 2.5kW Charger Concept HI We only have LLC controller and newest part is TEA2226AT | Digital Configurable LLC Controller | NXP Semiconductors But this part can drive maximum up to 1KW,so in your design should have two in parallel to get 2KW. You should add some circuits to achieve average/equal current in both controllers.

FS26 S32K3 FLT_ERR_CNT cannot decrease to 0 in Sbc_fs26_InitDevice(); Hi, when i initialized FS26 with S32K311, watchdog period = 32ms, watchdog duty cycle = 37.5%OPEN, watchdog recovery = 64ms, but in " Decrease FLT_ERR_CNT to 0 with WD_ERR_LIMIT good WD refresh", I got u8ErrorCounter = 1 in below codes. I don't know the meaning about "with WD_ERR_LIMIT good WD refresh", is that means it need to plus a WDrefresh routine code? Hope your answer! Kate Re: FS26 S32K3 FLT_ERR_CNT cannot decrease to 0 in Sbc_fs26_InitDevice(); Thanks a lot ! Re: FS26 S32K3 FLT_ERR_CNT cannot decrease to 0 in Sbc_fs26_InitDevice(); Hi Kate Please following the above picture to feed WD,you can try and should be no problem. Re: FS26 S32K3 FLT_ERR_CNT cannot decrease to 0 in Sbc_fs26_InitDevice(); Hi guoweisun, Thanks for the description! About the pic, open duty is 50% but there is 3/4 on the timeline. To my understanding, if it set 50% duty , it will be 1/2 between WD refresh and WD refresh 1. That is, if I want to set the time between WD refresh and WD refresh 1, the function must be WindowPeriod * WindowDc. Above all, is there something wrong? Re: FS26 S32K3 FLT_ERR_CNT cannot decrease to 0 in Sbc_fs26_InitDevice(); Finally you must use the normal mode not the debug mode,you can refer to below  for feed WD: Re: FS26 S32K3 FLT_ERR_CNT cannot decrease to 0 in Sbc_fs26_InitDevice(); Hi guoweisun, If I was in Debug mode, I can have a good WDfresh like below. Then I can get SBC initialize OK. But in Normal mode, I got a bad WDfresh like below. Then I can't initialize SBC. What states I need to set ? Re: FS26 S32K3 FLT_ERR_CNT cannot decrease to 0 in Sbc_fs26_InitDevice(); Please see below: Re: FS26 S32K3 FLT_ERR_CNT cannot decrease to 0 in Sbc_fs26_InitDevice(); Hi guoweisun, Thanks for your patience! I means what can make FS_WD_ANSWER change. If I just refresh one time, FS_WD_ANSWER is changed from 0xa54d to 0x4a9a. What can I  change FS_WD_ANSWER from 0x4a9a to 0x9535? Re: FS26 S32K3 FLT_ERR_CNT cannot decrease to 0 in Sbc_fs26_InitDevice(); HI Kate Don't understand you wrote only one time to change the WD. If you define the FS_WD_TOKEN register content, you have to calculate and feed the WD answer each time. Re: FS26 S32K3 FLT_ERR_CNT cannot decrease to 0 in Sbc_fs26_InitDevice(); Hi guoweisun, I used "Sequence to enter normal mode with a Watchdog Challenger" because of S32K311. The change timing of FS_WD_ANSWER is when Sbc_fs26_WdChangeToken be used, right? But now my code used Sbc_fs26_WdChangeToken when Sbc_fs26_InitFSConfigure is used. That means it just one time to change the wd answer. Where should i add Sbc_fs26_WdChangeToken to occur the wd answer changing? Re: FS26 S32K3 FLT_ERR_CNT cannot decrease to 0 in Sbc_fs26_InitDevice(); Hi  You can refer to below: Sequence to enter normal mode with a Watchdog Simple //INIT FS and simple WD enabled required //Open WD window SET_REG:FS26:Safety:FS_WDW_DURATION:0x008B SET_REG:FS26:Safety:FS_NOT_WDW_DURATION:0xF144 //Send 1 good wd refresh to close INIT window SET_REG:FS26:Safety:FS_WD_ANSWER:0x5AB2 //clean fault error counter SET_REG:FS26:Safety:FS_WD_ANSWER:0x5AB2 SET_REG:FS26:Safety:FS_WD_ANSWER:0x5AB2 SET_REG:FS26:Safety:FS_WD_ANSWER:0x5AB2 SET_REG:FS26:Safety:FS_WD_ANSWER:0x5AB2 SET_REG:FS26:Safety:FS_WD_ANSWER:0x5AB2 SET_REG:FS26:Safety:FS_WD_ANSWER:0x5AB2 //Exit dbg mode SET_REG:FS26:Safety:FS_STATES:0x4000 //release FS0B and FS1B SET_REG:FS26:Safety:FS_RELEASE_FS0B_FS1B:0xB2A5 Sequence to enter normal mode with a Watchdog Challenger //INIT FS and WD Challenger required //Open WD window SET_REG:FS26:Safety:FS_WDW_DURATION:0x008B SET_REG:FS26:Safety:FS_NOT_WDW_DURATION:0xF144 //Send 1 ZD refresh to close INIT window SET_REG:FS26:Safety:FS_WD_ANSWER:0xa54d //clean fault error counter SET_REG:FS26:Safety:FS_WD_ANSWER:0x4a9a SET_REG:FS26:Safety:FS_WD_ANSWER:0x9535 SET_REG:FS26:Safety:FS_WD_ANSWER:0x2a6a SET_REG:FS26:Safety:FS_WD_ANSWER:0x54d4 SET_REG:FS26:Safety:FS_WD_ANSWER:0xa9a9 SET_REG:FS26:Safety:FS_WD_ANSWER:0x5353 //Exit dbg mode SET_REG:FS26:Safety:FS_STATES:0x4000 //release FS0B and FS1B SET_REG:FS26:Safety:FS_RELEASE_FS0B_FS1B:0xA565 Re: FS26 S32K3 FLT_ERR_CNT cannot decrease to 0 in Sbc_fs26_InitDevice(); Hi guoweisun, Thanks for your reply. How would I continue refresh WD? If I use a timer to count, it will shut down in Sbc_fs26_TimeWaitClearFault(). Or is there a watchdog duty open example? In S32DK, there is only a infinite watchdog example. Re: FS26 S32K3 FLT_ERR_CNT cannot decrease to 0 in Sbc_fs26_InitDevice(); Hi  For your question: 1: Is that means it need to plus a WDrefresh routine code? [gw]Correct,you need continue to refresh WD till the fault error counter decrease into 0.

Issue Debugging OpenThread Images on JN5189DK6 with J-Link – "No source available for main()" Dear NXP Support Team, I am currently working with the JN5189DK6 development kit and attempting to flash and debug an OpenThread RCP image ( ot-rcp.elf) built from the OpenThread stack. I am encountering an issue where the debugger is unable to resolve symbols, specifically showing: No source available for "main() at 0x5da"   Configuration Details: Target MCU: JN5189DK6 SDK Used: SDK_2_6_16_JN5189DK6 OpenThread Version/Reference: Based on instructions from ot-nxp v1.4.0 README Debugger: Segger J-Link (SWD interface) Debugging Interface: Not using CMSIS-DAP (as mentioned in NXP guide) Flashing Format: .hex and .elf Debugging File: ot-cli-ftd.elf IDE Version : MCUXpressoIDE_24.12.148 Steps Taken: Built the OpenThread RCP firmware for the JN5189 target with debug symbols enabled. Connected the Segger J-Link debugger to the board using the SWD interface. Loaded the ot-rcp.elf into the debugger for symbol reference. Started a debug session, but encountered the message: No source available for "main() at 0x5da" Attachments: Board configuration images Debugging file (ot-rcp.elf) Project configuration screenshots Re: Issue Debugging OpenThread Images on JN5189DK6 with J-Link – "No source available for main( Hello, Vikash. After consulting with R&D, I think I can offer a better solution. As I said, JN5189 and K32W0x1 are compatible chips from the same family, the K32W0x1 being the upper trim of JN, with BLE added. In the K32W0x1 ot-nxp examples, there is a rcp_only_uart_dma configuration that is recommended to be used in your actual use case, RCP without frame control. You can check it out in script/build_k32w061. OT_OPTIONS_RCP_ONLY_UART_DMA=( "-DOT_RCP_UART_DMA=ON" "-DOT_APP_CLI=OFF" "-DOT_FTD=OFF" "-DOT_MTD=OFF" "-DOT_1_2_SUPPORT=ON" "-DUART_BAUD_RATE=1000000" ) readonly OT_OPTIONS_RCP_ONLY_UART_DMA This example uses a special DMA library which improves the UART and radio modules handling. You can build the K32W0 example and use it on JN5189 for your testing. BR, Mihai Re: Issue Debugging OpenThread Images on JN5189DK6 with J-Link – "No source available for main( Hi Mihai, 1) We are constrained to the JN5189 since we already have a significant number of devices deployed with this hardware. 2) I’ve tried using a baud rate of "1000000," but I’m still encountering a framing error during communication. I’ve tested with both UART_DRIVER and SERIAL_MGR. Why is SERIAL_MGR preferred? To debug further, I enabled logs and checked the USART FIFO Overflow Register values. I noticed that the RXERR bit is being set in FIFOSTAT. For reference, USART0 is clocked at 32 MHz (sourced from XTAL), and the main clock is running at 48 MHz. BR, Vikash Re: Issue Debugging OpenThread Images on JN5189DK6 with J-Link – "No source available for main( Hello Mihai, Thank you for your patience and the time you spent addressing each of the four points I raised. Your clear explanations have given me clarity and helped me understand the issues better. BR, Vikash Re: Issue Debugging OpenThread Images on JN5189DK6 with J-Link – "No source available for main( Hello, Vikash. Regarding 1), the difference between routing the UART between LPC-Link2 port and the FTDI port is that on the FTDI port, the UART is routed to the FT230XS FTDI chip on the DK6 board, which translates the signals to USB on a more "hardware" logic, implying that it's done faster. On the LPC-Link2 port, the signals are passed through the LPC4322 chip, which acts also as a debugger probe and I suspect that it implies a more "software" approach, with more processing leading to some delays. We haven't seen any issues using that port on our scenarios, but we do suggest using the FTDI port for real life scenarios, due to the limitations which I pointed out. One thing I can suggest to you is to switch the firmware running on the LPC Link2 chip. You can do this by putting the LPC in DFU mode (switch JP5 from NORMAL to DFU) and use the LPCScrypt software to do the change. A user guide is available in the link. You have the option to use the CMSIS or the JLink firmwares. Regarding 2), I suggest using UART_USE_SERIAL_MGR instead of UART_USE_DRIVER. The changes I suggested in the post earlier should also be done: - OPENTHREAD_CONFIG_LOG_OUTPUT to OPENTHREAD_CONFIG_LOG_OUTPUT_PLATFORM_DEFINED in src/k32w0/jn5189/openthread-core-jn5189-config.h - OPENTHREAD_CONFIG_LOG_LEVEL to OT_LOG_LEVEL_DEBG in the same file Regarding 3), yes, I remember capturing SWO debug lines in TeraTerm so it should work. Regarding 4), the change in linker file, RAM0: 0x4000400 was done to accommodate RAM needs from running the ROM code at boot (scratch RAM) and you can also change the settings in MCUXpresso to match, but I don't think it has any impact if you keep the old settings, as we are not loading any applications in RAM when writing the board. JN5189 is a legacy part and some things are out of date and won't be updated in next releases. Furthermore, JN5189 and K32W0x1 are to be removed from ot-nxp repository in next releases and enter a maintenance phase on the last released version. If you desire to develop a solution with NXP OpenThread Wireless silicon that will benefit from ongoing support regarding stack and SDK maintenance, I can suggest you to have a look at the MCXW7x family. BR, Mihai Re: Issue Debugging OpenThread Images on JN5189DK6 with J-Link – "No source available for main( Hi Mihai,   I’m currently facing several issues while setting up UART communication and debug logging for the JN5189 in my OpenThread Border Router (OTBR) environment. I’ve detailed the points below:     1) When I use the LPC-LINK2 port (even without the debugger, solely for UART communication), I encounter HDLC parse errors or framing errors shortly after launching the otbr-agent. In contrast, using the FTDI-USB UART interface works reliably, and the agent maintains communication unless exposed to heavy command loads.  I have attached the jumper setting when using the LPC-LINK2 port. (Refer to the attached image : Jn5189_Debug_port_jumper_config_.png)   2) I attempted to enable debug logs via USART1 (TX/RX on pins 10/11), considering the compatibility between K32W0 and JN5189. However, when I connect a USB-UART adapter and monitor the output via Minicom, no logs are displayed. Also, the otbr-agent fails to receive messages and eventually times out.   Here’s what I’ve modified so far:   In jn5189-sdk-config.h: #define UART_USE_DRIVER 1 #define UART_USE_SERIAL_MGR 0 #define UART_USE_DRIVER_LOG 1 #define UART_USE_SERIAL_MGR_LOG 0 #define UART_USE_SWO_LOG 0   Added the following to the CMake config: option(OT_DEBUG_CONSOLE_ENABLE "Enable debug console on gOtLogUartInstance" ON)   if (OT_DEBUG_CONSOLE_ENABLE) target_compile_definitions(${NXP_DRIVER_LIB} PUBLIC -DgUartDebugConsole_d=1 ) endif()   In the build_jn5189 script, under OT_OPTIONS, I added: -DOT_DEBUG_CONSOLE_ENABLE=ON   Despite these changes, no output is observed on USART1, and OTBR communication fails.   3) Is it possible to capture SWO debug logs using Minicom or similar terminal applications? If not, what tool or method is recommended for viewing SWO output on JN5189?   4) While creating the project and setting the RAM regions via: -> Project → Properties → C/C++ Build → MCU Settings → JN5189 → Apply & Close -> I noticed a mismatch between the RAM boundary values shown in the IDE and those defined in the linker script.   In the IDE: (Refer to the attached image :JN5189_Mem_Layou_Ide.png) RAM0: 0x4000000, Size: 0x15FE0 RAM1: 0x4020000, Size: 0x10000   In the jn5189 linker script (src/k32w0/jn5189/jn5189.ld) : RAM0: 0x4000400, Size: 0x0015C00 RAM1: 0x4020000, Size: 0x10000   Which of these memory configurations should be considered correct? Should we align the IDE settings with the linker script, or vice versa?     BR, Vikash    Re: Issue Debugging OpenThread Images on JN5189DK6 with J-Link – "No source available for main( Hello, Vikash. The debug logs are printed on the USART1 instance. You can check the JN5189 User Manual , table 3 about what other pins can be used for USART1. JN5189 has two USART instance, with USART0 for the OpenThread CLI/Spinel communication. On a quick search, we have: USART0_TXD: PIO3, PIO8, PIO18. UASRT0_RXD: PIO2, PIO9, PIO19. USART1_TXD: PIO0, PIO6, PIO10, PIO20. UASRT1_RXD: PIO1, PIO7, PIO11, PIO19. BR, Mihai Re: Issue Debugging OpenThread Images on JN5189DK6 with J-Link – "No source available for main( Hi Mihai, Thanks for your suggestion. Unfortunately, the end platform where I’ll be integrating the JN5189 doesn’t support hardware flow control, so I’ll need to explore alternatives that work without it. One follow-up question:- 1) is it possible to enable and redirect the debug logs by configuring a GPIO as a different USART instance and then view the output using Minicom? Best Regards, Vikash Re: Issue Debugging OpenThread Images on JN5189DK6 with J-Link – "No source available for main( Hello, Vikash. What I can suggest is to have a look at K32W0 configuration for flow control. More specifically, in script/build_k32w061, there is a build option: OT_OPTIONS_RCP_ONLY_UART_FLOW_CONTROL=( "-DOT_RCP_FLOW_CONTROL=ON" "-DOT_APP_CLI=OFF" "-DOT_FTD=OFF" "-DOT_MTD=OFF" "-DUART_BAUD_RATE=1000000" ) This sets to ON the OT_RCP_FLOW_CONTROL option, which enables the SDK option  gUartHwFlowControl_d Looking into the SDK in boards/ /wireless_examples/openthread/reed/bm/board.c, you can see that this enables RTS and CTS pin usage for flow control on UART0, by default on PIO6 for RTS and PIO7 for CTS. You can adjust the pins to other USART0 used pins by referencing Table 3 in JN5189 User Manual . This should improve the stability of the UART communication. K32W0x1 is pin compatible with JN5189, it's actually the JN5189 variant with BLE, so you can take as reference the K32W0 SDK. BR, Mihai Re: Issue Debugging OpenThread Images on JN5189DK6 with J-Link – "No source available for main( Hi Mihai, I’ve tried running the application with a free run configuration and made sure that no breakpoints are set, but I’m still encountering the same issue while checking through the LPCLINK2 port. Specifically, on the RCP side, we’re observing that bytes are being dropped or missed when the OTBR is transmitting high-volume(100-150 Bytes) messages in quick succession. This seems to indicate a potential issue with handling high RX load or buffer overflows(at present Rx buffer value is 10kb). Please let me know if there are any additional settings or steps I should verify, or if there’s something else that might be causing this behavior. BR, Vikash Re: Issue Debugging OpenThread Images on JN5189DK6 with J-Link – "No source available for main( Hello, Vikash. You are seeing RCP timeouts on the host side, meaning the MPU/MCU host running ot-daemon, which is normal, because while you are debugging the JN5189 RCP application, you are stopping the code execution on the chip and implicitly, the UART communication to the host. Using the FTDI USB doesn't stop the processor and communication, so it is normal to not see such events. BR, Mihai Re: Issue Debugging OpenThread Images on JN5189DK6 with J-Link – "No source available for main( Hi Mihai, I’m running into a repeatable “rcp out” error whenever I debug through the LPC-Link2 onboard probe in MCUXpresso IDE—even when I launch the session with no breakpoints set. If I switch to an FTDI-USB connection, with the previously flashed binary, there is no issue of time-out at all. Regards Vikash Re: Issue Debugging OpenThread Images on JN5189DK6 with J-Link – "No source available for main( Hi Mihai, I've followed the above-mentioned steps, and I'm able to successfully direct the logs to IDE. Thanks for your assistance. BR Vikash Re: Issue Debugging OpenThread Images on JN5189DK6 with J-Link – "No source available for main( Hello, Thanks for your prompt reply. I'll follow the above specified steps and get back to you. Re: Issue Debugging OpenThread Images on JN5189DK6 with J-Link – "No source available for main( Hello. Logging for any ot-nxp app on JN5189 can be enabled by modifying some of the defines from the build. From my memory, as I worked on this some time ago, you need to modify: - OPENTHREAD_CONFIG_LOG_OUTPUT to OPENTHREAD_CONFIG_LOG_OUTPUT_PLATFORM_DEFINED in src/k32w0/jn5189/openthread-core-jn5189-config.h - OPENTHREAD_CONFIG_LOG_LEVEL to OT_LOG_LEVEL_DEBG in the same file - UART_USE_SWO_LOG to 1 in src/k32w0/jn5189/jn5189-sdk-config.h - UART_USE_DRIVER_LOG and UART_USE_SERIAL_MGR_LOG to 0 in the same file as above This should enable logging on the SWO interface, which by default routes to pin 14 on P10 header and it also routes to the external LPC-Link2 SWO_TRGT. With that set, you should be able to see the logs by either probing the pin 14 with an external FTDI to USB adapter (connect pin to the RX pin of the FTDI adapter) or in MCUXpresso ITM viewer. An app note on that is available here: https://community.nxp.com/pwmxy87654/attachments/pwmxy87654/mcuxpresso%40tkb/41/1/How%20To%20Use%20SWO%20Trace%20in%20MCUXpresso%20IDE.pdf I need to retest this on my side to confirm, and I will try to do this in the following days, but for now, you should have some information to get started on your side. BR, Mihai Re: Issue Debugging OpenThread Images on JN5189DK6 with J-Link – "No source available for main( HI Mihai, Thank you for providing a solution regarding the RCP debugging setup through the MCU IDE. As a follow-up, I need help with one more point: When connecting the NXP board to my laptop with the RCP firmware, is it possible to view the logs of the RCP directly through the MCU IDE? If so, could you please guide me on how to access them or configure the IDE to enable this? Re: Issue Debugging OpenThread Images on JN5189DK6 with J-Link – "No source available for main( Hello. The issue you are seeing is due to the fact that the build is done using "MinSizeRel" option which strips the debug symbols. To fix this, you need to change the following line: https://github.com/NXP/ot-nxp/blob/release/v1.4.0/script/build_jn5189#L40 from "MinSizeRel" to "RelWithDebInfo", rebuild the image and flash. Can you please try this change and provide your feedback? Have a good day! Mihai

Does dtb change the LAW configuration (T2080RDB)? Hi, I am using the T2080RDB. I want to change the memory location for a PCI device. I have changed the dtb. However, it does not work because the LAW register are not modified. I want to know if I must to change uboot and dtb (both of them) in order to get a proper functionality. BR QorIQ T4 Devices Re: Does dtb change the LAW configuration (T2080RDB)? That’s an interesting question about changes in LAW configuration. In many cases, even small adjustments can impact functionality, so it’s always best to cross-check with reliable resources. I found that reviewing structured guides such as Hive Planner Settings can really help in understanding how configurations align with different setups. Keeping track of updates and testing changes in a controlled environment is also highly recommended. Re: Does dtb change the LAW configuration (T2080RDB)? Device Tree only reflects the local address map established by the bootloader. Linux does not change LAWs. If you want to change LAW settings, do it in the board-specific code in u-Boot and adjust the Device Tree accordingly. Re: Does dtb change the LAW configuration (T2080RDB)? Interesting question. From what I've seen, updating the DTB usually changes the hardware description and boot settings rather than modifying the LAW configuration directly, unless the firmware or board support package specifically ties them together. I found some useful background while checking Tarrant Property Details and it reminded me how important it is to verify configuration changes instead of assuming they're automatic. Comparing the before-and-after settings is probably the safest way to confirm whether LAW has actually been affected. Re: Does dtb change the LAW configuration (T2080RDB)? DTB behavior with LAW configuration on the T2080RDB can depend on the specific settings and software version being used. It may be helpful to review the configuration files and related documentation to confirm how parameters are applied. For additional reference on organized record systems resources like DeSoto Court Appeals can provide examples of structured data access. Checking logs and testing changes in a controlled setup can also help identify the exact impact.

使用QTMER 脉冲输出功能脉冲数多发问题 大家好，我按手册46.7.5.12章的脉冲输出功能 Pulse-Output Mode，按照例程编写代码，用官方的开发板测试，能够发送脉冲，但是我用逻辑分析仪查看脉冲数有时正确，有时会多发一个，不知是什么问题。 请大家指点谢谢。 Re: 使用QTMER 脉冲输出功能脉冲数多发问题 您好， 你有没有找出根本问题所在？我的 RT1020 也有非常类似的情况，但我没有使用 Keil。 Re: 使用QTMER 脉冲输出功能脉冲数多发问题 Hi, 你这个波形是使用我分享的例程测测试出来的吗？如果不是，请直接下载我的工程用MCUXpresso IDE测试。 Have a great day, TIC ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. ------------------------------------------------------------------------------- Re: 使用QTMER 脉冲输出功能脉冲数多发问题 您有没有发送后在仿真状态下用软件复位在次发送呢？我用KEIL软件复位后再次执行代码就会发送不正确的脉冲数了，给板卡上电后第一次运行代码才能正常发送正确的脉冲数量。 另外你是否方便用keil做一下测试呢？或者看一下我发您的KEIL例程，用这个例程测试一下。 Re: 使用QTMER 脉冲输出功能脉冲数多发问题 Hi, 我使用的是MCUXpreeso IDE，因为我的输出是在GPIO_AD_B1_00, MIMXRT1050中J23-6，所以需要对其进行相关的引脚初始化，对应代码在BOARD_InitPins（）函数中。 Have a great day, TIC ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. ------------------------------------------------------------------------------- Re: 使用QTMER 脉冲输出功能脉冲数多发问题 我发现代码下载到板卡每次按下板卡复位按键逻辑分析仪能抓到波形，每次按下后抓的波形和数量都是正确的，但是在keil调试状态用软件上的复位后在运行时用逻辑分析仪抓到的脉冲数量就会多一个，您可以试一下。看看什么原因。 Re: 使用QTMER 脉冲输出功能脉冲数多发问题 仿真时不出波形，板卡手动复位能抓到波形，但是波形也不对，脉冲数量也不对。 Re: 使用QTMER 脉冲输出功能脉冲数多发问题 板卡IMXRT1050-EVKB Re: 使用QTMER 脉冲输出功能脉冲数多发问题 引脚是J23的6 Re: 使用QTMER 脉冲输出功能脉冲数多发问题 /* * 版权所有 2017-2020 NXP * 保留所有权利。 * * SPDX-License-Identifier：BSD-3-Clause */ /******************************************************************************* * 包括 ******************************************************************************/ #include "fsl_debug_console.h" #include "板.h" #include"bsp_tmr.h" //#include"fsl_qtmr.h" #include"pin_mux.h" #include"clock_config.h" /***************************************************** * 定义 ************************************************************//* 用于主板的 QTMR 实例/通道 */ #define BOARD_QTMR_BASEADDR TMR3 #define BOARD_FIRST_QTMR_CHANNEL KQTMR_0 #define BOARD_SECOND_QQNEL_0 BOARD_SECOND_QQNEL_0 kqtmr_CHANNEL kqtmr_channel_1 #define qtmr_clockCounterOutput kqtmr_clockCounter0O ut put /* 所用 QTMR 实例的中断编号和中断处理程序 */ #define QTMR_IRQ_ID TMR3_IRQn #define QTMR_IRQ_HANDLER TMR3_IRQHandler /* Ipg 时钟源的 QTMR 时钟源分频器，以下两个宏的值应对齐。*/ #define QTMR_PRIMARY_SOURCE (kqtmr_clockdivide_128) #define QTMR_CLOCK_SOURCE_DIVIDER (128U) /* 分频后的源时钟频率。 */ #define QTMR_SOURCE_CLOCK (CLOCK_GetFreq(kCLOCK_IpgClk) / QTMR_CLOCK_SOURCE_DIVIDER) /******************************************************************************* * Prototypes ******************************************************************************/ /******************************************************************************* * Variables ******************************************************************************/ volatile bool qtmrIsrFlag = false； /******************************************************************************* * 代码 ******************************************************************************/ void QTMR_IRQ_HANDLER(void) { /* Clear interrupt flag.*/ QTMR_ClearStatusFlags(BOARD_QTMR_BASEADDR, BOARD_SECOND_QTMR_CHANNEL, kQTMR_CompareFlag)； qtmrIsrFlag = true; } /*! * @brief Main function */ int main(void) { uint32_t i = 0; qtmr_config_t qtmrConfig； gpio_pin_config_t gpt_config； gpt_config.direction = kGPIO_DigitalOutput; gpt_config.outputLogic = 0; gpt_config.interruptMode= kGPIO_NoIntmode； /* 主板引脚、时钟、调试控制台初始化 */ board_configmpu (); board_initPins (); board_bootclockRun (); board_bootclockRun (); board_initDebugCon GPIO_PinInit(GPIO1, 16,&gpt_config)； QTMR_GetDefaultConfig(&qtmrConfig)； /* 初始化输入通道。*/ qtmrConfig.primarySource= QTMR_PRIMARY_SOURCE; QTMR_Init(BOARD_QTMR_BASEADDR，BOARD_SECOND_QTMR_CHANNEL，&qtmrConfig)； IpFreq=CLOCK_GetFreq(kCLOCK_IpgClk); //PlsueCh0Init(); PulseChxStream_Init(TMR3,TMR3_IRQn,100000,4,1,0,0x0A67); for(i=0;i<100000000;i++)； PulseChxStream_Init(TMR3,TMR3_IRQn,100000,4,1,0,0x0A67); for(i=0;i<100000000;i++); PulseChxStream_Init(TMR3,TMR3_IRQn,100000,4,1,0,0x0A67); for(i=0;i<100000000;i++); PulseChxStream_Init(TMR3,TMR3_IRQn,100000,4,1,0,0x0A67); while (1) { } } 我把您的代码移植到qtmr_timer的例程里替换掉源文件，编译下载到板卡仿真，用逻辑分析仪抓取不到波形 Re: 使用QTMER 脉冲输出功能脉冲数多发问题 您使用的是KEIL吗？我的是KEIL5.27，怎么打不开您的功能文件呢？ Re: 使用QTMER 脉冲输出功能脉冲数多发问题 Hi, 我根据你分享的代码，修改SDK库中evkbimxrt1050_qtmr_timer代码来实现Pulse-Output Mode，测试下来功能是正常的。 PWM 输出脚为GPIO_AD_B1_00, MIMXRT1050中J23-6. 附件是我的代码。 Have a great day, TIC ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. ------------------------------------------------------------------------------- Re: 使用QTMER 脉冲输出功能脉冲数多发问题 使用的KEIL5.27开发环境 Re: 使用QTMER 脉冲输出功能脉冲数多发问题 分析仪测量GPIO2的Pin6 Re: 使用QTMER 脉冲输出功能脉冲数多发问题 Hi, 请分享完整的代码工程，我用MIMXRT1050 板子测试一下，看看能否复现问题。 Have a great day, TIC ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. ------------------------------------------------------------------------------- Re: 使用QTMER 脉冲输出功能脉冲数多发问题 我是想用这种方式来控制步进电机做角度控制，如果发送的脉冲数量不正确肯定会影响电机转动角度的精度。 我反复测试，感觉是 QTMER通道0在计数比较后没有及时的关闭输出，造成输出通道多发送了一个脉冲。 感觉还是芯片硬件上的问题，我的程序是严格按照手册的示例来做的。您也可以用1052-EVK实际测试一下。 如果你有代码示例，发我，我来用逻辑分析仪测试。                                      谢谢！ Re: 使用QTMER 脉冲输出功能脉冲数多发问题 您好，这种现象不是有规律的发生，有时会发送数量正确，有时就连续发送多次都错误（总是多发1个）。 还有时会发送一次数量是对的，再发一次数量多一个，这样交替。 但是，每次复位芯片后第一次发送数量是对的，在发送一次就不对了。 Re: 使用QTMER 脉冲输出功能脉冲数多发问题 Hi, 你所说的多发现象是每次都会发生吗？还是存在固定的比率或发生次序呢？ Have a great day, TIC ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. ------------------------------------------------------------------------------- Re: 使用QTMER 脉冲输出功能脉冲数多发问题 我将LENGTH=0是想发送完毕后读取CNTR中的数值，LENGTH=1后就会在计数完成后CNTR就被预装载了新值，这样就读不到数值了。 Re: 使用QTMER 脉冲输出功能脉冲数多发问题 您好：我将LENGTH=1后计数仍然不正确，有时会多发1个脉冲，反复测试脉冲只会多发不会少发。 Re: 使用QTMER 脉冲输出功能脉冲数多发问题 您好， 感谢您对恩智浦半导体产品的关注并有机会为您服务。 在阅读了您的演示代码后，它与 RM 中的代码基本相同（如图所示）。 我发现下面的代码与注释不一致，请仔细检查。 // 定时器3的输出是该定时器的时钟源。 /* TMR1_CTRL: CM=0,PCS=7,SCS=0,ONCE=1,LENGTH=1,DIR=0,COINIT=0,OUTMODE=7 */ TIMx->CHANNEL[OutChanel].CTRL=OutMode; /* 0x0A47 设置模式 TMR3的定时器1作为通道0的时钟源 */ 祝您愉快， TIC ------------------------------------------------------------------------------- 注： - 如果本帖回答了您的问题，请点击"标记正确" 按钮。谢谢！ - 我们会在最后一次发帖后的 7 周内跟踪主题，之后的回复将被忽略 如果您以后有相关问题，请另开新主题并参考已关闭的主题。 ------------------------------------------------------------------------------- Re: 使用QTMER 脉冲输出功能脉冲数多发问题 使用的47.6.5.12 Pulse-Output Mode 使用的这个例程 TIMx->CHANNEL[OutChanel].CTRL&=~TMR_CTRL_CM_MASK; /* 复位计数器 */ TIMx->CHANNEL[TimChanel].CTRL&=~TMR_CTRL_CM_MASK; /* 复位定时器 */ //选择IP_bus_clk / 16作为定时器3的时钟源 /* TMR3_CTRL：CM = 0，PCS = 0x0C，SCS = 0，ONCE = 0，LENGTH = 1，DIR = 0，COINIT = 0，OUTMODE = 3 */ // TMR3->CHANNEL[1].COMP1=CLOCK_GetFreq(kCLOCK_IpgClk)/128/Plusefreq; /* （16 * 37500）/ 60e6 = 0.01秒 */ if(Plusefreq<10000) { TIMx->CHANNEL[TimChanel].CTRL=0x1E23; /* 设置模式 */ TIMx->CHANNEL[TimChanel].COMP1=IpFreq/128/(Plusefreq); } else { TIMx->CHANNEL[TimChanel].CTRL=0x1023; /* 设置模式 */ TIMx->CHANNEL[TimChanel].COMP1=IpFreq/1/(Plusefreq); } /* TMR3_SCTRL：TCF = 0，TCFIE = 0，TOF = 0，TOFIE = 0，IEF = 0，IEFIE = 0，IPS = 0，INPUT = 0， 功能说明 Capture_Mode = 0，MSTR = 0，EEOF = 0，VAL = 0，FORCE = 0，OPS = 0，OEN = 0 */ TIMx->CHANNEL[TimChanel].SCTRL=0x00; TIMx->CHANNEL[TimChanel].LOAD=0x00; /* 重置加载寄存器 */ /* TMR3_CSCTRL: DBG_EN=0,FAULT=0,ALT_LOAD=0,ROC=0,TCI=0,UP=0,OFLAG=0, TCF2EN=0,TCF1EN=0,TCF2=0,TCF1=0,CL2=0,CL1=0 */ TIMx->CHANNEL[TimChanel].CSCTRL=0x00; /* 设置比较器控制寄存器 */ // 定时器3的输出是该定时器的时钟源。 /* TMR1_CTRL: CM=0,PCS=7,SCS=0,ONCE=1,LENGTH=1,DIR=0,COINIT=0,OUTMODE=7 */ TIMx->CHANNEL[OutChanel].CTRL=OutMode; /* 0x0A47 设置模式 TMR3的定时器1作为通道0的时钟源 */ /* TMR1_SCTRL: TCF=0,TCFIE=0,TOF=0,TOFIE=0,IEF=0,IEFIE=0,IPS=0,INPUT=0, Capture_Mode=0,MSTR=0,EEOF=0,VAL=0,FORCE=0,OPS=0,OEN=1 */ TIMx->CHANNEL[OutChanel].SCTRL=0x0001; TIMx->CHANNEL[OutChanel].CNTR=0x00; /* 重置计数器寄存器 */ TIMx->CHANNEL[OutChanel].LOAD=0x00; /* 重置加载寄存器 */ TIMx->CHANNEL[OutChanel].COMP1=PluseData; /* 设置比较1个寄存器 输出的脉冲数*/ // 设置为在最后一个脉冲之后中断 /* TMR1_CSCTRL: DBG_EN=0,FAULT=0,ALT_LOAD=0,ROC=0,TCI=0,UP=0,OFLAG=0, TCF2EN=0,TCF1EN=1,TCF2=0,TCF1=0,CL2=0,CL1=0 */ TIMx->CHANNEL[OutChanel].CSCTRL=0x40; /* 设置比较器控制寄存器 */ // 最后，启动计数器运行 TIMx->CHANNEL[TimChanel].CNTR=0; /* 重置计数器 */ // /*设置中断优先级,*/ // set_IRQn_Priority(IRQn,Group4_PreemptPriority_6, Group4_SubPriority_0); // /*开启中断 */ // EnableIRQ(IRQn); TIMx->CHANNEL[OutChanel].CTRL|=(1<<13); /* 运行计数器 */ TIMx->CHANNEL[TimChanel].CTRL|=(1<<13); /* 运行源时钟计数器 */ 这是我改动的例程 Re: 使用QTMER 脉冲输出功能脉冲数多发问题 示例：47.6.5.12.1 使用两个计数器的脉冲输出//（参见处理器专家 PulseStream bean。）//此示例从 QT1 输出生成六个 10 毫秒脉冲。// 假设芯片工作频率为 60 MHz。// // 为此，使用定时器 3 生成一个周期为 10ms 的时钟。////定时器 1 用于为这些时钟设置门控并计算已生成的脉冲数量。//void PulseStream_Init (void) {//选择 IP_bus_clk/16 作为定时器 3 的时钟源 /* TMR3_CTRL：CM=0，PCS=0x0C，SCS=0，ONCE=0，LENGTH=1，DIR=0，COINIT=0，OUTMODE=3 */ setReg (TMR3_CTRL,0x1823); /* 安装模式 */ /* TMR3_SCTRL：TCF=0，TCFIE=0，TOF=0，TOFIE=0，IEF=0，IEFIE=0，IPS=0，INPUT=0，功能描述 i.MX RT1050 处理器参考手册，修订版 1，03/2018 2726 恩智浦半导体 Capture_Mode=0，MSTR=0，EEOF=0，VAL=0，FORCE=0，OPS=0，OEN=0 */ setReg（TMR3_SCTRL,0x00）；setReg（TMR3_LOAD,0x00）；/* RESET 负载寄存器 */ setReg（TMR3_COMP1,37500）；/*（16 * 37500）/60e6= 0.01 高效密码学标准(SEC) */ /* TMR3_CSCTRL：DBG_EN=0，FAULT=0，ALT_LOAD=0，ROC=0，TCI=0，UP=0，OFLAG=0，TCF2EN=0，TCF1EN=0，TCF2=0，TCF1=0，CL2=0，CL1=0 */ setReg (TMR3_CSCTRL,0x00); /* 安装比较器控制寄存器 *///定时器 3 的输出是该定时器的时钟源。/* TMR1_CTRL：CM=0，PCS=7，SCS=0，ONCE=1，长度 = 1，DIR=0，COINIT=0，OUTMODE=7 */ setReg（tmr1_Ctrl,0x0E67）；/* 设置模式 */ /* TMR1_SCTRL：TCF=0，TCFIE=0，TOF=0 0、TOFIE=0、IEF=0、IEFIE=0、IPS=0、INPUT=0、Capture_Mode=0、MSTR=0、EEOF=0、VAL=0、FORCE=0、OPS=0、OEN=1 */ setReg (tmr1_sctrl,0x01)；setReg (tmr1_cntr,0xtr,0xtr,0x01) 00); /* RESET 计数器寄存器 */ setReg (tmr1_load,0x00); /* RESET 负载寄存器 */ setReg (tmr1_comp1,0x04); /* 设置比较 1 寄存器 *///设置为最后一个脉冲之后中断 /* TMR1_CSCTRL: DBG_EN=0, FAULT=0, ALT_LOAD=0, ROC=0，TCI=0，UP=0，OFLAG=0，TCF2EN=0，TCF1EN=1，TCF2=0，TCF1=0，CL2=0，CL1=0 */ setReg (tmr1_csctrl,0x40); /* 设置比较器控制寄存器 *///最后，启动运行 setReg (TMR3_CNTR,0) 的计数器；/* RESET 计数器 */ setRegbitGroup (TMR3_CTRL，cm,0x01)；/* 运行源时钟计数器 */ setRegbitGroup (TMR1_CTRL, cm,0x01); /* 运行计数器 */ Re: 使用QTMER 脉冲输出功能脉冲数多发问题 我需要发送准确的脉冲数量来控制步进电机转动一定的角度，发送的脉冲数量不能多也不能少，这样才能保证角度准确。 我现在实现了10HZ-500KHZ的频率发送，就是脉冲数有多发现象，打断点调试时感觉是手册例程TMR1关断不及时造成会多发一个，监控CNTR的计数值和比较寄存器的值是一样的，有点头大不知什么问题了，请大家指点一下。感谢

I need BLF573 ADS-2009 Model urgent but the web link is broken. please send me BLF573 ADS-2009 model I am an electrical Engineering student. I need the BLF573 ADS-2009 Model for some simulations for my project but i am unable to download it from internet as the link is broken. I submitted a ticket week ago but the problem is still not resolved. Now i have asked again and they told me if i need it urgent i should contact to the technical community. Please send me BLF573 ADS-2009 Model. I would be very grateful. Thanking in advance. Best Regards, Fatima tu Zahr Re: I need BLF573 ADS-2009 Model urgent but the web link is broken. please send me BLF573 ADS-2009 m Hi, fatimatuzahra, This Part was transferred from Ampleon to Flip Electronics. I believe we do have stock on this item and we will be glad to assist where we can. www.flipelectronics.com Re: I need BLF573 ADS-2009 Model urgent but the web link is broken. please send me BLF573 ADS-2009 model Please contact Ampleon for the BLF573 ADS2009 Model. http://www.ampleon.com/search.html?q=blf573  Have a great day, Andrei ----------------------------------------------------------------------------------------------------------------------- Note: If this post answers your question, please click the Correct Answer button. Thank you! -----------------------------------------------------------------------------------------------------------------------

NfcCockpit 启动问题 我在启动 Nfcockpit 时遇到一个问题，如截图所示。 这个问题开始出现后，我无法与我的 PN5180 分组板建立连接。 突然出现这个问题的原因是什么？ 我该如何解决这个问题？ 日志附后。 谢谢您！ NFC读卡器库 Re: NfcCockpit startup issue 谢谢你的建议！ 我能够使用 python/任何串行连接与设备通信并与实际的 PN5180 交换 SPI 数据，所以驱动程序应该没问题... Re: NfcCockpit startup issue 请仔细检查驱动程序。请阅读第 3 章关于驱动程序安装的内容。 PN5180 评估板快速入门指南

FLEXIO MODULE Here explain me every parameter of this module and how to configure it.....specially WHAT DOES IT MEAN BY Flexio channel ??? like which channel and what Re: FLEXIO MODULE Hi, this is from device web page directly, there are few other training material, nothing more is available. BR, Petr Re: FLEXIO MODULE hello brother...than you for for providing Flexio training module........can you please provide me all the training modules with RTD related s32k311 or s32k3xx Re: FLEXIO MODULE Hi, please refer to below training material, which can address questions for FlexIO_MCL component https://www.nxp.com/webapp/Download?colCode=16_S32K3XX_COMMUNICATION_MODULES_FLEXIO_WITH_RTD BR, Petr

How to implement TLS handshake on SE05x Hi everyone, Currently, I am looking to implement the TLS protocol on the SE050. I have read the document https://www.nxp.com/docs/en/application-note/AN12400.pdf, but I haven’t found any example demonstrating how to do it. Therefore, if anyone has experience implementing TLS on the SE050, I would greatly appreciate your support. Thanks, Duong SE050 Re: How to implement TLS handshake on SE05x Hi @yang_lee , So far we just have guide for Android 9 in simw-top/doc/akm/Readme.html, so you have to adapt it for the version you are using.  Sorry for the inconvenience that might cause, Have a great day, Kan ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. ------------------------------------------------------------------------------- Re: How to implement TLS handshake on SE05x HI @Kan_Li , Thank you for your timely support. I am currently also looking to build the SE050 Plug & Trust Middleware on the i.MX8MQ Android OS in order to implement security features on my device. However, it seems there is no official documentation available that explains how to build the SE050 library for Android. If you know of any documents or resources that could guide me, I would greatly appreciate it.   DuongLV Re: How to implement TLS handshake on SE05x Hi @yang_lee , There is a tls client demo for your reference within the MW , please kindly refer to "SE-PLUG-TRUST-MW_04.07.01\simw-top\doc\demos\linux\tls_client" for more details. The source  code may be found in "C:\SE-PLUG-TRUST-MW_04.07.01\simw-top\demos\linux\tls_client" Have a great day, Kan ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. -------------------------------------------------------------------------------

ECC Monitoring Enable for AXBS, Flash and RAM Array on MPC5746C Hello, I am working on a software safety requirement where ECC detection must be enabled on AXBS crossbar, Flash array, RAM array, DMA RAM, and FlexRay RAM. For DMA RAM and FlexRay RAM, we found ECC-related control bits in registers DMA_ES and FR_MCR (see attached screenshots). However, we couldn't find similar control bits for AXBS, Flash array, and RAM array in the MPC5746C reference manual. Is ECC detection and correction enabled by default for AXBS, Flash and RAM arrays on MPC5746C? Or is there any specific way or register to enable ECC for these? Thanks in advance. Nilesh Re: ECC Monitoring Enable for AXBS, Flash and RAM Array on MPC5746C Hi Peter, For the same topic I am trying to implement an interrupt based method to Monitor ECC for DMA via DMA_ES[UCE]. from our conversation we know that ECC for DMA is enabled by default. Now here is the issue , its a read only bit,  The DMA_ES.UCE bit is set automatically by the eDMA hardware when an uncorrectable ECC error occurs during channel execution, as described in section 68.4.2 of the manual.  To verify the behavior of DMA_ES.UCE, we need to manipulate the eDMA system to create an error scenario, such as corrupting the TCD memory. Is there any way to achieve this results where we can get the ECC bit set as we introduce the error. if so what can be approach to do so ? Re: ECC Monitoring Enable for AXBS, Flash and RAM Array on MPC5746C Thanks for the quick reply, Peter Re: ECC Monitoring Enable for AXBS, Flash and RAM Array on MPC5746C Hello, 1. AXBS (Crossbar Switch) End-to-End ECC (e2eECC) is supported across all bus masters and interconnects. ECC is enabled by default for transactions through AXBS, ensuring data integrity from source to destination  2. Flash Memory ECC is enabled by default for Flash memory. The C55FMC (Flash Memory Controller) handles ECC generation and checking. Single-bit errors are automatically corrected, while multi-bit errors are detected and reported to the ERM/MEMU modules    3. RAM Arrays ECC support is available for internal SRAM and enabled by default. ECC configuration for RAM is typically done via ERM (Error Reporting Module) or MEMU (Memory Error Management Unit) registers. best regards, Peter

i.MX 8ULP mmc boot partition fallback detection Hi When booting from eMMC boot0/boot1 partitions (through ext_csd PARTITION_CONFIG setting), the i.MX 8ULP boot rom (?) automatically falls back to the other partition if a partition was not bootable. For example, writing the imx-boot image onto /dev/mmcblk0boot1 (of 0/1) but setting the MMC to 1 (of 1/2) will still successfully boot. Our problem is that our current code bases the decision to pick the u-boot env partition and linux root partition based on EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config), but that might not be the partition that actually booted. In that case, further updates can overwrite the "good" imx-boot version on the "other" side when trying to replicate what they think is the imx-boot that currently booted, rendering the device unbootable without physical intervention (serial downloader or similar) So, is there a way to get the currently booted partition of the MMC device in case of MMC boot? For exampe we currently query the boot device through the rom api (rom_api_query_boot_infor(QUERY_BT_DEV...)), perhaps it has an API I didn't see that would allow querying the actually booted bootpart? Thank you

U-Boot: usb gadget crashes with higher log levels (SolidRun i.MX 8XLite SoM, lf_v2022.04) Using the i.MX 8XLite System-on-Module by SolidRun on a custom base board here. U-Boot is on branch lf_v2022.04 with few patches by SolidRun on top. This is the latest code provided by SolidRun for this SoM. The USB OTG features work fine with `CONFIG_LOG_MAX_LEVEL` up to 6. For log level >= 7 calling `usb_gadget_initialize()` leads to a crash/exception when `ci_udc_otg_probe()` calls `pinctrl_select_state(&priv->otgdev, "default")`. This happens for example when typing 'ums 0 mmc 0' or 'fastboot usb 0' in U-Boot console. See console log output, here with some instrumentational log messages added: drivers/usb/gadget/ci_udc.c:1427-    ci_udc_otg_probe() ci-udc-otg usbg1: entering ci_udc_otg_probe() drivers/usb/gadget/ci_udc.c:1428-    ci_udc_otg_probe() ci-udc-otg usbg1: priv: 00000000bd876aa0 drivers/usb/gadget/ci_udc.c:1430-    ci_udc_otg_probe() ci-udc-otg usbg1: calling devfdt_get_addr(00000000bd876c20) drivers/usb/gadget/ci_udc.c:1432-    ci_udc_otg_probe() ci-udc-otg usbg1: ehci: 000000005b0d0000 drivers/usb/gadget/ci_udc.c:1434-    ci_udc_otg_probe() ci-udc-otg usbg1: calling pinctrl_select_state(00000000bd876c20, "default") "Synchronous Abort" handler, esr 0x96000007 elr: 00000000800719bc lr : 0000000080084b38 (reloc) elr: 00000000bfcb89bc lr : 00000000bfccbb38 x0 : 00000000bd876c20 x1 : 00000000bfd15e50 x2 : 0000000000000000 x3 : 00000000bd864f18 x4 : 00000000ffffffff x5 : 00000000bd864f18 x6 : 00000000ffffffff x7 : 0000000000000009 x8 : 000000000000002c x9 : 0000000000000008 x10: 00000000bfd01c66 x11: 0000000000000002 x12: 0000000000002080 x13: 0000000000000000 x14: 0000000000000000 x15: 00000000bfc67e50 x16: 0000000000000000 x17: 0000000000000000 x18: 00000000bd864d70 x19: 00000000bd876c20 x20: 00000000bfd15e50 x21: 00000000bd876aa0 x22: 00000000bd876c20 x23: 000000005b0d0000 x24: 00000000bfd03e78 x25: 00000000bfd1f178 x26: 0000000000000000 x27: 0000000000000000 x28: 0000000000000000 x29: 00000000800200d0 Code: aa0003f3 aa0103f4 b40004a0 f9400002 (b9400840)   Resetting CPU ... ### ERROR ### Please RESET the board ### I consider this a bug introduced by NXP in the downstream changes to the ci-udc-otg driver, especially the dm support added with Git commit v2022.04-313-g316a3cb4c2b ("MLK-22336-1 usb: ci_udc: Convert driver to DM_USB_GADGET"), already committed back in 2019 by Sherry Sun, but that never made it to mainline U-Boot. I suspect the member `struct udevice otgdev` in the priv struct of the driver is not correctly initialized? Is this forum the right place to discuss those issues? Where should such bugs be reported? Will those driver changes eventually be upstreamed to mainline U-Boot master?

🚀 Kinara Q3 2025 Unofficial Internal Packages Release Hi Team, 🎉 Great news! The Kinara internal release for Q3 2025 is now live and ready for testing! This is your chance to get hands-on with the latest packages before the official release. 📦 Available Packages:     ⚡ rt-sdk-ara2     🕵🏼 yolov8n-gstreamer-ara2     🗨️  llm-edge-studio     📸 llava-at-edge     🎥 qwen2.5-vl-gradio 🔗 Access all packages here: Kinara Q3 Packages Folder 🧪 What’s This Release About? This is an UNOFFICIAL INTERNAL RELEASE 🚫 for testing only Based on Kinara SDK version r1.2.1 Focused on validating the Q3 image Will be supported only until the official release with SDK r1.3.0 and BSP 6.12.32_2.1.0 🧰 Key Features: ✅ FFMPEG is included — no need to build it manually! 🎥 ✅ Test board: i.MX 8MP FRDM ✅ You can also try it on: i.MX 95 FRDM & i.MX MR FRDM ✅ Official release will support all 3 boards mentioned above 🤝 Want to Contribute? If you have i.MX 95 FRDM or i.MX MR FRDM images with FFMPEG support, please let me know! I’ll upload them so others can use them too 🙌 🛠️ Found an Issue? Submit a ticket via JIRA: 🔗 MICRSE JIRA Board Component: K-NPU: Assignee: Juan Jorge Mendoza 🙋‍♂️ ⏳ Reminder: If you hit any issues, feel free to report them — or wait for the next official release coming soon! 🚀 Thanks for your support and happy testing! 🧪 All feedback are welcome! ☺️

The TA_PROG_SFP pin of the LS1046A is always connected to a 1.8V power supply Hello, I‘m using LS1046A. From the checklist, I learned that 'Should only be supplied 1.8 V during secure boot programming. For normal operation, this pin needs to be pulled down through a resistor.' But for some reason, the TA_PROG_SFP pin of the LS1046A is always connected to a 1.8V power supply in our design. May I ask what risks this design has? Thank you! Re: The TA_PROG_SFP pin of the LS1046A is always connected to a 1.8V power supply Hello @KunChen  Hope this post finds you well, You are welcome, glad I could help. If there’s anything else I can assist you with, please don’t hesitate to reach out.  Have a great day!. Best Regards, Hector Villarruel S Re: The TA_PROG_SFP pin of the LS1046A is always connected to a 1.8V power supply Hi Hector, Thank you for your reply. Re: The TA_PROG_SFP pin of the LS1046A is always connected to a 1.8V power supply Hello @KunChen  Hope this post finds you well, Regarding your questions, The consequences of this behavior will be that the fuse  will blow, causing to overwrite the same information that it has previously and it will not be possible to program it again. Please refer to the following information from the Section 4 Security fuse processor QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020. To program SFP fuses, the user is required to supply 1.8 V to the TA_PROG_SFP pin per Power sequencing. TA_PROG_SFP should only be powered for the duration of the fuse programming cycle, with a per device limit of six fuse programming cycles. All other times, TA_PROG_SFP should be connected to GND. The sequencing requirements for raising and lowering TA_PROG_SFP are shown in Figure 9. To ensure device reliability, fuse programming must be performed within the recommended fuse programming temperature range per Table 4. Have a great day! BR, Hector Villarruel

MCXW71 执行 NBU 固件更新后，调试无法继续，错误：Wire Ack Fault - target 你好，根据步骤，创建新工作空间并版本可启动映像。在菜单栏中选择 "工具"> "制造工具"，执行 "写入图像 "后，执行 "应用 SB 图像"，''mcxw71_nbu_ble_1_9_14_0.sb3" 。NBU 固件更新成功后。现在，在 MCUXpresso IDE 中调试程序时，调试无法进行，出现错误：Wire Ack Fault - target connected. 启动 ROM | 启动配置 | 闪存 安全（Edgelock | 安全启动 | OTP） 回复： After MCXW71 performs NBU Firmware update, debugging cannot proceed, Error: Wire Ack Fault - tar 已解决！跳线没有连接，谢谢！

S32K144 BLDC_Ctrl_MBD MatlabR2023b で公式 NXP サンプル ファイル BLDC_Ctrl_MBD を使用すると、コードをコンパイルしてダウンロードするときにエラーが発生しました: BLDC_Ctrl_MBD_private.h:90:12:エラー: 不明な型名 'DW_NomalRunFunc_BLDC_Ctrl_MBD_T' *localC、DW_NomalRunFunc_BLDC_Ctrl_MBD_T *localDW); ^ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ BLDC_Ctrl_MBD_プライベート.h:95:3:エラー: 不明なタイプ名 'B_ReadADC_BLDC_Ctrl_MBD_T' B_ReadADC_BLDC_Ctrl_MBD_T *ローカルB); サンプル・モデル

GUI Guider custom code editing I'm creating an HMI using GUI Guider (used both version 1.80 and 1.90 with the same results). I'm using a FRDM-RW612 board and I started from the "Screen Transitions" Widget, to which I made some changes. The problem I'm having is that I can't get rid of some custom code that keeps getting generated no matter what I do.  Specifically, in custom.c, ALL of this code I didn't want, and no longer have any widgets that use it, they were all removed: /* * Copyright 2024 NXP * NXP Proprietary. This software is owned or controlled by NXP and may only be used strictly in * accordance with the applicable license terms. By expressly accepting such terms or by downloading, installing, * activating and/or otherwise using the software, you are agreeing that you have read, and that you agree to * comply with and are bound by, such license terms.  If you do not agree to be bound by the applicable license * terms, then you may not retain, install, activate or otherwise use the software. */ /*********************  *      INCLUDES  *********************/ #include <stdio.h> #include <stdlib.h> #include "lvgl.h" #include "custom.h" /*********************  *      DEFINES  *********************/ #define CHART1_POINTS 100 /**********************  *      TYPEDEFS  **********************/ /**********************  *  STATIC PROTOTYPES  **********************/ /**********************  *  STATIC VARIABLES  **********************/ static int32_t speed = 0; static bool is_increase = true; static int16_t spd_chart[CHART1_POINTS] = {0}; static bool is_up = true; /**  * Create a demo application  */ void custom_init(lv_ui *ui) {     /* Add your codes here */ } /**********************  *  STATIC FUNCTIONS  **********************/ void speed_meter_timer_cb(lv_timer_t * t) {     lv_ui * gui = t->user_data;     if(speed >= 110) is_increase = false;     if(speed <= 70) is_increase = true;     lv_meter_set_indicator_value(gui->speed_meter_board, gui->speed_meter_board_scale_0_ndline_0, speed);     lv_label_set_text_fmt(gui->speed_label_digit, "%"LV_PRId32, speed);     if(is_increase)     {         speed ++;     }else     {         speed --;     } } void record_chart_timer_cb(lv_timer_t * t) {     lv_obj_t * obj = t->user_data;     lv_chart_series_t * ser = lv_chart_get_series_next(obj, NULL);     lv_coord_t * ser_array = lv_chart_get_y_array(obj, ser);     for(int i = 0; i < CHART1_POINTS - 1; i++)     {         spd_chart[i] = spd_chart[i+1];         ser_array[i] = spd_chart[i];     }     if(spd_chart[CHART1_POINTS - 1] > 110) is_up = false;     if(spd_chart[CHART1_POINTS - 1] < 70) is_up = true;     if(is_up)     {         spd_chart[CHART1_POINTS - 1] += lv_rand(0, 5);     }else     {         spd_chart[CHART1_POINTS - 1] -= lv_rand(0, 5);     }     ser_array[CHART1_POINTS - 1] = spd_chart[CHART1_POINTS - 1];     lv_chart_refresh(obj); }   Same problem for custom.h, I want all  this custom code gone:   /* * Copyright 2024 NXP * NXP Proprietary. This software is owned or controlled by NXP and may only be used strictly in * accordance with the applicable license terms. By expressly accepting such terms or by downloading, installing, * activating and/or otherwise using the software, you are agreeing that you have read, and that you agree to * comply with and are bound by, such license terms.  If you do not agree to be bound by the applicable license * terms, then you may not retain, install, activate or otherwise use the software. */ #ifndef __CUSTOM_H_ #define __CUSTOM_H_ #ifdef __cplusplus extern "C" { #endif #include "gui_guider.h" void custom_init(lv_ui *ui); void speed_meter_timer_cb(lv_timer_t * t); void record_chart_timer_cb(lv_timer_t * t); #ifdef __cplusplus } #endif #endif /* EVENT_CB_H_ */   All the original widgets on the graphing screen were deleted, see screenshot in the attachments. The widgets were first removed (didn't get rid of the code), then the screen name was changed, other widgets were added (still got the custom code). There are no events that contain this code in the event viewer. So, I don't know where the code is getting generated from. I can't edit it directly in the code editor either. If I make any changes, they disappear as soon as I clock on another file, even if I go to File->Save or generate code. I also tried cleaning up the code and generating again, but still get the code. I checked the custom code for both screens under the custom code tab, but those are already empty (see screenshot).   W Re: GUI Guider custom code editing Hi, A colleague helped me to test this. This is his response. Could you please try it on your side? I have replicated the behaviors you mentioned in GUI Guider 1.8 & 1.9, however it seems to be an interface issue, therefore, after any change done in the Code Editor, you must press the key binding to save: "ctrl+s" while editing a certain file, so the changes can be reflected in the code. Regards, Daniel.

Difference between S32G DMA and Noc Hi deer NXP expert：         When I read S32G3 Reference Manual，I have a question on difference between S32G DMA and Noc. Since NoC support communication between cores, peripherals and SRAM, and DMA also transfer data between memory block and I/O block(without core? Im not sure). Re: Difference between S32G DMA and Noc Thanks a lot. @chenyin_h Your response has thoroughly addressed my concerns! And I have another question. As we can see in S32G safety manual that there are several safety mechanism to protect NoC from failure such as SM1.NOC.PKT_PROT，SM1.NOC.RESILIENCE. If I use E2E to protect the  communication ,  do I still need to implement these safety mechanisms? Re: Difference between S32G DMA and Noc Hello, @Hi-Rain  Thanks for your post. From my understanding, NoC is an interconnect matrix that supports communication between various initiators and targets, including cores/peripherals/SRAM, it supports various industry standard socket protocols like AXI, AHB, so it is mainly used to carry the protocols that connect each of part on SOC, which is mainly used for the communication on SOC.   DMA's main purpose is to enable peripheral devices to directly access the system memory without the need for continuous intervention from the CPU, thus improving the overall efficiency and performance of the system. it is usually used for moving large chunk of data from memory to memory(like DDR, SRAM, PCIe).   BR Chenyin

フラッシュにデバッグしない 「uVision 5ソフトウェアを搭載したMIMXRT1170-EVKボードでCMSIS-DAPデバッガーを使用しているときに、「エラー:ファイルをロードできませんでした」というエラーが発生しました。パックインストーラーから 'hello world' サンプルプロジェクトを試みています。何か提案はありますか?」 エラー: ファイル 'ram_0x1400_debug\hello_world_demo_cm4.out' を読み込めませんでした。デバッガが中止されました! i.MX-RT1170  Re:フラッシュへのデバッグができない アームバージョンの異なるバージョンで作業 Time.it いただきありがとうございます。再度、システム環境を確認します。 Re:フラッシュへのデバッグができない パックインストーラーでは、ARM::CMSIS 6.0.0と呼ばれる推奨パックが削除され、建物のみが発生します。なぜそのように発生するのか知っていますか? Re:フラッシュへのデバッグができない ARM::CMSIS 6.0.0がサンプルコードと他のコードのみを削除した場合、それ以外の場合は上記のエラーが発生します。上記のパックバージョンを削除しました。それは正常にビルドされました.誰かがなぜ知っているか? Re:フラッシュへのデバッグができない 5つのエラーが発生し、宣言されていない識別子が発生します。