S32N7 FSS FW 1.14.0 build error Dera suport, I generated the FSS FW 1.14.0 from Tresos  and executed make build from  C:\NXP\S32N_FSS_FW_R21-11_1.14.0\eclipse\plugins\Fss_Firmware_TS_T31D62M114I0R0\examples\EBT\Firmware_S32N79_FSS> towards teh end of the process during linking I get below error c:/nxp/s32ds.3.6.5/s32ds/build_tools/gcc_v11.4/gcc-11.4-arm32-eabi/bin/../lib/gcc/arm-none-eabi/11.4.0/../../../../arm-none-eabi/bin/real-ld.exe: out/Os_cfg_c.o:(.osrodata+0x7f0): undefined reference to `FuncTASK_DDR1_DATA_INIT_STATUS' collect2.exe: error: ld returned 1 exit status make: *** [Makefile:635: main.elf] Error 1  I rechecked the FSS FW delivery and found references to function FuncTASK_DDR1_DATA_INIT_STATUS but there is no implementation in the delivery.  Also FSS User Manual does not mention this function. Any hint on how to deal with the error ? I used the  FSS FW 1.14.0 out of the box - no adjustments no changes. Best REgards, Viktor    FSS_FW Priority: HIGH Source: Direct Customer Source: NXP Internal Re: S32N7 FSS FW 1.14.0 build error Hi @viktorfellinger  FuncTASK_DDR1_DATA_INIT_STATUS will be generated in Fss_Ddr_Cfg.c of Fss_Firmware when "Os Task Reference" node is enabled. For Fss Firmware example of 1.14.0 release. We already enabled them with Os configuration together. So please re-check your Fss_Frimware.xdm configuration.

Clarification on Pin Multiplexing Differences Between CM7 and CM4 on i.MX RT1176 Hello everyone, I am working with the i.MX RT1176 using MCUXpresso SDK and developing applications for both the CM7 (primary) and CM4 (secondary) cores. I have an application that runs correctly on the CM7 core, and I replicated the same application logic on the CM4 core. The CM4 project builds successfully without errors. However, I noticed a significant difference in the generated pin_mux.c files for the two cores. In the CM7 project, the pin_mux.c file configures multiple peripherals such as ENET, LPUART1 and LPUART2, CAN, I2C, and several GPIOs. In contrast, the CM4 pin_mux.c file only configures LPUART1 and a limited number of GPIO pins. Peripherals like LPUART2, ENET, CAN, and I2C are completely absent in the CM4 pin configuration. Is this difference expected on the RT1176 due to core ownership, XRDC restrictions, or the way MCUXpresso generates projects for dual-core devices? What is the recommended approach when moving functionality from CM7 to CM4? Should pin multiplexing always be initialized on the CM7 core only, or is it valid for CM4 to configure its own pin multiplexing if clocks and XRDC permissions are set appropriately? Any guidance or best practices from NXP or experienced users would be greatly appreciated. Thank you. Evaluation Board Re: Clarification on Pin Multiplexing Differences Between CM7 and CM4 on i.MX RT1176 Hi @meetbhatt2113 , Thank you so much for your interest in our products and for using our community. Q1: Is this difference expected on the RT1176 due to core ownership, XRDC restrictions, or the way MCUXpresso generates projects for dual-core devices? A1: I suggest you can refer to IMXRT1170RM chapter3 Memory Maps, especially 3.2 System memory map (CM7) and 3.3 System memory map (CM4). You can find out that multiple peripherals can run in CM4. Q2: What is the recommended approach when moving functionality from CM7 to CM4? Should pin multiplexing always be initialized on the CM7 core only, or is it valid for CM4 to configure its own pin multiplexing if clocks and XRDC permissions are set appropriately? A2: There are many SDK demos for CM4 for you to refer.        Pin multiplexing can be initialized on the CM7 core, but synchronization with the CM4 core must be carefully managed. Alternatively, CM4 can configure its own pin multiplexing if required. The choice depends on your project  requirement. Q3:  Any guidance or best practices from NXP or experienced users would be greatly appreciated. A3:  I suggest you can refer to  the following application notes. https://www.nxp.com/docs/en/application-note/AN13264.pdf https://www.nxp.com/docs/en/application-note/AN13114.pdf Wish it helps you. If you still have question about it, please kindly let me know.  Best Regards MayLiu

Synchronizing eFlexPWM Submodules (PWMA0, PWMA1, PWMB1, PWMB2) on MC56F84789 I am using the MC56F84789 DSC and I need to synchronize the outputs PWMA0, PWMA1, PWMB1, and PWMB2 so they start at the exact same clock cycle without any delay. I am using CodeWarrior 11.1. I have read in the reference manual that synchronization between submodules is possible via the MCTRL register, but I am struggling to implement this correctly in C. My current understanding: PWMA0/B0 belong to Submodule 0. PWMA1/B1 belong to Submodule 1, and so on. I need to use a "Master Reload" or "Master Sync" signal. Questions: How should I configure the CTRL2[INIT_SEL] and CTRL2[MASTER_RELOAD] bits to ensure all submodules use the same timing reference? What is the correct sequence in CodeWarrior to set the LDOK bits in the MCTRL register simultaneously for multiple submodules? If I am using Processor Expert, which properties should I change to enable this hardware synchronization? Any code example or register configuration sequence would be very helpful. Re: Synchronizing eFlexPWM Submodules (PWMA0, PWMA1, PWMB1, PWMB2) on MC56F84789 Hello @GuilhermeTodys , Thanks for your post. We have previously provided a sharing on this topic. Kindly refer to it for details. Two or more eFlexPWM synchronization for KV4x, KV5x, MC56F84xxx and MC56F82xxx Hope it helps. BR Celeste

Kernel panic when up the pfe interface Hi We are using the pfe interface to communicate to 5G module, when up the PFE interface through ifconfig(time 36.025547), an kernel panic occurs as blow: （Not 100% reproducible） [ 32.980723] pfeng 46000000.pfe pfe2 (uninitialized): PTP HW addend 0x80000000, max_adj configured to 46566128 ppb [ 32.980736] pfeng 46000000.pfe: IEEE1588: Input Clock: 200000000Hz, Output: 100000000Hz, Accuracy: 10.0ns [ 32.986068] pfeng 46000000.pfe pfe2 (uninitialized): Registered PTP HW clock successfully on EMAC2 [ 32.990989] pfeng 46000000.pfe pfe2: registered [ 32.993695] loadpfe: 5G module is not setup,reload_pf2_ko... [ 36.024860] pfeng 46000000.pfe: HIF2 started [ 36.024889] pfeng 46000000.pfe pfe2: configuring for fixed/rgmii link mode [ 36.024963] pfeng 46000000.pfe pfe2: Set TX clock to 125000000Hz [ 36.025232] pfeng 46000000.pfe pfe2: Set TX clock to 125000000Hz [ 36.025257] pfeng 46000000.pfe pfe2: Link is Up - 1Gbps/Full - flow control off [ 36.025547] IPv6: ADDRCONF(NETDEV_CHANGE): pfe2: link becomes ready [ 37.043292] pfeng 46000000.pfe: ERR: (PFENG_DEV) event 19 - TLITE Watchdog trigered: [pfe_wdt_csr.c:126] [ 37.043504] SError Interrupt on CPU0, code 0x00000000bf000002 -- SError [ 37.043515] CPU: 0 PID: 618 Comm: Global polling Tainted: G O 5.15.119-rt65+g96b69aed2 #1 [ 37.043526] Hardware name: GRCE DOCAP-STD (DT) [ 37.043531] pstate: 00000005 (nzcv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) [ 37.043541] pc : el1_abort+0x30/0x6c [ 37.043562] lr : el1_abort+0x24/0x6c [ 37.043571] sp : ffffffc00bea36b0 [ 37.043574] x29: ffffffc00bea36b0 x28: ffffff88064d91c0 x27: 0000000000000000 [ 37.043589] x26: 0000000000000000 x25: ffffffc0090f6920 x24: ffffff880569d880 [ 37.043603] x23: 0000000060000005 x22: ffffffc000bed2ac x21: ffffffc00d090108 [ 37.043615] x20: 0000000096000210 x19: ffffffc00bea36f0 x18: ffffffffffffffff [ 37.043629] x17: 0000000000000000 x16: 0000000000000000 x15: ffffffc00bea3d90 [ 37.043642] x14: 63c46b65a62b8000 x13: 00ffffc000c28c08 x12: ffffffc000bdb8ac [ 37.043657] x11: 00ffff880543dd00 x10: ffffffc0080d87d4 x9 : 0000000000000000 [ 37.043669] x8 : ffffffc00bea3bc8 x7 : 0000000000000000 x6 : ffffff88064d91c0 [ 37.043682] x5 : ffffffc00bea36f0 x4 : 0000002000000000 x3 : 0000000000000025 [ 37.043695] x2 : 0000002200000000 x1 : 0000000096000210 x0 : 0000000000000000 [ 37.043712] Kernel panic - not syncing: [ 37.043715] Asynchronous SError Interrupt [ 37.043719] CPU: 0 PID: 618 Comm: Global polling Tainted: G O 5.15.119-rt65+g96b69aed2 #1 [ 37.043729] Hardware name: GRCE DOCAP-STD (DT) [ 37.043734] Call trace: [ 37.043736] dump_backtrace+0x0/0x1b0 [ 37.043751] show_stack+0x18/0x24 [ 37.043762] dump_stack_lvl+0x68/0x84 [ 37.043774] dump_stack+0x18/0x34 [ 37.043784] panic+0xb8/0x378 [ 37.043792] add_taint+0x0/0xc0 [ 37.043803] arm64_serror_panic+0x64/0x74 [ 37.043812] do_serror+0x58/0x60 [ 37.043819] el1h_64_error_handler+0x30/0x50 [ 37.043827] el1h_64_error+0x78/0x7c [ 37.043835] el1_abort+0x30/0x6c [ 37.043844] el1h_64_sync_handler+0xa4/0xd0 [ 37.043854] el1h_64_sync+0x78/0x7c [ 37.043861] pfe_pe_mem_read+0x88/0x18c [pfeng] [ 37.044005] pfe_pe_memcpy_from_dmem_to_host_32_nolock+0xa4/0x120 [pfeng] [ 37.044104] pfe_pe_get_fw_messages_nolock+0xc8/0x524 [pfeng] [ 37.044200] pfe_class_isr+0x90/0x18c [pfeng] [ 37.044297] pfe_poller_func+0x144/0x25c [pfeng] [ 37.044395] thread_func+0x28/0x60 [pfeng] [ 37.044494] kthread+0x160/0x174 [ 37.044504] ret_from_fork+0x10/0x20 [ 38.044774] SMP: stopping secondary CPUs [ 41.770704] Kernel Offset: disabled [ 41.774161] CPU features: 0x1,20002001,20000842 [ 41.778675] Memory Limit: none It seem that the watchdog trigered, but i don't know the reason. Also, in the following log, it was not reported that the watchdog was triggered. [ 20.780716] loadpfe: 5G module is not setup,reload_pf2_ko... [ 20.940209] copy data to lin1 share memory [ 20.940232] copy data successful [ 20.941262] LLCE LIN init success [ 20.941270] LLCE LIN is in sleeping, success. [ 20.942289] LLCE LIN wakeup success [ 20.943285] LLCE LIN is operational, success. [ 23.811487] pfeng 46000000.pfe: HIF2 started [ 23.811516] pfeng 46000000.pfe pfe2: configuring for fixed/rgmii link mode [ 23.811591] pfeng 46000000.pfe pfe2: Set TX clock to 125000000Hz [ 23.811857] pfeng 46000000.pfe pfe2: Set TX clock to 125000000Hz [ 23.811882] pfeng 46000000.pfe pfe2: Link is Up - 1Gbps/Full - flow control off [ 23.812171] IPv6: ADDRCONF(NETDEV_CHANGE): pfe2: link becomes ready [ 23.827428] Internal error: synchronous external abort: 96000210 [#1] PREEMPT SMP [ 23.827428] SError Interrupt on CPU0, code 0x00000000bf000002 -- SError [ 25.899053] Modules linked in: pfeng(O) brcmfmac(O) cypress_cfg80211(O) compat(O) brcmutil(O) nxp_llce_lin llce_logger llce_can llce_mailbox llce_core [last unloaded: pfeng] [ 25.905648] CPU: 0 PID: 555 Comm: Global polling Tainted: G O 5.15.119-rt65+g96b69aed2 #1 [ 25.921091] CPU: 2 PID: 24 Comm: kworker/2:0 Tainted: G O 5.15.119-rt65+g96b69aed2 #1 [ 25.930638] Hardware name: GRCE DOCAP-STD (DT) [ 25.939752] Hardware name: GRCE DOCAP-STD (DT) [ 25.944180] pstate: 00000005 (nzcv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) [ 25.948610] Workqueue: mld mld_ifc_work [ 25.955549] pc : el1_abort+0x30/0x6c [ 25.959370] pstate: 800000c5 (Nzcv daIF -PAN -UAO -TCO -DIT -SSBS BTYPE=--) [ 25.962926] lr : el1_abort+0x24/0x6c [ 25.969871] pc : pfe_hif_chnl_cfg_irq_mask+0x10/0x38 [pfeng] [ 25.973431] sp : ffffffc00bfab6b0 [ 25.979073] lr : pfe_hif_chnl_irq_mask+0x30/0x4c [pfeng] [ 25.982370] x29: ffffffc00bfab6b0 x28: ffffff8809cbc340 x27: 0000000000000000 [ 25.987665] sp : ffffffc00913be60 [ 25.994782] x26: 0000000000000000 x25: ffffffc0090f6920 x24: ffffff8806ce6980 [ 25.998081] x29: ffffffc00913be60 x28: ffffff8800141140 x27: ffffffc008e25008 [ 26.005198] x23: 0000000060000005 x22: ffffffc000a5b2ac x21: ffffffc010090108 [ 26.012316] x26: ffffff8800959800 x25: ffffffc008e25008 x24: ffffffc008fc8680 [ 26.019433] x20: 0000000096000210 x19: ffffffc00bfab6f0 x18: 0000000000000000 [ 26.026551] x23: ffffffc00913bf34 x22: 000000000000005e x21: 0000000000000000 [ 26.033669] x17: 0000000000000000 x16: 0000000000000000 x15: 0000007f9672e1b0 [ 26.040786] x20: ffffff880183d240 x19: ffffff880183d200 x18: ffffffc00910b16c [ 26.047904] x14: 0000000000000000 x13: 00000000000000c8 x12: ffffffc008c69938 [ 26.055021] x17: ffffffc856a3c000 x16: ffffffc009138000 x15: 0000000000000000 [ 26.062139] x11: 0000000000000028 x10: 0101010101010101 x9 : ffffffc00bfabcb0 [ 26.069257] x14: 0000010024000000 x13: 33efbeff01000000 x12: 00000000000002ff [ 26.076374] x8 : 7f7f7f7f7f7f7f7f x7 : 0000000000000000 x6 : ffffff8809cbc340 [ 26.083492] x11: 0000000000000040 x10: ffffff8800007268 x9 : ffffff8800007260 [ 26.090609] x5 : ffffffc00bfab6f0 x4 : 0000002000000000 x3 : 0000000000000025 [ 26.097727] x8 : ffffff88004126e8 x7 : 0000000000000000 x6 : 0000000000000000 [ 26.104845] x2 : 0000002200000000 x1 : 0000000096000210 x0 : 0000000000000000 [ 26.111962] x5 : ffffff88004126c0 x4 : 0000000000010403 x3 : 0000000000000000 [ 26.119081] Kernel panic - not syncing: [ 26.126197] x2 : 0000000000000001 x1 : 0000000000000364 x0 : ffffffc010098364 [ 26.130017] Asynchronous SError Interrupt [ 26.137136] Call trace: [ 26.137135] CPU: 0 PID: 555 Comm: Global polling Tainted: G O 5.15.119-rt65+g96b69aed2 #1 [ 26.153104] Hardware name: GRCE DOCAP-STD (DT) [ 26.157533] Call trace: [ 26.159961] dump_backtrace+0x0/0x1b0 [ 26.163607] show_stack+0x18/0x24 [ 26.166906] dump_stack_lvl+0x68/0x84 [ 26.170551] dump_stack+0x18/0x34 [ 26.173850] panic+0xb8/0x378 [ 26.176801] add_taint+0x0/0xc0 [ 26.179926] arm64_serror_panic+0x64/0x74 [ 26.183918] do_serror+0x58/0x60 [ 26.187130] el1h_64_error_handler+0x30/0x50 [ 26.191383] el1h_64_error+0x78/0x7c [ 26.194942] el1_abort+0x30/0x6c [ 26.198153] el1h_64_sync_handler+0xa4/0xd0 [ 26.202320] el1h_64_sync+0x78/0x7c [ 26.205792] pfe_pe_mem_read+0x88/0x18c [pfeng] [ 26.210308] pfe_pe_memcpy_from_dmem_to_host_32_nolock+0xa4/0x120 [pfeng] [ 26.217078] pfe_pe_get_fw_messages_nolock+0xc8/0x524 [pfeng] [ 26.222807] pfe_class_isr+0x90/0x18c [pfeng] [ 26.227147] pfe_poller_func+0x144/0x25c [pfeng] [ 26.231747] thread_func+0x28/0x60 [pfeng] [ 26.235827] kthread+0x160/0x174 [ 26.239036] ret_from_fork+0x10/0x20 [ 26.242599] pfe_hif_chnl_cfg_irq_mask+0x10/0x38 [pfeng] [ 26.247891] pfeng_hif_chnl_direct_isr+0x1c/0x40 [pfeng] [ 26.253187] __handle_irq_event_percpu+0x60/0x250 [ 26.257872] handle_irq_event+0x64/0xfc [ 26.261693] handle_fasteoi_irq+0xc0/0x220 [ 26.265772] handle_domain_irq+0x98/0xe4 [ 26.269679] gic_handle_irq+0x54/0x130 [ 26.273411] call_on_irq_stack+0x20/0x4c [ 26.277317] do_interrupt_handler+0x54/0x60 [ 26.281483] el1_interrupt+0x30/0x80 [ 26.285040] el1h_64_irq_handler+0x18/0x24 [ 26.289120] el1h_64_irq+0x78/0x7c [ 26.292507] preempt_count_sub+0x8/0xd4 [ 26.296326] sch_direct_xmit+0x104/0x350 [ 26.300230] __dev_queue_xmit+0x4c0/0xb14 [ 26.304224] dev_queue_xmit+0x14/0x20 [ 26.307870] neigh_resolve_output+0xfc/0x1a0 [ 26.312122] ip6_finish_output2+0x198/0x790 [ 26.316290] __ip6_finish_output+0x154/0x280 [ 26.320543] ip6_finish_output+0x34/0xd0 [ 26.324449] ip6_output+0x74/0x1d0 [ 26.327833] NF_HOOK.constprop.0+0xd4/0xe0 [ 26.331914] mld_sendpack+0x24c/0x440 [ 26.335560] mld_ifc_work+0x244/0x4e0 [ 26.339205] process_one_work+0x1d4/0x490 [ 26.342824] SMP: stopping secondary CPUs [ 26.343198] worker_thread+0x13c/0x490 [ 26.350836] kthread+0x160/0x174 [ 26.354048] ret_from_fork+0x10/0x20 [ 26.357614] Code: d503233f 53180421 11059021 8b214000 (b9400001) [ 26.363687] ---[ end trace e96ab85bba3102c9 ]--- [ 26.368420] Kernel panic - not syncing: [ 26.372101] synchronous external abort: Fatal exception in interrupt [ 26.372227] Kernel Offset: disabled [ 26.381911] CPU features: 0x1,20002001,20000842 [ 26.386424] Memory Limit: none [ 26.389465] Rebooting in 10 seconds.. Env: BSP38.0  pfe 1.5.0 Re: Kernel panic when up the pfe interface Hello @irfank, This post was closed due to inactivity. Please create a new post in the community so a member of my team can offer you support. Thanks  Re: Kernel panic when up the pfe interface HEllo Are there any updates regarding this topic? We are experiencing the same issue . pc : el1_abort+0x30/0x64 lr : el1_abort+0x24/0x64 sp : ffffffc00a59b6c0 x29: ffffffc00a59b6c0 x28: ffffff8001a56200 x27: 0000000000000000 x26: 0000000000000000 x25: 0000000000000000 x24: ffffff8005911f80 x23: 0000000060000005 x22: ffffffc000c41b1c x21: ffffffc00d090108 x20: 0000000096000210 x19: ffffffc00a59b700 x18: ffffffffffffffff x17: 7420676f64686374 x16: 6157204554494c54 x15: 0000000000000000 x14: 0000000000000000 x13: 0000000000000000 x12: 0000000000000000 x11: 0000000000000000 x10: 0000000000000000 x9 : ffffffc000c43334 x8 : ffffffc00a59b9e4 x7 : 0000000000000000 x6 : 000000000000003f x5 : ffffffc00a59b700 x4 : 0000002000000000 x3 : 0000000000000025 x2 : 0000002200000000 x1 : 0000000096000210 x0 : 0000000000000000 Kernel panic - not syncing: Asynchronous SError Interrupt CPU: 1 PID: 253 Comm: Global polling Tainted: G O 6.1.76-yocto-standard #1 Hardware name: ----- Call trace: dump_backtrace.part.0+0xc8/0xd4 show_stack+0x20/0x30 dump_stack_lvl+0x6c/0x88 dump_stack+0x18/0x34 panic+0x180/0x33c add_taint+0x0/0xc0 arm64_serror_panic+0x78/0x84 is_valid_bugaddr+0x0/0x30 el1h_64_error_handler+0x30/0x4c el1h_64_error+0x64/0x68 el1_abort+0x30/0x64 el1h_64_sync_handler+0xd8/0xe4 el1h_64_sync+0x64/0x68 readl+0x4/0x20 [pfeng] pfe_pe_memcpy_from_dmem_to_host_32_nolock+0xb4/0x134 [pfeng] pfe_pe_get_fw_messages_nolock+0xfc/0x5a0 [pfeng] pfe_class_isr+0xb8/0x1b8 [pfeng] pfe_poller_func+0x14c/0x264 [pfeng] thread_func+0x30/0x60 [pfeng] kthread+0x110/0x114 ret_from_fork+0x10/0x20 SMP: stopping secondary CPUs Kernel Offset: disabled CPU features: 0x090000,00800084,0000420b Secondary Error (Poller Disabled) We attempted to disable the pfe_poller function to isolate the issue. However, the crash persists and has simply shifted to a different code path: Call trace: dump_backtrace.part.0+0xc8/0xd4 show_stack+0x20/0x30 dump_stack_lvl+0x6c/0x88 dump_stack+0x18/0x34 panic+0x180/0x33c add_taint+0x0/0xc0 arm64_serror_panic+0x78/0x84 is_valid_bugaddr+0x0/0x30 el1h_64_error_handler+0x30/0x4c el1h_64_error+0x64/0x68 el1_abort+0x30/0x64 el1h_64_sync_handler+0xd8/0xe4 el1h_64_sync+0x64/0x68 readl+0x4/0x20 [pfeng] pfe_pe_memcpy_from_dmem_to_host_32_nolock+0xec/0x174 [pfeng] pfe_pe_mem_process_lock+0x48/0x1b8 [pfeng] pfe_pe_memlock_acquire_nolock+0x4c/0x60 [pfeng] pfe_pe_memcpy_from_host_to_dmem_32+0x7c/0x138 [pfeng] pfe_class_write_dmem+0x114/0x180 [pfeng] pfe_phy_if_write_to_class_nostats+0x48/0x88 [pfeng] pfe_phy_if_promisc_enable+0x4c/0x198 [pfeng] pfeng_netif_set_rx_mode+0x230/0x320 [pfeng] __dev_set_rx_mode+0x70/0xb0 dev_set_promiscuity+0x7c/0x9c vlan_dev_change_rx_flags+0x64/0x7c [8021q] __dev_set_promiscuity+0x128/0x130 dev_set_promiscuity+0x2c/0x9c packet_dev_mc+0x34/0xe0 packet_setsockopt+0xbac/0x11ac __sys_setsockopt+0xa8/0x1a4 __arm64_sys_setsockopt+0x30/0x40 invoke_syscall+0x5c/0x130 el0_svc_common.constprop.0+0x4c/0xf4 do_el0_svc+0x34/0xc0 el0_svc+0x28/0xa0 el0t_64_sync_handler+0xf4/0x120 el0t_64_sync+0x18c/0x190 SMP: stopping secondary CPUs Kernel Offset: disabled CPU features: 0x090000,00800084,0000420b --------------------- Could you please provide insight into what might be causing this sequence? BSP38, pfe driver:1.5, pfe firmware:1.9.  Depends on pfe frimware release note. pfe frimware has backward compatibility.  回复： Kernel panic when up the pfe interface Hello @StanleyShen, After a long period of inactivity the community posts get closed automatically, please create anew post so I may receive proper notifications. You can include the link to this post and my username in the new post to ensure working with me if that is what you prefer. Sorry for the inconveniences.  Best regards. 回复： Kernel panic when up the pfe interface Here is the panic log 回复： Kernel panic when up the pfe interface @alejandro_e  Pls refer to the attachment file  Re: Kernel panic when up the pfe interface @alejandro_e  Hi, > One thing I can recommend is to use modprobe to remove and add the module, instead of rmmod; or find another mechanism > of detecting the 5G module instead of loading and unloading the driver, this way, once the module is detected you can load the > driver. Currently, pfeng.ko is automatically loaded when the system starts. Since the same problem reappeared ,can you tell me how to determine the firmware version of PFE and Where to download 1.7.1 version of the firmware? 回复： Kernel panic when up the pfe interface @alejandro_e  Hi, Since the same problem reappeared ,can you tell me how to determine the firmware version of PFE and Where to download 1.7.1 version of the firmware? Auto Linux Re: Kernel panic when up the pfe interface 1.5.0 Should be the Linux driver version, the FW should have a different version, can you confirm you are using firmware version 1.7.1? which is the version compatible with with BSP38 as per the release notes of that version. One thing I can recommend is to use modprobe to remove and add the module, instead of rmmod; or find another mechanism of detecting the 5G module instead of loading and unloading the driver, this way, once the module is detected you can load the driver. Re: Kernel panic when up the pfe interface @alejandro_e  Which BSP are you using? BSP38.0 Which PFE firmware version are you using? 1.5.0 What modifications have you added to the BSP? The background is that according to the characteristic of  RGMII, the RX clock of PFE needs to be initialized by the clock of the other party (5G module) before it can proceed. However, we cannot know the startup time of the other party (5G module), so the current method is to continuously load and unload the PFE driver (rmmod&modprobe pfeng), and then confirm whether communication with the 5G module is OK through the ping command. Therefore, during each startup process, the PFE driver will be continuously unloaded and loaded every 3 seconds until communication with 5G is normal. We have conducted multiple restart tests on this solution and found that it works most of the time, but there are occasional instances (approximately once in every 20 attempts) where the above crash problem occurs. Are you using the S32G-VNP-RDB2 board or a custom board? It's a  custome board  Are you using Yocto build or manual build? using Yocto build and the PFE firmware was created at /tmp/work/${machine-name}-fsl-linux/pfe/1.0.0-r0/image/lib/firmware directory Re: Kernel panic when up the pfe interface Hello @StanleyShen , I will need more information about you setup to be able to help you. Which BSP are you using? Which PFE firmware version are you using? What modifications have you added to the BSP? Are you using the S32G-VNP-RDB2 board or a custom board? Are you using Yocto build or manual build? Thanks in advance for the information. 回复： Kernel panic when up the pfe interface CPU is  S32G274A

[Veoneer] S32K388 SAF - BIST Execution and eMcem Issues Hi Team, Customer Veoneer (working on Comet projects), is having issues running BIST and eMcem on S32K388 device using SAF 1.0.5. They are running BIST, which is completing with the STCU registers indicating that all of the tests are finishing; however the device is not doing a functional reset afterwards, it is doing a destructive reset. Also, after this reset and performing eMcem init, the MCU encounters a hard fault. After checking the FCCU registers, these point to faults in NCF[0] and NCF[2]. Looking into DCM_GPR registers, these NCF flags translate to be the following errors: CM7_0_LOCKUP PRAM0_ECC_ERR CM7_2_ITCM_ECC_ERR We had debug calls with them to check and they have a configuration that follows all pre-requisites outlined in the UM for BIST, and couldn’t locate any immediate issues that could be causing the faults after eMcem init. Can you support and check what is missing and/or causing the BIST to trigger a destructive reset instead of the functional reset, and also if there’s any setting in their configuration that could be leading to the faults? I’m attaching SFR dump with their faults’ register information and their Tresos configuration. Here’s also a code snippet with the state machine they programmed to run and call BIST APIs and check for pre-conditions: NO_OPTIMIZE FUNC(void, SafetyMgr_CODE) SafetyMgr_Bist_Run (void) { Bist_StatusType bist_status = BIST_OK; Std_ReturnType return_val = E_OK; //SafetyMgr_Bist_PreconditionCheck(); /* Bist startup if the precondition are met */ //if ( (safetymgr_bist_precondition & SAFETYMGR_BIST_PRECOND_ALL_CHK) == SAFETYMGR_BIST_PRECOND_ALL_CHK) //{ bist_status = Bist_GetExecStatus(BIST_SAFETYBOOT_CFG/*BIST_DIAGNOSTIC_CFG*/); //To Do: Re-enable after SAF package is updated for S32K388 support switch (bist_status) { case BIST_BUSY: /* Timeout monitor */ safetymgr_bist_check = SAFETYMGR_BIST_CHK_TIMEOUT; break; case BIST_NORUN: /* Start Bist test */ SafetyMgr_Bist_PreconditionCheck(); if( (safetymgr_bist_precondition & SAFETYMGR_BIST_PRECOND_ALL_CHK) == SAFETYMGR_BIST_PRECOND_ALL_CHK) { return_val = Bist_Run(BIST_SAFETYBOOT_CFG/*BIST_DIAGNOSTIC_CFG*/); //To Do: Re-enable after SAF package is updated for S32K388 support if (return_val == E_NOT_OK) { safetymgr_bist_check = SAFETYMGR_BIST_CHK_TEST_NO_SUPP; } } break; case BIST_INTEGRITY_FAIL: /* Start Bist test */ SafetyMgr_Bist_PreconditionCheck(); if( (safetymgr_bist_precondition & SAFETYMGR_BIST_PRECOND_ALL_CHK) == SAFETYMGR_BIST_PRECOND_ALL_CHK) { return_val = E_OK; //Bist_Run(BIST_SAFETYBOOT_CFG/*BIST_DIAGNOSTIC_CFG*/); //To Do: Re-enable after SAF package is updated for S32K388 support if (return_val == E_NOT_OK) { safetymgr_bist_check = SAFETYMGR_BIST_CHK_TEST_NO_SUPP; } } SET_SWTP4(); break; case BIST_ERROR: safetymgr_bist_check = SAFETYMGR_BIST_CHK_ERROR; bist_error = Bist_GetRawErrorStatus(); //To Do: Re-enable after SAF package is updated for S32K388 support SET_SWTP2(); break; case BIST_FAILED: safetymgr_bist_check = SAFETYMGR_BIST_CHK_FAILED; bist_ret_val_RD = Bist_GetFailRDs (bist_LBistRDList, bist_MBistRDList); //To Do: Re-enable after SAF package is updated for S32K388 support SET_SWTP3(); break; default: /* bist_status is BIST_OK --> run of selected BIST sequence was successfully proceed without any faults */ safetymgr_bist_check = SAFETYMGR_BIST_CHK_NO_FAIL; SET_SWTP4(); break; } //} //else //{ /* Precondition not met */ //} //IP_MC_ME->MODE_CONF &= ~0x02; //Clear the functional reset //IP_MC_ME->MODE_UPD = 0x00; //update mode SET_SWTP5(); } /****************************************************************************** * details * This function ensures that all preconditions are met before starting the Bist * param[in] * none * param[in] * none * param[out] * none * param[out] * none * return * none * constraints * <> * invocation_criteria * <> ******************************************************************************/ NO_OPTIMIZE FUNC(void, SafetyMgr_CODE) SafetyMgr_Bist_PreconditionCheck (void) { /* Bist preconditions */ /* 1. Only a single core should be active and used to configure the MCU for the runtime self-test. Core CM7_0 is the recommended core. Hence, the MCU should enter an operating mode which disables all other cores and to ensure no other operation is being carried out by CM7_0. 2. All communication interfaces (like CAN, ENET, DSPI, FLEXRAY, I2C, etc.) need to be disabled. 3. Ensure that software initiated functional/destructive resets are not triggered while performing self-test. 4. All system and peripheral clocks should be configured to generate max functional frequency as defined in the device reference manual and data sheet. 5. LBIST_CLK should be set to 40 MHz. 6. The system clock should be based on PLL. */ uint32 RegVal1; uint8 instance; FLEXCAN_Type * const flexcanBase[] = IP_FLEXCAN_BASE_PTRS; LPSPI_Type * const Lpspi_Ip_apxBases[LPSPI_INSTANCE_COUNT] = IP_LPSPI_BASE_PTRS; MDM_AP_Type * const mdm_ap_base[] = IP_MDM_AP_BASE_PTRS; VAR(uint8, FBLMGR_VAR) tctr; VAR(Mcu_PllStatusType, FBLMGR_VAR) pll_status; /* Enable all clocks using alternate clock configuration */ do { tctr = (uint8)0; /* Minimum MCAL Initialization */ /* NXP: MCU Precompile variant selected. Config parameter not required */ //(void)Mcu_Init(&Mcu_PreCompileConfig); /* PLL Initialization */ /* Initialize MCU Clock*/ /* parameter 0 is chosen here by default, the first clock configuration */ (void)Mcu_InitClock(McuClockSettingConfig_1); /* wait till PLL lock or for the timeout to expire */ do { /* while here the PLL is unable to lock, keep waiting for it to lock or for the timeout to expire */ pll_status = Mcu_GetPllStatus(); tctr++; }while((pll_status != MCU_PLL_LOCKED) && (tctr < /*PLL_MAX_CHECK_STATUS_COUNTS*/ 100u)); }while(pll_status == MCU_PLL_UNLOCKED); /* distribute the clock */ Mcu_DistributePllClock(); Mcu_SetMode(McuModeSettingConf_1); /* disable all CAN */ for ( instance = 0; instance < FLEXCAN_INSTANCE_COUNT; instance++ ) { flexcanBase[instance]->MCR |= FLEXCAN_MCR_MDIS_MASK; } safetymgr_bist_precondition |= SAFETYMGR_BIST_PRECOND_CAN_CHK; /* disable all SPI */ for ( instance = 0; instance < LPSPI_INSTANCE_COUNT; instance++ ) { RegVal1 = (Lpspi_Ip_apxBases[instance]->CR & (~LPSPI_CR_MEN_MASK)); RegVal1 |= LPSPI_CR_RST_MASK; Lpspi_Ip_apxBases[instance]->CR = RegVal1; } /* ensure there is no function/destructive reset trigger */ if( MDM_AP_MDMAPSTTS_FUNCRST(mdm_ap_base[0]->MDMAPSTTS) == 0 ) { safetymgr_bist_precondition |= SAFETYMGR_BIST_PRECOND_FUNC_RST_CHK; } if( MDM_AP_MDMAPSTTS_DESTRST(mdm_ap_base[0]->MDMAPSTTS) == 0 ) { safetymgr_bist_precondition |= SAFETYMGR_BIST_PRECOND_DESTR_RST_CHK; } IP_MC_ME->MODE_CONF |= 0x02; //set functional reset IP_MC_ME->MODE_UPD = 0x01; //update mode } Thanks, Daniel V. Safety_SW Re: [Veoneer] S32K388 SAF - BIST Execution and eMcem Issues Hi Luke, I don't remember exactly, but I think we have compared Tresos MCU clock settings between SAF Demo example and customers setup and found some disabled cocks needed for LBIST. Simply you can turn on all clocks, higher freq, better and in addition you can disable all FCCU channels before BIST. Trying to avoid anything which could cause reset, so also turn off watchdogs, all external communication, PMIC WDG, other cores inactive (clock enabled but keep in reset or inactive) etc. Kind Regards, Radoslav Re: [Veoneer] S32K388 SAF - BIST Execution and eMcem Issues Hello @RadoslavB  and @dvelazquez  May I ask about your case? My customer is facing similar issue during BIST. May I ask, which point was related with the issue? (I saw that you mentioned only clock, but I would like to get more information..) Thank you. Re: [Veoneer] S32K388 SAF - BIST Execution and eMcem Issues Hi Daniel, Can we close this ticket? I think per last debug session we have resolved the issue by correct configuration of the clocks. Kind Regards, Radoslav Re: [Veoneer] S32K388 SAF - BIST Execution and eMcem Issues Update: sent customer .elf file for the SAF BIST demo discussed in meeting (attaching as reference). The team verified it worked on our side with K388 and checked the device ID so they should have the same chip revision as the customers.  Customer has new update, can you review: """ Hello, I ran into significant issues with flashing the precompiled elf files on our hardware, I am trying to correct the issues. But is there any chance that you can review this sample code? It is essentially our main, MCAL, and SAF files (everything else stripped out). With this reduced set I am still running into the issues with BIST not completing. I attached the pre-compiled binaries (under build/PrecompiledBinaries) as well as the source, make, and linker files used in our build. The .out files are just elf files. There are 3 binaries, ApplicationCore0, ApplicationCore2, and IVT. They each need to be flashed.  They were compiled and linked using Windriver Diab 7.0.4 """ Re: [Veoneer] S32K388 SAF - BIST Execution and eMcem Issues Update: We are currently in progress with the customer via debug calls. Customer is trying now to execute the BIST via SAF Demo which he didn't try yet. We are trying to find HW configuration differences which might corrupt BIST execution between the customer application and SAF Demo example.

S32M244 代码覆盖范围 您好， 我正试图使用 GHS 编译器在调试器中启用代码覆盖选项，以检查函数是否被执行。 请问在使用 GHS 编译器时，哪些调试器支持代码覆盖？ 先行致谢。 Re: S32M244 Code Coverage 你好 我想了解在使用 GHS 编译器进行版本时使用 Lauterbach TRACE32 获得代码覆盖率的可能方法，因为版本覆盖率不可用。在这种情况下，使用任何基于调试器的机制来实现代码覆盖是否可行？ 请直接与 Laterbach 联系。因为这不是恩智浦的产品。 https://support.lauterbach.com/ 此外，使用 GCC 编译器，版本代码覆盖范围是否支持并与 Lauterbach TRACE32 兼容？ 是的，GCC 通过 --coverage 或 -fprofile-arcs -ftest-coverage 支持编译覆盖率 (gcov)。这将生成 .gcno/.gcda 文件，您可以使用 gcov、llvm-cov gcov 或 gcovr 进行后处理。TRACE32 可以与此类仪器化版本共存（你仍然可以调试/跟踪它们），但是 TRACE32 本身不读取 .gcda/.gcno ——你可以使用 gcov 工具来计算/报告覆盖范围。 但这又是劳特巴赫支持的问题。 致以最诚挚的问候， Peter Re: S32M244 Code Coverage 你好、 我想了解在使用 GHS 编译器进行版本时使用 Lauterbach TRACE32 获得代码覆盖率的可能方法，因为版本覆盖率不可用。在这种情况下，使用任何基于调试器的机制来实现代码覆盖是否可行？ 此外，使用 GCC 编译器，版本代码覆盖范围是否支持并与 Lauterbach TRACE32 兼容？ 我目前正在使用恩智浦 S32M244 微控制器。 感谢您的帮助和宝贵意见。 期待您的指导。 顺祝商祺！ K.Adithya Re: S32M244 Code Coverage 你好 请查看您的案例的简要结果： 青山多功能 IDE + G-Cover 用于对象级代码覆盖（函数、分支、语句）的集成工具，无需工具。 时间机器剖析器 MULTI 套件的一部分；使用跟踪数据提供执行我的和覆盖率可视化。 VectorCAST 与 GHS 内置的外部测试工具，用于自动单元/集成覆盖率分析。 TRACE32（劳特巴赫） 高级调试器；支持 GHS 符号，但不提供内置覆盖率指标。 顺祝商祺！ Peter Re: S32M244 Code Coverage 您好， 请告诉我如何使用MULTI + G-Cover 在NXPS32M244控制器上实现函数和分支的代码覆盖？ 我想了解 GHS 编译器是否支持这一功能，以及设置时需要哪些先决条件。 此外，请分享使用 MULTI 和 G-Cover 启用覆盖和生成覆盖报告的详细步骤。 提前谢谢您。

IMX8MPマザーボードによるブート失敗 imx8mp-evkコアボードを搭載したマザーボードは、OTGからのU-Boot起動に失敗しました。ログ情報は次のとおりです。 U-Boot SPL 2025.04-g44898b9f3cfe(2025年9月3日 - 09:56:50 +0000) デバイスからの読み取りエラー: 95f310 レジスタ: x! DDRINFO: DRAM初期化を開始 DDRINFO: Re: 基于imx8mp 主板启动失败 どのフラッシュメモリから起動しているか教えていただけますか？ソフトウェアは適切に移植されていますか？BSPのバージョンはどれですか？ Re: 基于imx8mp 主板启动失败 こんにちは@hjk003さん、 fastboot が U-Boot のフラッシュに失敗する問題については、BSP の使用方法と手順を明確に説明した新しい投稿を作成していただくことをお勧めします。これにより、弊社のエンジニアがより迅速にアドバイスを提供できるようになります。 よろしくお願いします リタ Re: 基于imx8mp 主板启动失败 こんにちは、私も同じ質問があります。どうやって直せばいいですか?

S32K3 ICU 频率和边缘触发信号问题 当我进行重症监护病房捕获时，我遇到了以下两个问题。我想征求所有工程师的意见。120MHZ ) 问题如下： 1. 如何捕获 50Hz PWM 信号？ 这里的最大分频为 16，无法精确获得 50Hz 信号。如何进一步划分频率？ 2.通过 IcuDefaultStartEdge 中的 3 个调试方法，发现可以通过 Icu_GetDutyCycleValues() 函数获取 ActiveTime 和 PeriodTime 的值。我没发现有什么不同。能否请您解释一下这三种方法在使用上的区别？ 谁能帮帮我？非常感谢。 回复： 还有一个问题： 我想将 IcuEmiosBusRef 配置为 EmiosCommon_1 (Emios1)。然而，即使配置了 Mcl，ICU 侧的 IcuEmiosBusRef 下拉界面也没有显示。此外，我还尝试手动修改路径，虽然可以导航到 Mcl 的 EmiosCommon_1 (Emios1)，但并没有跳转成功。但是会出现错误，如下图所示： 为什么会这样呢？您能帮我看看吗？ 非常感谢。 Re: S32K3 ICU Frequency and Edge Triggering Issues 您好， 1) 还有一个 eMIOS 全局预分频器，它按 1-256 模块时钟向下分频。然后，全局预分频时钟进入各个通道的内部预分频器（1-16）。假设通道 C2[UCPRECLK] 已清零。 2) 这会影响信道 EDPOL/EDSEL 配置，因此，如果不测量 50% 的占空比信号，则至少占空比/有效时间值会有所不同。 BR, Petr Re: 回复： 您好， ICU 所选通道很可能不是来自 eMIOS1 模块，请检查 eMIOS 硬件模块值。 BR, Petr Re: S32K3 ICU Frequency and Edge Triggering Issues 非常感谢。问题已经解决。

NCF29A1 Technical Information I've already signed an NDA with NXP and applied for the relevant security access on the official website, but how come I can't check the relevant information about this chip? Re: NCF29A1技术资料 I have requested access to this type of security documentation, the problem now is that I can't find the documentation for this chip on the NXP website. Re: NCF29A1技术资料 Hello @C_TANG1986753951 My apologies, information about this kind of automotive parts is under NDA (Non-Disclosure Agreement), it is not public, and this is not a secure communication channel to share any information about it. For further information and support on this part, could you please contact your local Distributor or the person who helped you with information of this product in a first place? I really apologize for the inconvenience this might cause you. Regards, Eduardo. Re: NCF29A1技术资料 Hi, Please contact your local Distributor or NXP Sales for further support on this. Regards, Eduardo.

[不正使用] 投稿者: @JohnKlug / ボード: imx-プロセッサ / 報告者: jlproet jlproet は、 @JohnKlug が投稿した 「Could not invoke dnf for external kernel module in Yocto kirkstone」という 投稿について、以下の理由で報告しました: 理由:嫌がらせ 詳細： %EB%%94%%91%%EC%%B4/%%98%%EA%%88%%B0%%EB%%91%%9D% 投稿リンク: https://community.nxp.com/t5/i-MX-Processors/Could-not-invoke-dnf-for-external-kernel-module-in-Yocto/mp/1627964#M203740 投稿者: @JohnKlug |メール著者 報告者: jlproet |メールレポーター 報告された投稿には 2 件の返信があります。

[不正使用] 投稿者: @JohnKlug / ボード: imx-プロセッサ / 報告者: hqutlea hqutlea は、 @JohnKlug が投稿した 「Could not invoke dnf for external kernel module in Yocto kirkstone」という 投稿について、以下の理由で報告しました: 理由:その他 詳細： 投稿リンク: https://community.nxp.com/t5/i-MX-Processors/Could-not-invoke-dnf-for-external-kernel-module-in-Yocto/mp/1627964#M203740 投稿者: @JohnKlug |メール著者 報告者: hqutlea |メールレポーター 報告された投稿には 2 件の返信があります。

[ABUSE] Post By: @JohnKlug / Board: imx-processors / Reported by: xwujogop xwujogop has reported the post Could not invoke dnf for external kernel module in Yocto kirkstone posted by @JohnKlug for the following reasons: Reason: Spam Details: https://www.chstm.org/node/79809"> https://golemobuchino.com/content/2469/pharmacy-online"> http://kalyterizoi.gr/initiative/pharmacy-online-0"> https://dev.beautynbrushes.com/services-provided/invisible-ponytail-maroonimmortalep"> https://backend.dawahnigeria.com/audit/304767"> https://www.danduo168.com/en/artworks/692/pharmacy-online-1"> https://cadel.ru/pharmacy-online-0"> http://ph-ed-plus.nspu.ru/article/17925"> https://liderforum.webconfmep.gate1.campuz.org/ru/content/pharmacy-online-12"> https://events.citeve.pt/question-usersquashtalk-time1759025704"> https://www.rapidservice.com.ec/es/content/1-sobres-documentos-47554"> http://hr-life.ru/node/53788"> https://museusvalenciades.grupotecopy.es/en/node/2362"> https://hunam.mx/no-12515-organizacion-de-bibliotecas"> https://golemobuchino.com/content/2469/pharmacy-online"> https://app.feizufenqi.com/fp/content/pharmacy-online-4"> http://xn--80ab2anoq0a.xn--p1ai/art/pharmacy-online-3"> http://www.alsongs.com.hk/node/15608"> https://www.vgame.ca/node/46848"> https://trenerbiegania.pl/blog/rubina-oneil/pharmacy-online"> https://museusvalenciapre.grupotecopy.es/en/node/3716"> https://escolesvalenciades.grupotecopy.es/val/node/1303"> https://www.albatrosplus.ru/pharmacy-online-24"> https://events.citeve.pt/question-usersquashtalk-time1759025704"> https://carros-usados.us/pharmacy-online-14"> http://www.alsongs.com.hk/node/15608"> https://museusvalenciades.grupotecopy.es/en/node/2362"> https://neweddingday.com/your-couple-name-2367"> https://ruckup.org/caregivers-forum/topic/6379"> https://reflexologie-cerilly.fr/en/node/4238"> https://satto.vtranet.com/binh-luan-392"> http://www.le-cercle-des-sourires.fr/article/pharmacy-online-0"> https://www.rapidservice.com.ec/es/content/1-sobres-documentos-47554"> https://recruitment.kenet.or.ke/node/2039"> http://pi5ny.com/node/4952"> http://stage.isupportveterans.org/node/5267"> https://www.globalrealtor.co.in/node/4213"> https://rus.langnotes.ru/phonetics/pharmacy-online"> https://cadel.ru/pharmacy-online-0"> https://www.aairlab.com/IDev/?q=node/248"> Post link: https://community.nxp.com/t5/i-MX-Processors/Could-not-invoke-dnf-for-external-kernel-module-in-Yocto/m-p/1627964#M203740 Post author: @JohnKlug | Email Author Reported by: xwujogop | Email Reporter The reported post has 2 replies.

闪存完整性测试（SM1.FLASH.AI_SELFCHECK） 我目前正在努力启用闪存功能安全机制（SM1.FLASH.AI_SELFCHECK），并且对实现有一些疑问。   我在 c40_ip 驱动程序中找到了两个相关的 API：C40_Ip_ArrayIntegrityCheck 和 Fls_IPW_CheckUserTestStatus。   1.如果 C40_Ip_ArrayIntegrityCheck 启动闪存完整性测试并返回测试状态（真或假），那么 Fls_IPW_CheckUserTestStatus API 的具体用途是什么？   2.我知道在进行闪存完整性测试之前，需要将代码从闪存复制到 SRAM。能否就如何实施提供指导？链接器脚本需要做哪些具体修改？   3.在最新的 AUTOSAR 标准中，使用了 mem40_Infls 模块。以前的 AUTOSAR 版本包括 fls 模块，它为用户测试模式提供了配置选项。如何使用最新的 AUTOSAR 版本实现用户测试功能？   感谢您对这些问题的帮助。   Re: Flash Integrity test (SM1.FLASH.AI_SELFCHECK) 嗨，丹尼尔， ，我使用的是 RTD 3.0.0。您提到的最新 RTD 中可能包含上述 api。我会检查的。 如果您能提供数组完整性检查的示例代码，将对我们更有帮助。 Regards Sandeep Singh Re: Flash Integrity test (SM1.FLASH.AI_SELFCHECK) 你好，我是@sandeepSingh18606、 您使用的是哪个版本的 RTD？ 1. 我认为这与 Mem_43_INFLS （S32K3xx RTD 6.0.0）中的当前实现非常相似。 Mem_43_INFLS_ArrayIntegrityCheck() Mem_43_INFLS_GetJobUtestState() C40_Ip_ArrayIntegrityCheck() C40_Ip_CheckUserTestStatus() 请参阅 RTD_MEM_43_INFLS_UM.pdf（位于 RTD 安装文件夹中）。 3.6.4.3 驱动程序硬件实用程序测试模式服务 此外，还有如何使用应用程序接口的示例。 2. 让我检查一下。 3. 请参阅上述《用户手册》。 此致， 丹尼尔 Re: Flash Integrity test (SM1.FLASH.AI_SELFCHECK) 你好，我是@sandeepSingh18606、 现附上使用 RTD 3.0.0 创建的示例P07. 我们没有其他参考项目。 此致， 丹尼尔 Re: Flash Integrity test (SM1.FLASH.AI_SELFCHECK) 嗨，丹尼尔， 关于上述主题是否有任何更新？ 致敬 桑迪普-辛格 Re: Flash Integrity test (SM1.FLASH.AI_SELFCHECK) 嗨，丹尼尔   感谢您提供示例代码。   我已经测试了代码，虽然它偶尔会起作用，但它主要是进入总线故障处理程序。检查 CPU 寄存器后，CFSR 显示指令位错误。     我怀疑在启动阵列完整性检查之前，需要将代码移到 SRAM 中。   请告知正确的执行程序。   顺祝商祺！ 桑迪普-辛格 Re: Flash Integrity test (SM1.FLASH.AI_SELFCHECK) 你好，我是@sandeepSingh18606、 很抱歉延迟回复--我现在不在办公室。 你是对的；它应该从 SRAM 运行。 我还没有发现任何基于闪存的示例包含从 SRAM 运行的完整性检查。我还联系了 C40_Ip 驱动程序的所有者，询问他们是如何验证这一点的，得到的答复是整个测试项目都是通过 SRAM 执行的。 您可以将 C40_Ip_ArrayIntegrityCheck()、C40_Ip_CheckUserTestStatus() 和您的封装函数放在 SRAM 中，类似于下面示例中的做法。目前，我还不能完全确定是否有其他功能也需要转移到 SRAM 中。 https://community.nxp.com/t5/S32K-Knowledge-Base/S32K312-C40-Ip-SRAM-RTD-500-DS35/ta-p/2074245 此致， 丹尼尔 Re: Flash Integrity test (SM1.FLASH.AI_SELFCHECK) 嗨，丹尼尔   谢谢您的建议。   我尝试使用所提供的示例代码从 SRAM 执行数组完整性检查功能。但是，该应用程序当前正在触发硬故障错误。我怀疑可能需要更新链接器文件才能支持这种实现方式。 Re: Flash Integrity test (SM1.FLASH.AI_SELFCHECK) 嗨，丹尼尔   非常感谢你们的支持。我的链接器脚本出了问题，现在我已经更新了。我这边一切正常。 我接受的上述示例解决方案对我来说是可行的，包括从 SRAM 运行示例代码。   顺祝商祺！   桑迪普-辛格

[ABUSE] Post By: @JohnKlug / Board: imx-processors / Reported by: ujonvenq ujonvenq has reported the post Could not invoke dnf for external kernel module in Yocto kirkstone posted by @JohnKlug for the following reasons: Reason: Harassment Details: https://chitapage.ru/auto/17218"> https://gglabs.us/node/5704"> https://futbal.totalhockeymanagement.com/pharmacy-online"> https://lotteryobzor.com/forum/pharmacy-online-2"> https://www.jobwebby.ilovemarkso.com/domainasname-anthony-gmbh/pharmacy-online-0"> http://onlyforsalebyowner.com/for-sale-by-owner-homes/ok/32"> https://asafestival.com/de/node/3800"> http://www.hudebniburza.cz/dilo/pharmacy-online-4"> https://obzorpoker.info/forum/pharmacy-online-2"> https://gglabs.us/node/5704"> https://www.spinsheet.com/racing-team-log/pharmacy-online-0"> https://www.ziveknihy.sk/audiokniha/pharmacy-online-3"> http://03otvet.ru/voprosy/dietologiya/pharmacy-online"> http://shop.ls-s.ru/product/10106"> http://en.sp-journal.ru/article/19174"> https://carros-usados.us/pharmacy-online-9"> https://lotteryobzor.com/forum/pharmacy-online-2"> https://www.rapidservice.com.ec/es/content/1-carga-pesada-14481"> http://lsdsng.com/node/4265"> https://evere.co/articles/pharmacy-online-2"> https://www.intellectualpedia.org/countyelectron-pharmacy-online-2"> https://slp.millingtonpubliclibrary.org/content/pharmacy-online-2"> https://masters.adminskiracing.com/node/413301"> http://surfing.4fan.cz/node/147"> https://asafestival.com/de/node/3800"> https://whs6570.com/node/2096"> https://www.isupportveterans.org/node/3030"> http://santorini.cz/node/6337"> http://stage.isupportveterans.org/node/5260"> https://californiaweddingday.com/your-couple-name-2328"> http://xn--80ab2anoq0a.xn--p1ai/story/pharmacy-online-2"> https://masters.adminskiracing.com/node/413301"> https://www.ziveknihy.sk/audiokniha/pharmacy-online-3"> http://en.sp-journal.ru/article/19174"> https://www.jobwebby.ilovemarkso.com/domainasname-anthony-gmbh/pharmacy-online-0"> http://www.hudebniburza.cz/dilo/pharmacy-online-4"> https://www.onlyhomebuyers.com/for-sale-by-owner-homes/44"> http://lsdsng.com/node/4265"> https://www.trustcirclenetworks.org/issues/2221"> https://slp.millingtonpubliclibrary.org/content/pharmacy-online-2"> Post link: https://community.nxp.com/t5/i-MX-Processors/Could-not-invoke-dnf-for-external-kernel-module-in-Yocto/m-p/1627964#M203740 Post author: @JohnKlug | Email Author Reported by: ujonvenq | Email Reporter The reported post has 2 replies.

MPC5777c etpu 特定の etpu チャネルのパルス数とパルス幅をどのように読み取るか。 Re: MPC5777c etpu eTPU は複雑な I/O コプロセッサです。2 つの方法で使用できます。 1) NXPが用意したeTPU機能を使用する 2) 独自の関数を作成したり、NXPの関数を変更したりする 広告1） NXP によって事前に準備された eTPU 関数 (eTPU 関数セレクタでダウンロードできるもの) を変更なしで使用するには、eTPU コンパイラは必要ありません。見る http://www.nxp.com/webapp/etpu/ また、現在はいくつかの機能のみを含む新しいバージョンもいくつかあります。 http://www.nxp.com/webapp/etpu_cw/ ダウンロードして、eTPU グラフィカル構成ツール (GCT) で構成し、必要なすべてのファイルを CodeWarrior またはその他のコンパイラに含めて使用するだけです。 GCT は、NXP が用意したほとんどの機能を構成することを目的としたツールで、ここからパックとしてダウンロードできます。 http://www.nxp.com/webapp/sps/download/license.jsp?colCode=ETPUGCT&Parent_nodeId=1311258915317726989428&Parent_pageType=product ここでは、eTPU PWM 機能の使用方法を段階的に例示します。 http://www.nxp.com/files/soft_dev_tools/doc/app_note/AN4687.pdf すべての eTPU FUNCTION には独自の説明ドキュメント (アプリケーション ノート) があり、そのソフトウェア アタッチメントには通常、いくつかの簡単なサンプル コードが含まれています。 http://www.nxp.com/products/automotive-products/microcontrollers-and-processors/32-bit-power-architecture/ultra-reliable-mpc56xx-32-bit-automotive-industrial-microcontrollers-mcus/enhanced-time-processor-unit:eTPU?tab=Documentation_Tab 広告2） 既存の eTPU 関数をアプリケーションに適合できない場合は、独自の関数を作成するか、既存の関数を変更することができますが、そのためには eTPU コンパイラとシミュレータが必要になります。 現在、2 つのオプションがあります。 1) Ashwareソリューション（コンパイラ+シミュレータ） https://www.ashware.com/etpu2-simulators 2) NXP eTPU2 開発スイート（コンパイラ + シミュレータ） http://www.nxp.com/products/automotive-products/microcontrollers-and-processors/32-bit-power-architecture/ultra-reliable-mpc56xx-32-bit-automotive-industrial-microcontrollers-mcus/codewarrior-development-studio-for-etpu-v10.3:eTPU2

S32K312, VKMS, Specify the output parameters of Csm_KeyElementGet Hi CRT team: The original ticket is: VKMS-HSE-Specify-the-output-parameters-of-Csm-KeyElementGet  customer: Yanfeng  project: VW project  Our customer Yanfeng is using the VKMS HSE FW + S32K312 in their project.  During VKMS functional testing at VW Auto, one of the test results did not match the theoretical value. Based on an initial assessment by the local team and customer, the issue appears to be related to the output parameters of  Csm_KeyElementGet() .   A similar phenomenon also occurred in the VKMS Demo within RTD 400P21, as shown in the figure below.         The customer’s current question is:   why does the return value of Vkms_u32ResponseLength = 3 after executing  Csm_KeyElementGet(CsmConf_CsmKey_CsmKey_0xF0010002, 0xF0010002U, Vkms_au8Response, &Vkms_u32ResponseLength ); to get training counter ?   According to the customer’s description, theoretically, this return value should be the following: If meta data of one key are required: 5 If meta data if all keys are required: 1+ * 6 Could you please help to have a check? Best Regards, Zheng Lin Board: S32K312 Component: HSE FW Component: Security Crytpo Priority: MEDIUM SW Variant: CUSTOM Type: ISSUE Re: S32K312, VKMS, Specify the output parameters of Csm_KeyElementGet Hi Cuong, Please find below info:  - S32K3 RTD version: RTD 4.0.0 P21  - Platform: S32K312   - HSE FW Version: 9.2.26.0  - Crypto configuration files: As mentioned in the ticket, test with the VKMS demo project of RTD  - What is stored in CsmKey_0xF0010002, and what is the expected theoretical value? As mentioned in the ticket, test with the VKMS demo project of RTD, CTM want to have a clarify of the result of the RTD demo. Best Regards, Zheng Lin Re: S32K312, VKMS, Specify the output parameters of Csm_KeyElementGet Hi @ZhengLin  Could you specify more information about customer environment:  - S32K3 RTD version  - HSE FW Version  - Crypto configuration files  - What is stored in CsmKey_0xF0010002, and what is the expected  theoretical value? Re: S32K312, VKMS, Specify the output parameters of Csm_KeyElementGet Hi Cuong, Is there any update about this case? Best Regards, Zheng Lin Re: S32K312, VKMS, Specify the output parameters of Csm_KeyElementGet Hi Cuong, The customer got below theoretical info from the document provided by Audi, which cannot share with us, but we can set a online meeting with the customer if needed. Best Regards, Zheng Lin

Flash Integrity test (SM1.FLASH.AI_SELFCHECK) I am currently working on enabling the flash memory safety mechanism (SM1.FLASH.AI_SELFCHECK) and have a few questions regarding the implementation.   I found two relevant APIs in the c40_ip driver: C40_Ip_ArrayIntegrityCheck and Fls_IPW_CheckUserTestStatus.   1. If C40_Ip_ArrayIntegrityCheck starts the flash integrity test and returns the test status (true or false), what is the specific purpose of the Fls_IPW_CheckUserTestStatus API?   2. I understand that the code needs to be copied from flash to SRAM before running the flash integrity test. Could you please provide guidance on how to implement this? What specific changes are required in the linker script?   3. In the latest AUTOSAR standard, the mem40_Infls module is used. Previous AUTOSAR versions included the fls module, which provided configuration options for a user test mode. How can the user test functionality be achieved using the latest AUTOSAR version?   Thank you for your help with these queries.   Re: Flash Integrity test (SM1.FLASH.AI_SELFCHECK) Hi Daniel, I am using RTD 3.0.0. Above api's may be available in latest RTD you mentioned. I will check that. It will be more helpful if you can share any example code for array integrity check if you have. Regards Sandeep Singh Re: Flash Integrity test (SM1.FLASH.AI_SELFCHECK) Hi @sandeepSingh18606, Which version of the RTD do you use?  1. I think this is very similar to the current implementation in Mem_43_INFLS (S32K3xx RTD 6.0.0) Mem_43_INFLS_ArrayIntegrityCheck() Mem_43_INFLS_GetJobUtestState() C40_Ip_ArrayIntegrityCheck() C40_Ip_CheckUserTestStatus() Refer to RTD_MEM_43_INFLS_UM.pdf (located in the RTD installation folder). 3.6.4.3 Driver Hardware Utest Mode Service There are also examples how to use the APIs. 2. Let me check. 3. Refer to the User Manual mentioned above. Regards, Daniel Re: Flash Integrity test (SM1.FLASH.AI_SELFCHECK) Hi Daniel, Is there any update on above topic? Regards Sandeep Singh Re: Flash Integrity test (SM1.FLASH.AI_SELFCHECK) Hi @sandeepSingh18606, I'm attaching an example created with RTD 3.0.0 P07. We don't have any other reference project. Regards, Daniel Re: Flash Integrity test (SM1.FLASH.AI_SELFCHECK) Hi Daniel,   Thank you for providing the example code.   I have tested the code, and while it occasionally works, it is mostly entering the bus fault handler. After checking the CPU registers, the CFSR indicates an instruction bit error.     I suspect the code needs to be moved to SRAM before starting the Array Integrity Check.   Could you please advise on the correct procedure for implementing this?   Best regards, Sandeep Singh Re: Flash Integrity test (SM1.FLASH.AI_SELFCHECK) Hi @sandeepSingh18606, I'm sorry for the delayed response — I am currently out of the office. You are correct; it should run from SRAM. I haven't found any flash-based example that includes the integrity check running from SRAM. I also contacted the owner of the C40_Ip driver to ask how this was validated, and the answer was that the entire test project was executed from SRAM. You can place C40_Ip_ArrayIntegrityCheck(), C40_Ip_CheckUserTestStatus(), and your wrapper function in SRAM, similar to how it is done in the following example. At the moment, I'm not fully sure if there are additional functions that also need to be moved to SRAM. https://community.nxp.com/t5/S32K-Knowledge-Base/S32K312-C40-Ip-SRAM-RTD-500-DS35/ta-p/2074245 Regards, Daniel Re: Flash Integrity test (SM1.FLASH.AI_SELFCHECK) Hi Daniel,   Thank you for your suggestion.   I have attempted to execute the array integrity check function from SRAM using the provided example code. However, the application is currently triggering a Hard Fault error. I suspect that updates to the linker file may be required to support this implementation. Re: Flash Integrity test (SM1.FLASH.AI_SELFCHECK) Hi Daniel,   Thank you very much for your support. There was an issue with my linker script, which I have now updated. Everything is working correctly on my end. The above example I have accepted as solution is working for me including running example code from SRAM.   Best regards,   Sandeep Singh

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[IMX8ULP] Cannot disable power switches using uPower API Hello!  We are trying to optimize power usage on imx8ulp. According to AN13951 it is recommended to disable unused modules. Thus, we are trying to disable HIFI4 with API call in M33 code and it returns success: UPOWER_PowerOffSwitches((upower_ps_mask_t)(kUPOWER_PS_HIFI4));   Than we are monitoring power consumption with another API call: upwr_vtm_power_measure(PowerSwitchSel_HIFI4, UPOWER_DummyCallback); upwr_poll_req_status(sg, &sgf, &err, result, 0); And we observe that it is not 0 as we expect: HIFI4_POWER: I=44mA How can we turn off power switch and make sure it is actually disabled? i.MX8ULP Re: [IMX8ULP] Cannot disable power switches using uPower API refer to the i.mx8ulp domain, HIFI4 is belong to LPAV domain, for this, try to disable in the uboot via upwr_pwm_power_off https://github.com/nxp-imx/uboot-imx/blob/4ddbad60eff308a5b356fb9ab8734ac382ddd692/arch/arm/mach-imx/imx8ulp/upower/upower_api.c  Re: [IMX8ULP] Cannot disable power switches using uPower API That helps, thank you!