i.MX7D UART5 in DTE mode using I2C4 Hi. This is the original i.MX7D board. The 2-wire UART5 circuit uses the I2C4 port. This UART5 is in DTE mode. I am configuring the CCM, IOMUXC ports, IOMUXC DAISY settings, and UART5. CCM_TARGET_ROOTn=0x10000000 CCM_CCGRn=0x3 IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL=1 IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA=1 IOMUXC_UART5_RX_DATA_SELECT_INPUT=1 UART5_UCR1=1 UART5_UCR2=0x7027 UART5_UCR3=0x784 UART5_UCR4=0x8000 UART5_UFCR=0x240 UART5_UBIR=0xF UART5_UBMR=0x271 After sending one character, UART5_UTS remains at 0x20 (having changed from 0x60). I do not know why UART5_UTS does not return to 0x60. Best Regards. Re: i.MX7D UART5 in DTE mode using I2C4 Spoiler (Highlight to read) Hi. AldoG. There was an error in a portion of the information I sent. UART5_CLK_ROOT(0x30380b18)=0x10000000 The correct version is as follows. UART5_CLK_ROOT(0x3038b180)=0x10000000 Best regards. Re: i.MX7D UART5 in DTE mode using I2C4 Hi. AldoG. Upon startup, for some reason IPG_CLK_ROOT (0x30389080) was set to 0x1, so I changed it to 0x0. UART5_CLK_ROOT(0x30380b18)=0x10000000 UART5_CCM_CCGR=CCM_CCGR152(0x30384980)=0x3 It has been set up this way. I tried changing the pins used from I2C4 to SAI1, but the result was unsuccessful. I set the register to be checked to TXDC within USR2. Best regards. Re: i.MX7D UART5 in DTE mode using I2C4 Hello,
For the i.MX7D UART status register, UTS[6] is the TX FIFO empty indication and UTS[5] is the RX FIFO empty indication. Therefore, 0x60 indicates that both FIFOs are empty, while 0x20 indicates that the RX FIFO is empty but the TX FIFO is not yet empty. Seeing 0x20 immediately after writing a character can therefore be expected.
UTS[6] only reflects the FIFO state. If you need to determine when the character has completely finished transmitting, check USR2[TXDC], which indicates that the transmit FIFO and shift register are empty.
For this two-wire configuration, please also verify the following:
Hardware CTS/RTS flow control is disabled. If CTS/RTS is enabled without the corresponding signals being connected, transmission may be prevented.
Both the UART5 functional clock and the IPG clock are enabled, and the UBIR/UBMR values are calculated using the actual UART5 clock frequency.
The DTE pin mapping is checked against the i.MX7D Reference Manual. DTE mode changes the apparent RX/TX pin direction, so the signal names can be confusing.
The I2C4 peripheral is not also enabled or driving the same pads.
The UART5 TX pin is probed with an oscilloscope or logic analyzer. If a valid waveform is present, the 0x20 reading is likely only a status-sampling issue. If no waveform is present, check the clock, flow-control, and pin-mux configuration first.
Please refer to the i.MX 7Dual Reference Manual (IMX7DRM), especially the UART and IOMUX sections. The NXP discussions iMX7 UART pin setup and i.MX7 IPG_CLK_ROOT and UART's clock may also be useful. Best regards/Saludos, Aldo. Re: i.MX7D UART5 in DTE mode using I2C4 Hello, TXDC indicates that the TX FIFO and shift register are empty. Please check whether USR2[TXDC] becomes 1 after the character is sent. If it remains 0, please also capture the UTS, USR1, and USR2 values before and after transmission, together with the UART5 TX pin waveform.
For the two-wire configuration, please also verify that hardware CTS/RTS flow control is disabled. If CTS/RTS is enabled without the corresponding signals being connected, the transmitter may remain blocked. Also confirm that no I2C4 or SAI1 peripheral remains enabled and driving the selected pads. Best regards/Saludos, Aldo. Re: i.MX7D UART5 in DTE mode using I2C4 Hi AldoG, To avoid confusion caused by DTE mode, I modified the board wiring to set it to DCE mode. After initialization in U-Boot, I used an oscilloscope to monitor the pin voltage levels while toggling the IOMUXC pull-up/pull-down settings. The input pins responded correctly to these configuration changes. Next, I set the DTE bit in the UART5_UFCR register and repeated the test; the input pins again responded correctly to the configuration changes. The output pins switch according to the DCE/DTE configuration, and in both cases, the voltage level is '1'. Therefore, the PAD configuration is correct. Since the IRTS bit in the UART5_UCR2 register is set to '1', the RTS signal should be ignored. Could you please provide specific, detailed support on what I should investigate next to resolve this issue? Best regards. Re: i.MX7D UART5 in DTE mode using I2C4 Hi AldoG. The issue has been resolved. I have reverted from the 2-wire DCE mode to the 3-wire DTE mode. The pins used are I2C3_SCL, I2C4_SCL, and I2C4_SDA. The clock is configured via the CCM in `/arch/arm/mach-imx/mx7/clock.c` within the `init_clk_uart()` function. The pin configuration is as follows: static iomux_v3_cfg_t const uart5_pads[] = { MX7D_PAD_I2C3_SCL__UART5_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL), MX7D_PAD_I2C4_SCL__UART5_DTE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), MX7D_PAD_I2C4_SDA__UART5_DTE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), }; imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads)); writel(readl(0x30330158) | 0x10, 0x30330158); writel(readl(0x30330160) | 0x10, 0x30330160); writel(readl(0x30330164) | 0x10, 0x30330164); writel(0, 0x30330710); writel(0, 0x30330714); Next, I will proceed with serial initialization and baud rate configuration, using `serial_mx.c` as a reference. However, the UCR2 register will be configured as follows: writel(UCR2_WS | UCR2_TXEN | UCR2_RXEN | UCR2_SRST, &base->cr2); This worked.
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