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FRDM-i.MX95 EVK 的 Ubuntu 安装指南 (Ubuntu 22.04/24.04) 你好, 我目前正在使用FRDM-i.MX95 EVK ,并且想在这个平台上运行Ubuntu(22.04 或 24.04) 。 我找到了以下关于在 i.MX8MP 上安装 Ubuntu 的指南: https://community.nxp.com/t5/i-MX-Processors/How-to-install-ubuntu-on-imx8mp/td-p/1744295 我的问题是: 我可以按照 i.MX8MP 指南中描述的步骤来操作 FRDM-i.MX95 EVK 吗? 是否有官方支持的适用于 i.MX95 的 Ubuntu 镜像或 BSP? 如果不能直接兼容,那么在 i.MX95 上运行 Ubuntu 的推荐方法是什么? (例如,Yocto + Ubuntu rootfs,或任何预构建的映像) 是否存在我应该注意的已知限制或差异(例如,引导加载程序、内核、设备树、GPU/NPU 支持)? 我非常感谢您能提供任何关于在 i.MX95 上运行 Ubuntu 的指导或参考资料。 提前谢谢您。 此致, 杰克 Re: Ubuntu installation guide for FRDM-i.MX95 EVK (Ubuntu 22.04/24.04) 你好@JK-IMX 我们已停止对Ubuntu操作系统的支持。我们现在支持 Debian 操作系统。有关 Debian 系统的信息,请参阅以下链接。 https://www.nxp.com/design/design-center/software/embedded-software/linux-software-and-development-tools/nxp-debian-linux-sdk-distribution-for-i-mx-and-layerscape:NXPDEBIAN BR
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T Embedにはどのようなポートがありますか? 標準モデルのTエンベッドを持っていますが、どのポートか全く分かりません(もう一つのポートで、USB-Cではありません)。公式サイトではGroveポートと書いてあり、LilygoのWikiサイトではQwiicポートと書かれています。どなたか助けていただけませんか? ブートROM|ブート|フラッシュ Re: What kind of port does the T Embed have? こんにちは、 @papaku さん、 T-EmbedはNXP製品ではないため、当社のサポート範囲外かもしれません。ご理解いただきありがとうございます。 BR セレステ
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Best practice for time-deterministic (TAS) traffic when using LLCE + PFE CAN2ETH Hello NXP Team, We are working on a zonal architecture using S32G399A as Zone Controllers connected to HPC Current Architecture: We are currently using the GMAC with full Time-Aware Shaper (TAS / 802.1Qbv) support along with complete TSN features. DDS runs over this GMAC path, and we have good time determinism for our service-oriented traffic. New Exploration: We have successfully brought up and tested the official NXP LLCE + PFE sample application (CAN2ETH / ETH2CAN) as described in AN13423. The goal is to offload selected high-frequency / low-latency CAN signals from ECUs directly via LLCE → PFE (IEEE1722 AVTP over UDP) to reduce CPU load and latency on the Zone Controller. From community discussions, we understand that PFE only supports 802.1AS-Rev (time synchronization) and does not support Time-Aware Shaper (802.1Qbv / TAS) or Frame Preemption, unlike GMAC. Question / Request for Guidance: Since LLCE is tightly integrated with PFE (using PFE_HIF3), what is NXP’s recommended best practice in this scenario? Can we enable TAS support on PFE by using / customizing the PFE source code provided by NXP? (I saw that NXP provides PFE source code – would this help us add or enable TAS functionality?) If TAS cannot be enabled on PFE, what is NXP’s recommended best practice to achieve strong time determinism for the LLCE + PFE CAN2ETH traffic? Should critical time-sensitive CAN signals continue to use the GMAC + TAS path, while only non-critical or high-volume signals use LLCE + PFE? Is the recommended approach to rely on an external TSN switch (such as SJA1110) downstream of the PFE port to provide full TAS scheduling for the tunneled traffic? Are there any plans or firmware updates that will add TAS support on PFE in the future? We want to decide the right split between GMAC and PFE paths without compromising determinism for safety-relevant or hard real-time signals. Any official guidance, reference designs, or configuration recommendations would be very helpful. Thank you in advance! Best regards, Arsal Imam SDV Architect @ GK Automobiltechnologie (Disrupt) GoldVIP Re: Best practice for time-deterministic (TAS) traffic when using LLCE + PFE CAN2ETH Hi,arsalimam Thank you for your contacting and detail information. I have received your questions and will help you to check it. BR Joey Re: Best practice for time-deterministic (TAS) traffic when using LLCE + PFE CAN2ETH Hi,arsalimam Refer to the AUTOSAR_MCAL_ETH_43_PFE_UM.pdf, PFE MCAL driver supports the Time Aware shaper, the shaper can be configured in the EB. Hope this information can help you. BR Joey Re: Best practice for time-deterministic (TAS) traffic when using LLCE + PFE CAN2ETH Hello Joey_z, Thank you for your prompt response and for pointing me to the AUTOSAR_MCAL_ETH_43_PFE_UM.pdf. I appreciate the clarification, we will review the PFE MCAL driver documentation and explore Time-Aware Shaper (TAS / 802.1Qbv) configuration through the EB (Elektrobit) tool. As a quick follow-up question: Does the PFE MCAL driver also support Frame Preemption (IEEE 802.1Qbu / 802.3br)? If yes, could you please share the relevant section in the User Manual or any configuration guidance for enabling it alongside TAS? We are trying to fully understand the TSN feature set available on the PFE path before finalizing the traffic split between GMAC and LLCE+PFE. Thank you again for your support. Best regards Re: Best practice for time-deterministic (TAS) traffic when using LLCE + PFE CAN2ETH Hi,arsalimam As a quick follow-up question: Does the PFE MCAL driver also support Frame Preemption (IEEE 802.1Qbu / 802.3br)? >>>PFE does not support it. BR Joey
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Call SDK flash API and some data in D_Flash missing of S32K144 Hi team:  I call SDK flash init API in my project (S32K144), and then call Flash erase and Flash write. Then I find some data in Flash became to 0xFF. Then I try to add a Delay between Flash init and flash Erase/Write, and then the data is normal. And then I try to check while (!(FTFC->FSTAT & FTFC_FSTAT_CCIF_MASK)); instead of using delay function. But it still failed. So, I wonder if it has to delay some time to wait for the flash module to complete initialization on hardware layer. BR Loky Re: Call SDK flash API and some data in D_Flash missing of S32K144 Hi @Loky, Which driver version are you using? It is not recommended to use the legacy SDK drivers; RTD drivers should be used instead. The Flash_Init function does not modify flash contents. The erase and write functions already poll the CCIF flag internally, so there is no need to poll it in your application code. The behavior you observe may be related to cache or the flash prefetch buffer. Please try disabling them (PCCCR, OCMDR0) and check if the issue persists. Regards, Daniel Re: Call SDK flash API and some data in D_Flash missing of S32K144 Hi Daniel: This is the SDK Flash Driver Version now we are using. My colleague told me that S32K144 only has SDK Flash Driver and no RTD Driver. Could you briefly explain what's wrong with the SDK driver? And could you please share it to me if you have S32K144 RTD driver. I tried to use the methed you mentioned(Disable cache), but it didn't work. I will record some information in flash when power on reset or LVD reset,  and some other data is in the same sector.  I will read all sector data out and update information and rewrite to the sector. But I've had some new discoveries. I found that the data was already 0xFF before reading the flash. If the flash is accidentally powered off while executing erase or write instructions, it will cause the data in the sector to be 0xFF after power on again? I will continue to investigate this issue, maybe it is a bug in my software. BR Loky Re: Call SDK flash API and some data in D_Flash missing of S32K144 Hi @Loky, The SDK is legacy software. NXP now provides RTD drivers, which also include Flash drivers, both the MCAL layer and the low-level IP layer equivalent to the legacy SDK. You can download the RTD package here: https://www.nxp.com/webapp/swlicensing/sso/downloadSoftware.sp?catid=SW32K1-RTD44-D Please ensure that you use a compatible version of S32 Design Studio, as specified in the RTD Release Notes. Did you also disable the prefetch buffers? OCMDR0 – Program Flash prefetch buffer OCMDR1 – Data Flash prefetch buffer If the Flash is unexpectedly powered down while an erase or program operation is in progress, NXP cannot guarantee data integrity. The affected Flash contents become undefined and may contain ECC errors. Consider using the Emulated EEPROM functionality. It is optimized for this purpose. Please refer to AN11983 – Using the S32K1xx EEPROM Functionality https://www.nxp.com/docs/en/application-note/AN11983.pdf Chapter 5 S32K1xx brownout detection Chapter 6 S32K1xx new quick write mode Regards, Daniel Re: Call SDK flash API and some data in D_Flash missing of S32K144 Hi Daniel: Thanks for your RTD package, I'll check it tomorrow. I haven't tried to disable prefetch buffers yet. Do you mean I should disable both cache and prefetch before erase and write flash? I'll try it also. Yes, I did come across an uncorrectable ECC and it triggered Hardfault today. Except erasing this sector again after powering on the device, is there any way to fix this ECC issue? I think this way is not applicable to my current software design. Thank you for your suggestion. I will discuss the Emulated EEPROM with my colleagues. BR Loky Re: Call SDK flash API and some data in D_Flash missing of S32K144 Hi Daniel: I'm glad to tell you we have found the root cause, because the VCC-5v is unstable during power down and MCU reset at low voltage repeatedly, resulting in the software erasing flash during initialization but not writing flash. BR Loky
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T Embed 使用的是哪种接口? 我有一台标准的 T 型嵌入式开发板,但我不知道它用的是哪种接口(不是 USB-C 接口),因为官方网站说它是 Grove 接口,而 Lilygo Wiki 网站说它是 Qwiic 接口。请问有人可以帮帮我吗? 启动 ROM | 启动配置 | 闪存 Re: What kind of port does the T Embed have? 你好@papaku , T-Embed 不是 NXP 的产品,因此这可能超出我们的支持范围。感谢您的理解。 BR 塞莱斯特
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S32k388 启动 ROM 参考手册中提到了启动 ROM,但没有提供更多信息。 RM 只是说有五个 32kb 的启动 ROM 实例可用。 启动ROM何时变得重要?是否有固件可以在 sbaf 运行之前,由 HSE 从此处运行? Re: S32k388 Boot ROM 嗨@Ars_ , 启动由 sBAF 管理,而 sBAF 实际上是内部 FLASH 中的代码。这些启动 ROM 部分供 HSE 使用。 从内部讨论来看,有人要求修改描述,我会跟进这个帖子,看看什么时候能进行修改。 此致, 朱利安
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使用 LLCE + PFE CAN2ETH 时,时间确定性 (TAS) 流量的最佳实践 您好,NXP团队, 我们正在开发一种基于S32G399A的区域架构,该架构使用S32G399A作为区域控制器,并连接到高性能计算(HPC)。 当前架构: 我们目前使用的是具有完整时间感知整形器 (TAS / 802.1Qbv) 支持以及完整 TSN 功能的 GMAC。 DDS 通过此 GMAC 路径运行,我们的面向服务的流量具有良好的时间确定性。 新的探索: 我们已经成功启动并测试了 AN13423 中描述的 NXP LLCE + PFE 官方示例应用程序 (CAN2ETH / ETH2CAN)。 目标是通过 LLCE → PFE(基于 UDP 的 IEEE1722 AVTP)直接从 ECU 卸载选定的高频/低延迟 CAN 信号,以降低区域控制器的 CPU 负载和延迟。 从社区讨论中我们了解到,PFE 仅支持 802.1AS-Rev(时间同步),不支持时间感知整形器 (802.1Qbv / TAS) 或帧抢占,这与 GMAC 不同。 问题/咨询请求: 由于 LLCE 与 PFE 紧密集成(使用 PFE_HIF3),在这种情况下,NXP 推荐的最佳实践是什么? 我们能否通过使用/定制NXP提供的PFE源代码,在PFE上启用TAS支持?(我看到NXP提供了PFE源代码——这是否能帮助我们添加或启用TAS功能?) 如果 PFE 上无法启用 TAS,NXP 推荐的最佳实践是什么,才能实现 LLCE + PFE CAN2ETH 流量的强时间确定性? 对于关键的、时间敏感的 CAN 信号,是否应该继续使用 GMAC + TAS 路径,而对于非关键的或大容量的信号,是否应该使用 LLCE + PFE? 推荐的做法是依靠 PFE 端口下游的外部 TSN 交换机(例如 SJA1110)来为隧道流量提供完整的 TAS 调度吗? 未来是否有任何计划或固件更新会在 PFE 上添加 TAS 支持? 我们希望在不损害功能安全相关或硬实时信号的确定性的前提下,确定 GMAC 和 PFE 路径之间的正确划分。 任何官方指南、参考设计或配置建议都将非常有帮助。 提前谢谢! 顺祝商祺! 阿尔萨尔·伊玛目 SDV架构师 @ GK Automobiltechnologie (Disrupt) 金VIP Re: Best practice for time-deterministic (TAS) traffic when using LLCE + PFE CAN2ETH 你好, arsalimam 感谢您与我们联系并提供详细信息。 我已经收到您的问题,我会帮您核实。 BR 乔伊 Re: Best practice for time-deterministic (TAS) traffic when using LLCE + PFE CAN2ETH 你好,arsalimam 请参阅 AUTOSAR_MCAL_ETH_43_PFE_UM.pdf 文件。PFE MCAL 驱动程序支持时间感知整形器,整形器可以在 EB 中进行配置。 希望这些信息对您有所帮助。 BR 乔伊 Re: Best practice for time-deterministic (TAS) traffic when using LLCE + PFE CAN2ETH 你好 Joey_z, 感谢您的及时回复,并向我指出了 AUTOSAR_MCAL_ETH_43_PFE_UM.pdf 文件。感谢您的澄清,我们将查看 PFE MCAL 驱动程序文档,并通过 EB(Elektrobit)工具探索时间感知整形器 (TAS / 802.1Qbv) 配置。 还有一个后续问题:PFE MCAL 驱动程序是否也支持帧抢占(IEEE 802.1Qbu / 802.3br)?如果可以,能否请您分享用户手册中的相关章节或任何关于如何将其与 TAS 结合使用的配置指南? 在最终确定 GMAC 和 LLCE+PFE 之间的流量分配之前,我们正在努力充分了解 PFE 路径上可用的 TSN 功能集。再次感谢您的支持。 顺祝商祺! Re: Best practice for time-deterministic (TAS) traffic when using LLCE + PFE CAN2ETH 你好, arsalimam 还有一个后续问题:PFE MCAL 驱动程序是否也支持帧抢占(IEEE 802.1Qbu / 802.3br)? PFE不支持此功能。 BR 乔伊
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Automotive Brake Status Monitoring Using S32K3 Microcontrollers Overview This article demonstrates how to implement a brake status monitoring system using NXP S32K3 microcontrollers. The solution is based on Application Code Hub examples for S32K344 and S32K312 platforms and showcases how real-time sensor data can be used to detect braking events and trigger visual feedback. This is based on the following Application Code Hub demonstrations: Brake-Control-Monitoring-FRDM-A-S32K312 Brake-Control-Monitoring-FRDM-A-S32K344 The application simulates braking conditions using a sensor input and provides immediate system response via an LED indicator. Such systems are commonly used in automotive environments to improve system awareness and support safety-related functionality. Learning Scope This article covers both practical implementation and core embedded concepts, including: Reading analog signals using ADC Processing real-time signals Controlling outputs using GPIO Implementing decision logic based on thresholds Understanding signal flow in embedded systems System Architecture The application is built around a simple but representative embedded system: Input: Analog sensor (force / brake simulation) Processing: S32K3 microcontroller Output: LED indicator Functional Flow The sensor generates an analog signal proportional to applied force The ADC converts the analog signal into a digital value The software evaluates the value against defined thresholds The system updates the output (LED) based on braking state Brake Monitoring Application ArchitectureBrake Monitoring Application Architecture Key Concepts Analog Signal Acquisition (ADC) Sensors typically output analog values that must be digitized for processing. The ADC periodically samples this signal and produces a digital representation used by the application logic. Typical interpretation: Low value → no braking activity High value → braking detected Real-Time Signal Processing The system continuously reads sensor data and reacts immediately. This is essential in automotive contexts where delayed responses may impact system behavior. Output Control Using GPIO The LED output reflects the system state: OFF → no braking detected ON → braking condition detected In extended implementations, multiple states or patterns can be used. Hardware and Software Setup Required Hardware FRDM-A-S32K3xx development board FRDM-A-S32K312FRDM-A-S32K312 FRDM-A-S32K344FRDM-A-S32K344 Force Click (or similar analog sensor module) Force ClickForce Click 4x4 RGB Click (LED output) 4X4 RGB Click4X4 RGB Click USB cable / power supply The example applications demonstrate how these peripherals are connected to the MCU pins and used to simulate brake inputs and outputs Software Environment S32 Design Studio S32K3 Automotive Software Package Application Code Hub project import Implementation Guide Step 1: Import the Project Open S32 Design Studio Use “Import project from Application Code Hub” Locate the brake monitoring example Import and configure the project Expected result: Project is successfully loaded into the workspace Step 2: Build the Application Compile the project Resolve any dependency issues if needed Expected result: No compilation errors Step 3: Connect Hardware Connect the development board via USB Attach sensor and LED modules Ensure correct pin connections Expected result: Board is powered and detected by the IDE Step 4: Flash and Run Program the MCU Start execution Expected result: Application runs continuously Step 5: Functional Validation Apply pressure to the sensor Observe LED behavior Expected result: LED activates when braking condition is detected Signal Behavior and Threshold Logic The application relies on threshold-based decision logic: If ADC value < threshold → no brake If ADC value ≥ threshold → brake active Placeholder: Signal vs Threshold Diagram Figure: Brake monitoring threshold behavior. The ADC raw value is converted into millivolts using a 0–5000 mV reference range. The converted value is compared against predefined thresholds to progressively activate the green, yellow, orange, and red LED columns.Figure: Brake monitoring threshold behavior. The ADC raw value is converted into millivolts using a 0–5000 mV reference range. The converted value is compared against predefined thresholds to progressively activate the green, yellow, orange, and red LED columns. Troubleshooting Board Not Detected Verify USB cable and drivers Check debugger connection Restart IDE No Output Response Validate GPIO configuration Check LED connections Confirm code execution Incorrect Sensor Readings Verify ADC configuration Inspect sensor wiring Confirm scaling and thresholds Extending the Application The basic implementation can be extended in several ways: Multi-Level Brake Detection Define multiple thresholds: Low → normal Medium → moderate braking High → emergency braking Noise Filtering Apply software filtering to stabilize readings Avoid false triggering from sensor noise Timing-Based Logic Add debounce or delay mechanisms Require sustained input before triggering State Machine Implementation A more advanced approach is to implement a state machine: Idle Braking Emergency Placeholder: State Machine Diagram [IMAGE_PLACEHOLDER: Brake State Machine] States: Idle → Brake → Emergency Transitions based on ADC thresholds Safety Context Although simplified, this application reflects concepts used in automotive safety systems: Continuous monitoring of input signals Immediate response to changes Clear indication of system state In real systems, additional mechanisms are required: Redundancy Fault detection Compliance with safety standards (e.g., ISO 26262) Conclusion This example demonstrates how a simple embedded application can model a real-world automotive use case. By combining ADC input, real-time processing, and GPIO output, it highlights the core principles behind monitoring functions in automotive ECUs. The provided implementation serves as a foundation for more advanced designs, including multi-state logic, filtering techniques, and safety-focused extensions. The course serves as a foundation for the Eat-Sleep-Code-Repeat learning initiative, encouraging a hands-on approach where students continuously learn, develop, test, and improve automotive embedded applications using real hardware and practical examples.
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需要 S32K342 FOTA 引导加载程序架构指南(基于 UART 的更新) 您好,NXP团队, 我们正在为 S32K342 开发定制的固件空中升级 (FOTA) 解决方案,希望获得有关推荐的闪存架构和启动流程的指导。 MCU详情 设备:S32K342 PFlash:2 MB 银行 0:1 MB 银行 1:1 MB DFlash:128 KB 当前状态 我们使用UART作为固件更新接口。 目前为止,我们已成功做到: 通过 UART 接收固件(.bin 文件)。 将完整的二进制文件存储到闪存中 确认接收到的图像已正确存储。 我们剩下的挑战是实现引导加载程序架构和应用程序切换机制。 我们希望就以下问题获得澄清: 1. 推荐的FOTA Flash布局 对于 S32K342 双镜像 FOTA 实现,推荐的内存布局是什么? 具体来说,我们想知道以下方面的推荐地点: 引导加载程序 应用插槽 A 应用插槽 B 元数据/启动标志 版本信息 CRC 回滚信息 提供一份包含地址的内存映射示例将非常有帮助。 2. 推荐的启动流程 请问有人能解释一下NXP推荐的完整启动顺序吗? 例如: 重置 引导加载程序启动 检查启动标志 选择活动应用程序 验证图像(CRC/签名) 跳转到应用程序 我们希望能得到流程图或对整个流程的解释。 3. 从引导加载程序跳转到应用程序 对于 S32K342,标准的 Cortex-M7 跳转序列是否足够? 例如: 从应用程序基地址读取 MSP 从基数 + 4 读取 Reset_Handler 设置 MSP 更新 VTOR 跳转到 Reset_Handler 在转移控制权之前,是否有任何 S32K342 特有的要求或初始化步骤? 4. 双应用图像 如果应用 A 和应用 B 位于不同的闪存地址: 每个应用程序都应该有自己的链接脚本吗? 或者,NXP 是否有推荐的构建双槽应用的方法? 5. 闪存库的使用 由于 S32K342 有两个 1 MB 的 PFlash 存储区: 推荐的方法是否是: 从 Bank 0 执行引导加载程序 将新固件编程到 Bank 1 中。 验证成功后切换执行 两个 PFlash 存储体之间是否存在读写限制或擦除/编程限制? 6. 元数据存储 理想的存储地点在哪里? 活动图像标志 图像有效性 Firmware version CRC 回滚状态 这些物品应该存放在: 保留 PFlash DFlash 另一个专用的区域? 7. 基于UART的FOTA 由于我们的更新接口是 UART,我们想知道推荐的工作流程。 以下流程是否正确? 个人电脑 │ UART │ 引导加载程序接收 .bin 文件 │ 将固件存储到非活动闪存插槽中 │ 验证CRC │ 更新启动元数据 │ RESET MCU │ 引导加载程序选择新映像 │ 跳转至应用程序 或者恩智浦是否推荐其他方法? 8. AB_SWAP 与自定义引导加载程序 对于 S32K342 的生产 FOTA 而言,HSE AB_SWAP 是否是强制性的? 或者,具有双应用程序插槽的完全自定义引导加载程序也是一种受支持且常用的架构吗? 如果您有任何专门介绍 S32K342 FOTA、UART 固件更新或双映像引导加载程序的应用笔记、参考项目、引导加载程序示例或文档,我们将非常感谢您提供这些参考资料。 感谢您的支持。 S32K3 S32DS-ARM Re: S32K342 FOTA Bootloader Architecture Guidance Required (UART-Based Update) 你好@bavinkumar_02 1.对于 S32K342,AB_SWAP 只有一种可能的设置。参见“3.5.3.2HSE固件参考手册中提供了“AB_SWAP”模式下闪存布局的图示,该手册可从“文档”->“安全文件”下载: https://www.nxp.com/products/S32K3 就您的情况而言,最方便、最常见的布局是: 必须安装 AB_SWAP 版本的 HSE 固件(交换是 HSE 的一项功能,没有 HSE 固件就无法执行此操作)。固件已安装到两个分区,并且如图所示,它占用了两个分区中最后的 176KB。 因为整个数据块都被交换了,所以两个数据块中必须有完全相同的引导加载程序副本。其余部分分配给申请。 代码始终从活动块运行,因此引导加载程序和所有应用程序都是针对活动块中的地址编译的。 当引导加载程序更新应用程序时,它会将应用程序编程为被动阻塞,因此在闪存编程期间不会出现边读边写的问题。应用程序编程完成后,即可触发 HSE_SRV_ID_ACTIVATE_PASSIVE_BLOCK HSE 服务。下次RESET后,分区将被交换,引导加载程序将像往常一样跳转到应用程序(跳转到当前活动块中的新应用程序)。 2. 流程取决于应用程序。在现代汽车应用中,简单的基于 CRC 的验证已不再被认为足够。软件的完整性和真实性通常通过安全启动机制来保证。在 S32K3 设备上,这是由硬件网络安全引擎 (HSE) 处理的,它会执行加密验证(例如)。基于签名)在启动过程中自主进行。预计量产汽车系统将利用这些硬件支持的网络安全功能,而不是仅仅依赖 CRC 验证。 我们提供安全启动应用笔记,其中包括演示项目。可从以下网址下载: https://www.nxp.com/products/S32K3 应用笔记请点击此处查看: 文档 -> 安全文件 -> 安全启动应用笔记 v0.1.1.0(AN744511) 相关演示项目可在此处下载: 设计资源 -> 软件 -> 安全文件 -> SecureBootAppNoteDemo (SW745310) 您可以在 HSE 演示示例中找到其他安全启动示例: https://www.nxp.com/webapp/Download?colCode=S32K3_HSE_DemoExamples 三种模式——高级安全启动、基本安全启动和 SHE 安全启动——都有相应的示例。建议启用高级安全启动。 请参阅所有项目中包含的 Readme.md 文件。 3. 是的,这是标准的跳转序列。强烈建议在跳转之前取消初始化引导加载程序初始化的所有资源。 4. 如上所述,代码始终从活动分区执行,因此应用程序始终使用相同的链接器文件。 5. 前面已经讨论过了。 6.这取决于用户。您可以将数据存储在应用程序映像后面,或者存储在数据闪存中。 7. 对于生产汽车用例而言,从数据传输的角度来看,所提出的流程总体上是正确的,但正如前面提到的,我不建议依赖 CRC 作为主要的验证机制。 在汽车应用中,接收到的图像通常会受到加密保护——例如,图像可能会被加密,并且其真实性/完整性会通过数字签名(而不仅仅是 CRC)来验证。 此外,在使用 HSE AB_SWAP 机制时,引导加载程序在 RESET 后不会简单地通过软件元数据选择新映像。新映像被编程到被动分区并成功验证后,应用程序/引导加载程序应调用 HSE 服务 HSE_SRV_ID_ACTIVATE_PASSIVE_BLOCK。这将激活被动块,因此RESET后设备将从新激活的分区启动。 8. HSE AB_SWAP 并非严格强制要求,但对于 S32K342 上的量产汽车 FOTA 解决方案,强烈建议使用。 如果没有 HSE 就实施 FOTA,那就意味着您没有利用 S32K3 平台的一个关键优势。这些设备的主要优点是内置支持 HSE 处理的 A/B 交换(分区重映射)。如果没有它,引导加载程序就必须手动管理一切。 具体而言,不包括 HSE AB_SWAP: 你需要自己实现一种机制来选择 A/B 图像。 您需要仔细管理地址空间,并将每个应用程序链接到不同的固定位置。 图像之间的切换不会由硬件自动处理,而完全由您的软件处理。 除了 HSE AB 交换功能之外,没有其他硬件支持的重映射机制可用。 此外,您还将失去与 AB_SWAP 集成的安全启动的简洁性和稳健性。借助 HSE,图像激活、验证和分区之间的切换以更加可控和高效的方式进行处理,符合汽车网络安全要求。 总之,虽然不考虑 HSE 也能做到这一点,但这会大大增加复杂性,并消除该平台的关键优势。 您可以查看“S32K3XX HSE 和 OTA 高级培训 [TR744101]”,该培训文档可从以下链接下载:文档 -> 安全文件: https://www.nxp.com/products/S32K3 问候, 卢卡斯
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ウィンボンドW664GG6RB-06用IMX-8M-MINI DDRコントローラのタイミング こんにちは、 DDR4タイミングセットが正常に動作しない理由について説明を求めています。簡単に言えば、 DDRツールによって生成されたタイミングは校正および応力試験に合格しましたが、 断続的なLinuxカーネルは起動時にクラッシュし、「未定義命令」エラーが発生します。 設定(生の事実): - SoCはi.MX8M Mini Solo(シングルCortex-A53)、DDR4(Winbond W664GG6RB-06)です。 1200 MHz(DDR4-2400)は1:2 DFI(DDR PHYインターフェース)周波数比モードで、 単一のx16 4 Gbデバイス(512MB、ECCなし)。 - BSPはNXP L4.14.98_2.0.0(Linux 4.14.98、U-Boot 2018.03);DDRの設定は Mscale DDR Tool v3.31(Windows版)とPHYトレーニングファームウェアで生成 v201709。同じファームウェアがYoctoでU-Bootイメージの構築に使われています。 - 3つの交換可能な4Gb x16 DDR4メモリに対して、共通のタイミングセットを1つ認定しています。 部品(Alliance AS4C256M16D4、ISSI IS43QR16256B、Winbond W664GG6RB-06)はすべて動作しています 1200MHzで。 - 最も遅い部分 (Winbond) の tRCD/tRP/tAA (2400 bin で約 14.16 ns) を満たすために、 CL=17 (17-17-17) を設定すると、ツールはそれを MR0 = 0x0864 とエンコードし、対応する CL由来レジスタ(例:DFITMG0 = 0x038C8207、DRAMTMG2 = 0x0609050D)。 - DRAMは2400設定値で静的動作(デバイス内でDVFS/バス周波数が無効化) そのため、Linuxによる実行時の周波数スケーリングはありません。 観察結果: - 17-17-17構成は、DDRツールのストレステスト(約24時間)とU-Bootのmtest(約1時間)に合格します。 エラーなし。 - Linux上(シェルプロンプトに到達した起動時)ではstressapptest +にも合格します fio(CRC32C認証済み)は、Tj = 84°Cの温度で1時間以上連続かつ一定温度で、 データエラーはゼロです。 - それにもかかわらず、Linuxは起動時に「内部エラー: 未定義命令」(破損したカーネルの.text)、カーネル開始から約1.1秒後、 コールドブートの5~7%(自動コールド電源サイクルループで測定)。 - 故障はダイに依存しない:CL=17の画像も1秒間で同じ方法でクラッシュします これらの部分(ISSI)を使い、CL=16イメージは同じISSI上でLinuxを安定して起動します パート。 - 両方のeven-CL構成がLinuxを安定して起動します:16-16-16(当社の長年にわたる本番環境) タイミング)および新たに構築された18-18-18(カーネルクラッシュは見られません)—ただし、奇数CLのみです。 17-17-17は失敗。 - CL由来のレジスタのみが失敗設定と動作設定(MR0)で異なります CASビット、DFITMG0 dfi_t_rddata_en、DRAMTMG2リードレイテンシ/rd2wr、DFITMG2 rdcslat、 ODTCFG rd_odt_delay)。 仮説: 1:2のDFI比率での奇数CASレイテンシが根本原因、すなわち読み取りデータ(リードデータ)にあると推測しています 返還レイテンシはDFIクロックでCL/2であり、CL=17の場合は整数8.5、整数8.0は非整数です / 9.0 で CL=16 / 18。読み取りFIFO(DQSが書き、コントローラが読み取り)以降 クロック(リファレンス・マニュアル§9.3.2.2.2)は定常状態と定常応力を扱います 通過し、エッジ性は読み取りバースト間遷移で表面が現れると推測します。ここで 奇数CLの半DFIクロックオフセットは、RMが直面しない初拍・最後のビートのエッジCASEに当てはまります 記録を残す。 質問: CASレイテンシは奇数です(例:CL=17) は、1:2 DFI の i.MX8M Mini DDR4 PHY でサポートされています。 モード、または奇数CLに関する既知の制約/エラーはありますか?特にDDRは ツールは独自のストレステストを通過するが限界的な奇数CL構成を生成する 実際のブートトラフィックの下で、読書を制限する推奨方法はありますか? 奇数のCLのバースト・トゥ・バーストタイミングは? 添付ファイル:カーネルクラッシュコンソールダンプ、CL=17 .dsDDRツールのスクリプト、および ddr4_timing.c が生成されました。 どんなアドバイスでもありがたいです。 Re: IMX-8M-MINI DDR Controller timings for Winbond W664GG6RB-06 申し訳ありませんが、何らかの理由で添付ファイルが添付されませんでした。それらは以下の通りです。 Re: IMX-8M-MINI DDR Controller timings for Winbond W664GG6RB-06 以下の部品のタイミングパラメータで、CASレイテンシのtRCD(ns)tRP(ns)を確認してください。 Alliance AS4C256M16D4 DDR4-2400 17 14.1614.16 ISSI IS43QR16256B 2400Mbps 16-16-16 (-083R) ウィンボンド W664GG6RB-06 DDR4-2400 17-17-17 IS43QR16256Bの3番目のパラメータは異なります。そのため、3つのパーツごとに専用の設定が必要になるかもしれませんが、3つのパーツすべてに1つの設定を使うのではなく。問題は起動時のみ発生するようですね? Re: IMX-8M-MINI DDR Controller timings for Winbond W664GG6RB-06 こんにちは、 CL=17からCL=18に修正して再試し、DDRテストを実行し、Linuxを再度テストしてください。新しいバージョンへのアップグレードをおすすめします。
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MCXA153:LPSPI 数据突发传输。 你好, 参考手册 MCXA153 包含了对 TDBRn 和 RDBRn LPSPI 寄存器的描述: “TDBRn 和 RDBRn 寄存器支持向发送 FIFO 发送数据进行突发传输,以便与 DMA 控制器一起使用”。 请问有人可以分享一下使用这些寄存器进行突发传输的示例代码吗? 此致 博格丹 通信与控制(I3C | I2C | SPI | FlexCAN | 以太网 | FlexIO) MCXA Re: MCXA153: LPSPI data burst transfer. 嗨@bogdan_u 抱歉,目前没有相关示例。 我找到的最接近的 MCXA153 示例使用 LPSPI_MasterTransferEDMALite() 和 eDMA,但驱动程序通过 LPSPI_GetTxRegisterAddress() / LPSPI_GetRxRegisterAddress() 来定位 TDR/RDR,而不是突发别名窗口。 但我认为你可以尝试使用。 typedef struct { uint32_t cmd; uint32_t data[128]; } lpspi_burst_tx_t; static inline uint32_t LPSPI_TCBR_Address(LPSPI_Type *base) { return ((uint32_t)base + LPSPI_TCBR_OFFSET); } static inline uint32_t LPSPI_TDBR0_Address(LPSPI_Type *base) { return ((uint32_t)base + LPSPI_TDBR0_OFFSET); } static inline uint32_t LPSPI_RDBR0_Address(LPSPI_Type *base) { return ((uint32_t)base + LPSPI_RDBR0_OFFSET); } void LPSPI_StartTxBurstDMA(LPSPI_Type *base, edma_handle_t *txDmaHandle, uint32_t *cmd_plus_data, uint32_t nwords) { edma_transfer_config_t cfg = {0}; cfg.srcAddr = (uint32_t)&cmd_plus_data[0]; cfg.destAddr = LPSPI_TCBR_Address(base); cfg.srcOffset = 4; cfg.destOffset = 4; cfg.srcTransferSize = kEDMA_TransferSize4Bytes; cfg.destTransferSize = kEDMA_TransferSize4Bytes; cfg.minorLoopBytes = 4; cfg.majorLoopCounts = nwords + 1u; EDMA_ResetChannel(txDmaHandle->base, txDmaHandle->channel); EDMA_SetTransferConfig(txDmaHandle->base, txDmaHandle->channel, &cfg, NULL); EDMA_StartTransfer(txDmaHandle); LPSPI_EnableDMA(base, kLPSPI_TxDmaEnable); } void LPSPI_StartRxBurstDMA(LPSPI_Type *base, edma_handle_t *rxDmaHandle, uint32_t *rx_words, uint32_t nwords) { edma_transfer_config_t cfg = {0}; cfg.srcAddr = LPSPI_RDBR0_Address(base); cfg.destAddr = (uint32_t)&rx_words[0]; cfg.srcOffset = 4; cfg.destOffset = 4; cfg.srcTransferSize = kEDMA_TransferSize4Bytes; cfg.destTransferSize = kEDMA_TransferSize4Bytes; cfg.minorLoopBytes = 4; cfg.majorLoopCounts = nwords; EDMA_ResetChannel(rxDmaHandle->base, rxDmaHandle->channel); EDMA_SetTransferConfig(rxDmaHandle->base, rxDmaHandle->channel, &cfg, NULL); EDMA_StartTransfer(rxDmaHandle); LPSPI_EnableDMA(base, kLPSPI_RxDmaEnable); } BR 哈里
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S32K358 + FS2633:MCUを組み立てた状態でRSTBは低(LOW)のままですが、JTAGがコネクテッド時は高くなります 私はFS2633とS32K358を使用しています。FS2633セクション(MCUを取り外した部分)だけをテストすると、RSTBが解放され(HIGH)、3.3Vレールが存在します。 MCUとすべてのコンポーネントを組み立てた後、 RSTBはLOWのままで、MCUは起動しません。 JTAGデバッガを接続するとRSTBが高負荷になり、MCUを正常にプログラムでき、アプリケーションは通常通り動作します。しかし、JTAGを切断すると RSTBが再び低くなり 、MCUが停止します。 一つ気づいた点として、FS2633のRSTB出力は3.3Vの信号であるのに対し、私の基板ではS32K358のRESETラインは5Vにプルアップされている。この電圧差にもかかわらず、JTAGデバッガが接続されている間は正しく動作します。このリセット電圧レベルやデバッガーがリセットや電源オンの流れに影響を与えている可能性はありますか? この問題は、電源オンシーケンス、リセットタイミング、FS2633の起動設定、あるいはデバッガ関連の挙動に関連している可能性はありますか?同様の問題を経験された方、またはデバッグに関するご提案をお持ちの方はいらっしゃいますか? Re: S32K358 + FS2633: RSTB stays LOW with MCU assembled, but goes HIGH when JTAG is connected FS2633 RSTBを3.3Vにプルアップしてテストしてみて、この問題が解決するかどうか確認した方が良いでしょう。
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Regarding the CAN issue of s32k344 The compiler I am currently using is s32ds3.4, RTD2.0.0. Among them, CAN FD function is enabled for can0-can5, and ENABLE RX FIFO function is enabled for can0. The implemented function is that can1 sends 64bit data to can0, can4 sends 64bit data to can2, and can3 sends 64bit data to can5. However, why can can0 and can5 receive data normally but can2 cannot receive data? When I set can4 to Loop-back mode, can4 can also receive data normally. The hardware connection is achieved by connecting CANH of can1 to CANH of can0, CANL of can1 to CANL of can0, CANH of can4 to CANH of can2, CANL of can4 to CANL of can2, CANH of can5 to CANH of can3, and CANL of can5 to CANL of can3 using DuPont wires. Here is my code 回复: Regarding the CAN issue of s32k344 I found a problem. The pin configuration is incorrect
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MCXA265VPNレイアウト案 NXPチーム、 MCXA265VPNのファンアウトの例はありますか?パッドと穴のサイズに関する推奨事項が必要です。ビアはパッド内ですか、それともピン間ですか? BGAでしっかりしたGND機が必要ですか? 助けてください。 ダン・ロジャースさん、ありがとう。 ボード設計
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MCXA153:LPSPIデータバースト転送。 こんにちは、 リファレンス・マニュアルMCXA153 TDBRnおよびRDBRn LPSPIレジスタの説明が含まれています。 「TDBRnおよびRDBRnレジスタは、DMAコントローラで使用するための送信FIFOへのバースト転送をサポートします」。 これらのレジスタを使ったバースト転送のサンプルコードを誰か共有してもらえますか? よろしくお願いします ボグダン 通信・制御(I3C |I2C |SPI |FlexCAN |イーサネット |FlexIO) MCXA Re: MCXA153: LPSPI data burst transfer. こんにちは、 @bogdan_u 申し訳ありませんが、現在、関連する事例はございません。 私が見つけた最も近い例はMCXA153 LPSPI_MasterTransferEDMALite()とeDMAを使っていますが、ドライバーはTDR/RDRをLPSPI_GetTxRegisterAddress() / LPSPI_GetRxRegisterAddress()経由でターゲットにしており、バーストエイリアスウィンドウではありません。 でも、試してみることはできると思います。 typedef struct { uint32_t cmd; uint32_t data[128]; } lpspi_burst_tx_t; static inline uint32_t LPSPI_TCBR_Address(LPSPI_Type *base) { return ((uint32_t)base + LPSPI_TCBR_OFFSET); } static inline uint32_t LPSPI_TDBR0_Address(LPSPI_Type *base) { return ((uint32_t)base + LPSPI_TDBR0_OFFSET); } static inline uint32_t LPSPI_RDBR0_Address(LPSPI_Type *base) { return ((uint32_t)base + LPSPI_RDBR0_OFFSET); } void LPSPI_StartTxBurstDMA(LPSPI_Type *base, edma_handle_t *txDmaHandle, uint32_t *cmd_plus_data, uint32_t nwords) { edma_transfer_config_t cfg = {0}; cfg.srcAddr = (uint32_t)&cmd_plus_data[0]; cfg.destAddr = LPSPI_TCBR_Address(base); cfg.srcOffset = 4; cfg.destOffset = 4; cfg.srcTransferSize = kEDMA_TransferSize4Bytes; cfg.destTransferSize = kEDMA_TransferSize4Bytes; cfg.minorLoopBytes = 4; cfg.majorLoopCounts = nwords + 1u; EDMA_ResetChannel(txDmaHandle->base, txDmaHandle->channel); EDMA_SetTransferConfig(txDmaHandle->base, txDmaHandle->channel, &cfg, NULL); EDMA_StartTransfer(txDmaHandle); LPSPI_EnableDMA(base, kLPSPI_TxDmaEnable); } void LPSPI_StartRxBurstDMA(LPSPI_Type *base, edma_handle_t *rxDmaHandle, uint32_t *rx_words, uint32_t nwords) { edma_transfer_config_t cfg = {0}; cfg.srcAddr = LPSPI_RDBR0_Address(base); cfg.destAddr = (uint32_t)&rx_words[0]; cfg.srcOffset = 4; cfg.destOffset = 4; cfg.srcTransferSize = kEDMA_TransferSize4Bytes; cfg.destTransferSize = kEDMA_TransferSize4Bytes; cfg.minorLoopBytes = 4; cfg.majorLoopCounts = nwords; EDMA_ResetChannel(rxDmaHandle->base, rxDmaHandle->channel); EDMA_SetTransferConfig(rxDmaHandle->base, rxDmaHandle->channel, &cfg, NULL); EDMA_StartTransfer(rxDmaHandle); LPSPI_EnableDMA(base, kLPSPI_RxDmaEnable); } BR ハリー
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关于 s32k344 的 CAN 问题 我目前使用的编译器是s32ds3.4,RTD2.0.0。其中,CAN FD 功能对 can0-can5 启用,ENABLE RX FIFO 功能对 can0 启用。实现的功能是:can1 向 can0 发送 64 位数据,can4 向 can2 发送 64 位数据,can3 向 can5 发送 64 位数据。但是,为什么 can0 和 can5 可以正常接收数据,而 can2 却无法接收数据?当我将 can4 设置为环回模式时,can4 也能正常接收数据。硬件连接是通过使用杜邦线将 can1 的 CANH 连接到 can0 的 CANH,将 can1 的 CANL 连接到 can0 的 CANL,将 can4 的 CANH 连接到 can2 的 CANH,将 can4 的 CANL 连接到 can2 的 CANL,将 can5 的 CANH 连接到 can3 的 CANH,以及将 can5 的 CANL 连接到 can3 的 CANL 来实现的。这是我的代码 回复: Regarding the CAN issue of s32k344 我发现了一个问题。引脚配置错误
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MCXA265VPN布局建议 NXP团队 您有MCXA265VPN扇出示例吗?需要根据垫片和孔径尺寸进行推荐。过孔是在焊盘内还是引脚之间?BGA下方是否需要完整的接地层? 请帮忙。 谢谢丹·罗杰斯 电路板设计
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MCXA265VPN Layout Suggestion NXP Team, Do you have a MCXA265VPN fanout example?  Need recommended via pad and hole size.  Are the vias in pads or between pins?  Need to have a solid GND plane under BGA? Please help. Thanks Dan Rogers Board Design
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S32k344のCAN問題について 現在使用しているコンパイラはs32ds3.4です。RTD2.0.0その中で、can0-can5ではCAN FD機能が有効、can0ではENABLE RX FIFO機能が有効です。実装された機能は、can1がcan0に64ビットのデータを送信し、can4がcan2に64ビットのデータを送信し、can3がcan5に64ビットのデータを送信するというものです。しかし、なぜcan0とcan5は通常データを受け取れるのにcan2はデータを受け取れないのでしょうか?can4をループバックモードに設定すると、can4は通常通りデータを受け取ることができます。ハードウェア接続は、デュポンワイヤを使用して、can1のCANHとcan0のCANH、can1のCANLとcan0のCANL、can4のCANHとcan2のCANH、can4のCANLとcan2のCANL、can5のCANHとcan3のCANH、can5のCANLとcan3のCANLを接続することによって実現されます。これが私のコードです 回复: Regarding the CAN issue of s32k344 問題点を見つけました。ピン配置が間違っています
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S32K342 FOTA Bootloader Architecture Guidance Required (UART-Based Update) Hello NXP Team, We are developing a custom Firmware Over-The-Air (FOTA) solution for the S32K342 and would like guidance on the recommended flash architecture and boot flow. MCU Details Device: S32K342 PFlash: 2 MB Bank 0: 1 MB Bank 1: 1 MB DFlash: 128 KB Current Status We are using UART as the firmware update interface. So far, we have successfully: Receive the firmware (.bin) over UART Store the complete binary into flash memory Verify that the received image is stored correctly Our remaining challenge is implementing the bootloader architecture and application switching mechanism. We would like clarification on the following: 1. Recommended FOTA Flash Layout What is the recommended memory layout for an S32K342 dual-image FOTA implementation? Specifically, we would like to know the recommended locations for: Bootloader Application Slot A Application Slot B Metadata / Boot flags Version information CRC Rollback information An example memory map with addresses would be extremely helpful. 2. Recommended Boot Flow Could someone explain the complete boot sequence recommended by NXP? For example: Reset Bootloader starts Check boot flags Select active application Validate image (CRC/signature) Jump to application We would appreciate a flow diagram or explanation of the complete process. 3. Bootloader to Application Jump For S32K342, is the standard Cortex-M7 jump sequence sufficient? For example: Read MSP from application base address Read Reset_Handler from base + 4 Set MSP Update VTOR Jump to Reset_Handler Are there any S32K342-specific requirements or initialization steps before transferring control? 4. Dual Application Images If App A and App B are located at different flash addresses: Should each application have its own linker script? Or is there a recommended NXP approach for building dual-slot applications? 5. Flash Bank Usage Since S32K342 has two 1 MB PFlash banks: Is the recommended approach to: Execute the bootloader from Bank 0 Program the new firmware into Bank 1 Switch execution after successful verification Are there any Read-While-Write or erase/programming restrictions between the two PFlash banks? 6. Metadata Storage Where is the preferred location to store: Active image flag Image validity Firmware version CRC Rollback status Should these be stored in: Reserved PFlash DFlash Another dedicated region? 7. UART-Based FOTA Since our update interface is UART, we would like to know the recommended workflow. Is the following flow correct? PC │ UART │ Bootloader receives .bin │ Store firmware into inactive flash slot │ Verify CRC │ Update boot metadata │ Reset MCU │ Bootloader selects new image │ Jump to application Or does NXP recommend a different approach? 8. AB_SWAP vs Custom Bootloader Is HSE AB_SWAP mandatory for production FOTA on S32K342? Or is a fully custom bootloader with dual application slots also a supported and commonly used architecture? If there are any application notes, reference projects, bootloader examples, or documentation specifically covering S32K342 FOTA, UART firmware updates, or dual-image bootloaders, we would greatly appreciate the references. Thank you for your support. S32K3 S32DS-ARM  Re: S32K342 FOTA Bootloader Architecture Guidance Required (UART-Based Update) Hi @bavinkumar_02  1. In case of S32K342, there’s only one possible setup for AB_SWAP. See “3.5.3.2 Illustrations of Flash memory layout in AB_SWAP” in HSE Firmware reference manual which can be downloaded from Documentation -> Secure files: https://www.nxp.com/products/S32K3 In your case, the most convenient and most common layout is: It’s necessary to install AB_SWAP version of HSE firmware (the swap is a feature of HSE, it’s not possible to do that without HSE firmware). The firmware is installed to both partitions and it occupies last 176KB in both blocks as shown on the picture. Because whole blocks are swapped, it’s necessary to have exact copy of the bootloader in both blocks. The rest is allocated for applications. The code is always running from active block, so the bootloader and all applications are compiled for addresses in active block. When bootloader updates an application, it programs the application to passive block, so there’s no problem with read-while-write issues during flash programming. Once the application is programmed, you can trigger HSE_SRV_ID_ACTIVATE_PASSIVE_BLOCK HSE service. After next reset, the partitions will be swapped and bootloader will jump to application as usual (to new application which is in active block now). 2. The flow is application dependent. In modern automotive applications, simple CRC-based validation is no longer considered sufficient. Integrity and authenticity of the software are typically ensured using Secure Boot mechanisms. On S32K3 devices, this is handled by the Hardware Security Engine (HSE), which performs cryptographic verification (e.g. signature-based) autonomously during boot. Production automotive systems are expected to leverage these hardware-backed security features rather than relying on CRC-only validation. We provide Secure Boot application note including demo projects. It can be downloaded from: https://www.nxp.com/products/S32K3 Application note can be found here: Documentation -> Secure Files -> Secure Boot Application note v0.1.1.0 (AN744511) Associated demo project can be downloaded here: Design Resources -> Software -> Secure Files -> SecureBootAppNoteDemo (SW745310) Other examples for secure boot can be found in HSE Demo Examples: https://www.nxp.com/webapp/Download?colCode=S32K3_HSE_DemoExamples There are examples for all three modes – advanced secure boot, basic secure boot and SHE secure boot. Advanced secure boot is recommended. See Readme.md file which is included in all projects. 3. Yes, that’s standard jump sequence. It’s just highly recommended to de-initialize all resources initialized by bootloader before the jump. 4. As mentioned above, the code is always executed from active partition, so the application always uses the same linker file. 5. Already discussed above. 6. This is up to user. You can store the data behind the application image or to data flash. 7. For a production automotive use case, the proposed flow is generally correct from the data-transfer point of view, but as already mentioned, I would not recommend relying on CRC as the main validation mechanism. In automotive applications, the received image is typically protected cryptographically - for example, the image may be encrypted and its authenticity/integrity is verified using a digital signature, not only by CRC. Also, when using the HSE AB_SWAP mechanism, the bootloader does not simply select the new image by software metadata after reset. After the new image is programmed into the passive partition and successfully verified, the application/bootloader should call the HSE service HSE_SRV_ID_ACTIVATE_PASSIVE_BLOCK. This activates the passive block, so after reset the device boots from the newly activated partition. 8. HSE AB_SWAP is not strictly mandatory, but for a production automotive FOTA solution on S32K342 it is strongly recommended. Implementing FOTA without HSE would mean you are not leveraging one of the key advantages of the S32K3 platform. The main benefit of these devices is the built-in support for A/B swap (partition remapping) handled by HSE. Without it, the bootloader would have to manage everything manually. Specifically, without HSE AB_SWAP: You would need to implement your own mechanism for selecting between A/B images You would have to carefully manage the address space and link each application to different fixed locations The swap between images would not be handled autonomously by the hardware, but entirely in your software There is no alternative hardware-supported remapping mechanism available outside of HSE AB swap feature In addition, you would lose the simplicity and robustness of Secure Boot integrated with AB_SWAP. With HSE, image activation, validation, and switching between partitions are handled in a much more controlled and efficient way, aligned with automotive security requirements. In summary, doing this without HSE is possible, but it significantly increases complexity and removes key benefits of the platform. You can take a look at “S32K3XX HSE and OTA Advance Training [TR744101]” which can be downloaded Documentation -> Secure files: https://www.nxp.com/products/S32K3 Regards, Lukas
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