LPC55S28 ISP_CMD_EN not disabling ISP commands Hello, I have an LPC55S28 MCU with the attached CMPA and CFPA settings. I got these value directly from reading via blhost via python with the commands below. So these came directly from the actual MCU. This was after a full power cycle of the MCU. CMPA read via USB. uv run python -m spsdk.apps.blhost -u 0x3972,0x3333 read-memory 0x0009E400 512 -f cmpa_dump.bin CMPA parse into yaml with uv run python -m spsdk.apps.pfr parse -f lpc55s28 -t cmpa -b cmpa_dump.bin -o parsed_cmpa.yaml Then the same thing for CFPA with different address. I read the CFPA from address 0x9DE00, which I think is the scratch version. But the ping and pong match other than the fact that the CMPA_PROG_IN_PROGRESS reads something non-zero for the scratch. But 0x00 for ping and pong. Below is a summary of the full files attached. Full files attached for more details CMPA: PIN, DFLT NIDEN = USE_DAP, DISABLED DEGEN = USE_DAP, DISABLED TAPEN = USE_DAP, DISABLED ISP_CMD_EN = USE_DAP, DISABLED FA_ME_CMD_EN = FIXED_STATE, ENABLED SEC_BOOT_EN = ENABLE_0 CFPA: PIN, DFLT NIDEN = USE_DAP, DISABLED DEGEN = USE_DAP, DISABLED TAPEN = USE_DAP, DISABLED ISP_CMD_EN = USE_DAP, DISABLED FA_ME_CMD_EN = FIXED_STATE, ENABLED From my understanding, with these settings, I should not be able to use blhost to read memory. I can read CMPA, CFPA, application flash, application RAM, I can dump my entire executable via blhost with no DAP authentication. Questions: 1. If ISP_CMD_EN is disabled, does that mean you can not read and write to internal memory? Either PFR or application memory. I still need the ability to send secure .sb files to the bootloader though. 2. Does ISP_CMD_EN disable the ability to load .SB files via USB over the bootloader? 3. What settings do I need to keep USB bootloader functionality with .SB files, but disable the ability to read and write to memory over ISP commands? 4. Why is my MCU still allow blhost ISP commands even though the CMPA and CFPA have it disabled? I have read the forum post at this link: https://community.nxp.com/t5/LPC-Microcontrollers-Knowledge/LPC55-Disable-ISP-and-SWD-to-utilize-code-protection/ta-p/1654157 But the settings have it completely disable ISP, which disables the bootloader completely. I I don't think that forum post shows why my settings are still allowing ISP commands over the blhost, when the ISP_CMD_EN is disabled. Re: LPC55S28 ISP_CMD_EN not disabling ISP commands Hi @guitardenver
The key point is that ISP_CMD_EN is not a global enable/disable bit for all blhost commands. It controls whether ISP mode can be entered through the Debug Mailbox Enter ISP Mode command. Once the device has entered ROM ISP through another permitted boot path, USB blhost commands are handled separately by the ROM bootloader.
1. Memory read/write: Disabling ISP_CMD_EN does not by itself disable ReadMemory or WriteMemory. These commands can still access memory that is not otherwise protected.
2. SB file download: ISP_CMD_EN does not directly disable the ROM ReceiveSBFile command. Therefore, it should not be treated as the control for USB SB-file updates.
3. SB update while blocking raw memory access: According to the LPC55S28 reference manual, there is currently no configuration that can keep USB ISP available for SB updates while disabling ReadMemory and WriteMemory commands.
4. Why blhost still works: This behavior does not necessarily mean your CMPA/CFPA settings are being ignored. The device has already entered ROM ISP, while ISP_CMD_EN controls a different path into ISP.
BR
Harry Re: LPC55S28 ISP_CMD_EN not disabling ISP commands Hi Harry, Thanks for clarifying the role of ISP_CMD_EN and confirming that the ROM ISP handler lacks command-level filtering once entered. Our original design assumption was that the LPC55S28's authenticated ROM bootloader was intended to serve as the production field update interface over USB (via signed SB2.1 containers) without needing a secondary flash bootloader. However, from your reply, it appears that exposing the USB ROM ISP interface effectively leaves a wide-open memory backdoor: anyone with physical USB access can issue raw read-memory, write-memory, and flash-erase-region commands. While Secure Boot prevents modified/unsigned code from executing, an attacker could still dump unencrypted flash IP or probe SRAM in the field. Given that, I have a few specific questions on how NXP expects customers to deploy this in a secure commercial product: PRINCE + Open USB ISP: If we enable PRINCE flash encryption across the entire application flash to protect IP at rest, what is NXP's security stance on leaving USB ISP enabled in the field? Specifically, does arbitrary read/write access to internal SRAM while inside the ROM bootloader present a realistic attack surface for compromising keys or bypassing boot logic? If not, this is the path I think I would take. Recommended Field-Update Architecture: If leaving ROM ISP active over an exposed USB port is considered an insecure anti-pattern, what is NXP's recommended architecture for field updates? Does NXP recommend disabling ROM ISP entirely (DEFAULT_ISP_MODE = DISABLE) and implementing a custom dual-bank / secondary bootloader using the ROM IAP API to consume SB containers? Re: LPC55S28 ISP_CMD_EN not disabling ISP commands Hi @guitardenver
Thanks for the additional questions. I would recommend referring to AN12283 – LPC55Sxx Secure Boot, especially Sections 5, 5.6 and 5.7.
AN12283 documents the use of Secure Boot, SB2/SB2.1 firmware updates through the ROM ISP receive-sb-file command, and PRINCE flash encryption. It also states that the PRINCE keys are provided by the on-chip PUF through an internal hardware bus that is not software accessible.
One important point is to confirm your actual Secure Boot configuration. According to AN12283, SEC_BOOT_EN = 00 means Plain image, while 01, 10, and 11 mean Signed image. Since your previous SPSDK output showed SEC_BOOT_EN = ENABLE_0, I recommend checking its raw value first.
Please refer to AN12283 for the detailed Secure Boot, SB2.1 update, and PRINCE configuration.
LPC55Sxx Secure Boot
BR
Harry
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