S32K144: Is there a way to use FlexIO pin for PWM generation in Simulink Currently trying to figure out how to use a FlexIO pin for PWM generation in Simulink. I don't see any blocks in Simulink for using a FlexIO pin for PWM generation, only for I2C, SPI and UART. Any help would be greatly appreciated.  Re: S32K144: Is there a way to use FlexIO pin for PWM generation in Simulink Thank you for the information Re: S32K144: Is there a way to use FlexIO pin for PWM generation in Simulink Hello @mirali , Unfortunately, in MBDT for S32K1xx, for the FlexIO we do not provide PWM generation blocks. However, such support can be achieved by using custom code in a similar approach described by this article: https://community.nxp.com/t5/NXP-Model-Based-Design-Tools/How-to-use-your-own-C-code-in-our-Toolbox-Battery-Management/ta-p/1119004 I am not sure if the S32K1 SDK, the abstraction layer on which the MBDT for S32K1 generates the hardware access peripherals code has such support for the PWM generation, so in this case you can directly control and achieve such functionality by writing to registers using a similar approach mentioned in the article above. Regards, Marius

S32K144:SimulinkでPWM生成にFlexIOピンを使用する方法はありますか 現在、SimulinkでPWM生成にFlexIOピンを使用する方法を理解しようとしています。Simulinkには、PWM生成にFlexIOピンを使用するためのブロックは見当たらず、I2C、SPI、およびUARTのみに使用されています。どんな助けでも大歓迎です。 Re:S32K144:SimulinkでPWM生成にFlexIOピンを使用する方法はありますか 教えて頂きありがとうございました

MIFARE Development Hey there, I´m relativly new in RFID/NFC an got some questions. We´ve got a new costumer. They have already an excisting custom Board which is powered by an ST Frontend. For there current purpose they use Mifare Ultralight. Now they want to get access to several other Tags, e.g: Mifare® Classic®, Ultralight®, Ultralight C®, Plus®, DESFire® EV1, EV2, EV3, ICODE 2, ICODE SLI. I would choose the CLCR663 PLus - IC for the new development. I have watched the Mifare Academy videos, but still don´t know how to solve following problems: 1. Create Application on 3rd party Tags: In my understanding, the Tag owner has to create a new App to the e.g DESfire EV3 Tag. When connecting to the Product, the Product searches for this specific App through AID. But in case of EV3 Tag, the App is secured by an App-Key. Because the Tag owner doesn´t want me to know the Master-Key and i don´t want the owner to know my App-Key. And without the Master-Key, I´m not able to create a new App by my own, when the customer presents the Tag to my Product, or? - Who generates the Key for the App? - Is there a 'Best Practice' in those cases? 2. AES-128 key: If i want to use AES-128 encryption both sides need the same key. If there is a 3rd party Tag, i don´t know the key. Same questions like 1. - Who generates the Key? - Do i have to write the key to the Tag, when I´m able to get access to my App? - Is there a 'Best Practice' in those cases? Best regards Oliver Contact Smart Card Reader ICs Re: MIFARE Development Ok. Thank you. Re: MIFARE Development The detail information is in the full version of datasheet. The datasheet is NDA required and can be downloaded under "Secure" file.  

I.MX R1170 SEMC SDRAM 在 SRAM 访问期间中断 你好 我将 SDRAM（CS0）和 SRAM（CSX1）连接到 RT1170 的 SEMC。 我发现 CS0 有时为低脉冲而 CSX1 为低，这意味着当 SEMC 正在访问 SRAM 时，SEMC 对 SDRAM 进行了中断访问。 访问 SRAM 时是否可以阻止 SDRAM 访问？ 回复：I.MX R1170 SEMC SDRAM 在 SRAM 访问期间中断 是的，如果需要执行刷新，自动刷新仍然会中断 burts 操作。它只是分割突发，以便可以在其间插入自动刷新。 此致， 奥马尔 回复：I.MX R1170 SEMC SDRAM 在 SRAM 访问期间中断 是的，因为自动刷新是定期执行的。不幸的是，我们没有这个具体实现的例子。 此致， 奥马尔 回复：I.MX R1170 SEMC SDRAM 在 SRAM 访问期间中断 SEMC 在发送 AUTO REFRESH 命令之前发送 PRECHARGE ALL 命令来关闭设备上任何打开的页面。因此，如果自动刷新被禁用，则这两个命令都不会被执行。这在 SDRAMCR3[REN] 字段上被禁用。 请注意，如果刷新没有按照 sdram 时序进行，则可能会导致 sdram 上的某些数据丢失。 此致， 奥马尔 回复：I.MX R1170 SEMC SDRAM 在 SRAM 访问期间中断 SDRAM 的哪个特定命令会中断 SRAM 访问？ 将 BMCR 设置为 0x81 的目的是避免重新排序命令队列，以便命令按照“先进先出”策略执行。 建议 UT 和 RT 保持不变，将它们更改为内存可能的最高刷新周期可能会减少 SDRAM 的中断，因为我怀疑中断是自动刷新命令。 此致， 奥马尔 回复：I.MX R1170 SEMC SDRAM 在 SRAM 访问期间中断 我认为SDRAM的中断是由于自动刷新命令造成的，因此调整SDRAM刷新的时间对于防止这种情况至关重要。 另外，在 BMRC 寄存器上实施不同的设置可能会有所帮助，我建议设置 0x81 以防止重新排序命令。 此致， 奥马尔

I.MX R1170 SEMC SDRAM interrupt during SRAM access Hi  I'm connecting SDRAM(CS0) and SRAM(CSX1) to the SEMC of RT1170. I found CS0 sometimes had low pulse while CSX1 was low, which means SEMC had an interrupt access to SDRAM while SEMC was accessing SRAM. Is it possible to prevent SDRAM access while accessing SRAM? Re: I.MX R1170 SEMC SDRAM interrupt during SRAM access Yes, the auto-refresh still interrupts the burts operation if necesary to execute refresh. It just splits the burst so it can insert auto-refresh in between.  Best regards, Omar Re: I.MX R1170 SEMC SDRAM interrupt during SRAM access Hi @Omar_Anguiano  I found other related thread. In this thread, NXP described ">>1. The SDRAM refresh command is inserted between SEMC burst access.". It looks I can prevent SDRAM refresh from interrupting SRAM access while Auto-Refresh is enabled. Which is correct? https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Questions-when-using-SDRAM-and-SRAM-together-on-SEMC/m-p/1366152/highlight/true#M16998 Re: I.MX R1170 SEMC SDRAM interrupt during SRAM access Yes as auto-refresh is executed periodically. Unfortuantely, we don't have an example of this specific implementation.  Best regards, Omar Re: I.MX R1170 SEMC SDRAM interrupt during SRAM access Hi @Omar_Anguiano  Thank you for your support. Do you mean it's impossible to prevent SDRAM refresh from interrupting SRAM access while Auto-Refresh is enabled? Do you have any sample projects where the Auto-Refresh is disabled? Re: I.MX R1170 SEMC SDRAM interrupt during SRAM access The SEMC sends PRECHARGE ALL command to close any opened page on device before sending AUTO REFRESH command. So if the Auto-refresh is disable then both commands will not be executed. This is disabled on SDRAMCR3[REN] field.  Please consider that if refresh is not done with the sdram timings it may cause loosing some data on the sdram.  Best regards, Omar Re: I.MX R1170 SEMC SDRAM interrupt during SRAM access Hi @Omar_Anguiano  >>Which specific command of the SDRAM is interrumping the SRAM access?  I checked the interruption and it was "Precharge All Banks" and "Auto Refresh".  Is it possible to prevent these SDRAM interruptions? Which setting is causing this behavior? Re: I.MX R1170 SEMC SDRAM interrupt during SRAM access Which specific command of the SDRAM is interrumping the SRAM access?  The goal of having BMCR to 0x81 is to avoid re-ordering of the command queue so the commands are executed under "first in first out" policy.  UT and RT are suggested to stay the same, changing them to the highest refresh period possible by the memory might reduce the interruption of SDRAM as I suspect that the interruption is the auto-refresh command.  Best regards, Omar Re: I.MX R1170 SEMC SDRAM interrupt during SRAM access Hi @Omar_Anguiano  >>adjusting the timing of SDRAM refresh is crucial to prevent this. I'm using Auto Refresh so, I tried to adjust SDRAMCR3[31-1], for example changed to UT = RT or UT < RT.  However the result was same, there are still interruption of SDRAM. How can I avoid the interruption?  BMCR are set to 0x81. Re: I.MX R1170 SEMC SDRAM interrupt during SRAM access Hi Thank you for your information. But how can I adjust the timing of SDRAM refresh? Should I change UT[31-24] value?  Currently I set UT[31-24] and RT[23-16] on SDRAMCR3 as same value because NXP recommended.  BMRC registers are 0x81. Re: I.MX R1170 SEMC SDRAM interrupt during SRAM access I believe that the interruption of SDRAM is due to the auto-refresh command, so adjusting the timing of SDRAM refresh is crucial to prevent this. Also implementing different settings on the BMRC registers might be helpful, I suggest the setting of 0x81 to prevent re-ordering of the commands. Best regards, Omar

Stresstest fails at 3 frequencypoints but passes with 1 frequencypoint, LPDDR4 Hello everyone, I had asked a similar question when i used the mScale DDR Test Tool and that error was resolved when switched to ConfigTool V15. I am currently working on a board bring-up with the following combination of SOC, RAM and Software for the RAM-Stresstest: - i.MX 8M Plus (1600 MHz) + Micron LPDDR4 4GB (MT53D1024M32D4DS) - iMX Config Tool v24.12 I have used the NXP RPA Excel sheet for generating the according ".ds"-file for the Stresstest program. Also using the standard parameters in the "DDR Configuration Sheet" results in the same error.  The question is as following: Why does the Stresstest run smoothly and without errors, even under temperature fluctuations, when chosing 2000 MHz as the single frequency for the test, but fails when i chose the same parameterset, but now with three frequency points enabled. In that case the default, additional 200 MHz and 50 MHz, are tested as well.  Any help is hugely appreciated Greetings Niko i.MX 8 Family | i.MX 8QuadMax (8QM) | 8QuadPlus Re: Stresstest fails at 3 frequencypoints but passes with 1 frequencypoint, LPDDR4 Hello, If selecting a frequency range to test, ensure that the start frequency test is within ±50MHz of the frequency that the DDR initialization script is tuned for and make sure end frequency is no less than start frequency and within 100Mhz of the start frequency. Best regards. Re: Stresstest fails at 3 frequencypoints but passes with 1 frequencypoint, LPDDR4 I have already extensively tested the ODT, PDDS, Vref etc. For our highest target frequency i can get the stresstest running succesfully, without errors, when its the only tested frequency -> i assume our layout is good, because the most critical operating point works. Also in the first test run when 200 and 50 MHz are enabled. Only from the second run errors arrise in the highest frequency operating point as well -> i assume some the firmware or the Config Tool dont work as expected: So you´d test the 2000 MHz/200 MHz and 50 MHz seperately and then just enable the 3 frequencies in the RPA sheet?  Re: Stresstest fails at 3 frequencypoints but passes with 1 frequencypoint, LPDDR4 Hello, It is suggested to run the stress test at the target operating frequency for an extended period of time to verify the DDR performance on the target board. Running the stress test higher/lower than the target operating frequency is not meaningful. The signal waveform may change a lot as the frequency increases/decreases. Therefore, passing the stress test at a frequency higher/lower than the target operating frequency does not necessarily mean that there is more timing margin. To pass the stress test you may need to change: ODTImpedance Desired ODT impedance in Ohm. Valid values for DDR4=240,120,80,60,40. Valid values for LPDDR4=240,120,80,60,40 TxImpedance Write Driver Impedance for DQ/DQS in ohm (Valid values for all DDR type= 240, 120, 80, 60, 48, 40, 34) ATxImpedance Write Driver Impedance for Address/Command (AC) bus in ohm (Valid values for all DDR type = 120, 60, 40, 30, 24, 20) Best regards.

I.MX SRAMアクセス中のR1170 SEMC SDRAM割り込み こんにちは RT1170のSEMCにSDRAM(CS0)とSRAM(CSX1)を接続しています。 CS0 のパルスが Low で CSX1 のパルスが Low になることがあることがわかったのは、SEMC が SRAM にアクセスしている間に SEMC が SDRAM に割り込みアクセスしていたことを意味します。 SRAMにアクセスしながらSDRAMのアクセスを防ぐことは可能ですか? Re: SRAM アクセス中の R1170 SEMC SDRAM 割り込み I.MX はい、自動更新は、更新を実行するために必要な場合は、バーツ操作を中断します。バーストを分割するだけで、その間に自動更新を挿入できます。 よろしくお願いいたします オマル Re: SRAM アクセス中の R1170 SEMC SDRAM 割り込み I.MX はい、自動更新は定期的に実行されます。残念ながら、この特定の実装の例はありません。 よろしくお願いいたします オマル Re: SRAM アクセス中の R1170 SEMC SDRAM 割り込み I.MX SEMC は、AUTO REFRESH コマンドを送信する前に、デバイス上の開いているページを閉じるために PRECHARGE ALL コマンドを送信します。したがって、自動更新が無効になっている場合、両方のコマンドは実行されません。これは SDRAMCR3[REN] フィールドで無効になっています。 SDRAM のタイミングでリフレッシュが行われないと、SDRAM 上の一部のデータが失われる可能性があることを考慮してください。 よろしくお願いいたします オマル Re: SRAM アクセス中の R1170 SEMC SDRAM 割り込み I.MX SDRAMのどのコマンドがSRAMアクセスを妨害していますか。 BMCR を0x81する目的は、コマンドが「先入れ先出し」ポリシーで実行されるように、コマンド・キューの順序変更を回避することです。 UTとRTは同じままにしておくことをお勧めしますが、メモリによって可能な限り高いリフレッシュ期間に変更すると、中断が自動更新コマンドであると疑われるため、SDRAMの中断を減らすことができます。 よろしくお願いいたします オマル Re: SRAM アクセス中の R1170 SEMC SDRAM 割り込み I.MX SDRAMの中断は自動更新コマンドによるものと考えており、これを防ぐためにはSDRAMの更新タイミングを調整することが重要です。 また、BMRCレジスタに異なる設定を実装すると役立つかもしれませんが、コマンドの並べ替えを防ぐために0x81を設定することをお勧めします。 よろしくお願いいたします オマル

MC9S12XEP100 Flash burner question MC9S12XEP100. Code Warrior 5.9.0, single chip, absolute assembler. I have a program, similar to the one I wrote using the MC9S12C64, but larger and more complex. I couldn't figure out the flash burner process for that one until I posted the question and Ladislav was able to explain it to me with his C64-FLASH-ASM test program. Using that I was able to get my program to work just fine. Now I am having the same issue using the MC9S12XEP100 processor. I was hoping there would be enough similarities in the process that I could adapt what I learned, but I'm having some difficulties. Is there a test program similar to the C64-FLASH-ASM, but specific to the MC9S12XEP100 in single chip, absolute assembler that I could study and see if I could get that to work? I'm attaching a basic test code that I am using to troubleshoot. Regards, Robert   Re: MC9S12XEP100 Flash burner question Hi Ladislav, Thanks so much for your detailed response. There are still a few minor errors in your comments, but no matter, I'm quite sure I know what you are doing and they really helped. Your screen shots of the memory window were a big revelation to me. I didn't know about the l, g and r suffix. That explains a lot. The spread sheet that compares the equivalent addresses also really helped in my education. I now feel I have a good understanding of what you have done and a better understanding of what the debugger can do. As a result of my new found knowledge I am realizing that I should be using EEPROM emulation. I have some questions about that in a separate thread.  Thanks once more for all your help and patience. Regards, Robert Re: MC9S12XEP100 Flash burner question Hi, I have found my notes contain copy/paste mistakes. I am not sure what are you looking at so more detailed comments. Moreover, I suppose the DFLASH is in erased status before it is written. Moreover, the question is how the RAM content is refreshed in your memory window. You should also check the setup lime it is done for DFLASH. The address 0x2100 is selected by compiler so the array is placed: Buffer[0] is at address 0x2100,0x2101    of a  local address space Buffer[1] is at address 0x2102,0x2103 Buffer[2] is at address 0x2104,0x2105 Buffer[3] is at address 0x2106,0x2106 Finally, it is good to understand local and global address space. The RAM 0x2100 is in local address space 0x2100 and in the global address space 0x0F_E100. Si memory map in attachment. ... and be careful when you show address space ... extension 'G  or 'L. For example 0FE100'G and 2100'L represents the same address from different views.    .... does no exist  .... the variable "buffer" in a local address space  ... the variable "buffer" in a global address space better comments of the original asm code..            ;---------------------------             ;err = DFLASH_Program(0x0000, &buffer[0], 4); //write 4 words to D Flash address 0x10_0000             ; GPAGE (0x10_.... ) is not used in the Addr variable because it is directly used in the DFLASH_Program routine             MOVW  #$0000,Addr  ; address to be written 0x(10)0000~0x(10)0007                        MOVB  #4,Cnt       ; number of words to be written             ;for example data to be written into DFLASH are 0x0123, 0x4567, 0x89AB, 0xCDEF             ; written global DFLASH address is 0x10_0000’G   … for data visualization in a debugger memory             ; window“ ’G ” must be added into memory address             LDX   #Buffer      ; Load the base address of the array into X register, the base address                                              ; is selected by compiler if you do not set exact address             LDD  #$0123      ; Load the hexadecimal value 0x0123 into D register             STD  0,X                ; Store the value at the 0th position of the array;  Buffer[0] = 0x0123             LDD  #$4567      ; Load the value 0x4567 into D register             STD  2,X                ; Store the value at the 1st position of the array;  Buffer[1] = 0x4567             LDD  #$89AB      ; Load the value 0x89AB into D register             STD  4,X                ; Store the value at the 2nd position of the array;  Buffer[2] = 0x89AB             LDD  #$CDEF     ; Load the value 0xCDEF into D register             STD  6,X                ; Store the value at the 3rd position of the array;  Buffer[3] = 0xCDEF             CALL  DFLASH_Program  ; note there is a status of verification in the Err variable after execution of this command             ;---------------------------             ;err = DFLASH_Program(0x0008, &buffer[0], 4); //write 4 words to eeprom address 0x0000             ;… at this place you should check whether Err value is OK to be sure entire write process has             ;     finished correctly. I am not doing it in this example.             ;---------------------------             ; write another set of data to a 8 bites higher address of the DFLASH             ; written global DFLASH address is 0x10_0008’G             MOVW  #$0008,Addr  ; address to be written  0x(10)0008~0x(10)000F                        MOVB  #4,Cnt       ; number of words to be written                        ;for example data to be written into DFLASH are 0xDEAD,0xBEEF,0xC0DE,0xCAFE             LDX   #Buffer      ; Load the base address of the array into X register, the base address                                              ; is selected by compiler if you do not set exact address             LDD  #$DEAD     ; Load the hexadecimal value 0xDEAD into D register             STD  0,X                ; Store the value at the 0th position of the array;  Buffer[0] = 0x0123             LDD  #$BEEF      ; Load the value 0xBEEF into D register             STD  2,X                ; Store the value at the 1st position of the array;  Buffer[1] = 0x4567             LDD  #$C0DE      ; Load the value 0XC0DE into D register             STD  4,X                ; Store the value at the 2nd position of the array;  Buffer[2] = 0x89AB             LDD  #$CAFE     ; Load the value 0xCAFE into D register             STD  6,X                ; Store the value at the 3rd position of the array;  Buffer[3] = 0xCDEF             CALL  DFLASH_Program  ; note there is a status of verifiction in the Err variable after execution of this command             ;---------------------------             ;err = DFLASH_Program(0x0008, &buffer[0], 4); //write 4 words to eeprom address 0x0000             ;… at this place you should check whether Err value is OK to be sure entire write process has             ;     finished correctly. I am not doing it in this example.             ;--------------------------- Best regards, Ladislav Re: MC9S12XEP100 Flash burner question Hi Daniel, Freescale USBDM (from China). I use it successfully to load programs. Does that answer your question? Regards, Robert Re: MC9S12XEP100 Flash burner question Hi Robert, I mean debugger like PE Micro Multilink (with revision), USBDM, ... Re: MC9S12XEP100 Flash burner question Hi Daniel, Code Warrior IDE V5.9.0 Build 5294 Special Edition. Regards, Robert Re: MC9S12XEP100 Flash burner question Hello @roberthiebert, What debugger do you use? The debugger can interpret the data as 0xCAFE because of ECC, for example. Regards, Daniel Re: MC9S12XEP100 Flash burner question I've spent a lot of time stepping through this code and recording all the variable and register states on each step. I think I have a pretty good understanding of what is happening here, but one thing in particular still has me puzzled. In this section of code: LDX #Buffer ; Load the base address of the array into X register LDD #$0123 ; Load the value 0123 into A register STD 0,X ; Store the value at the 0th position of the array X is loaded with $2100, the address of "Buffer" in RAM D is loaded with decimal 0123 Decimal 0123 is copied into the first two bytes of the "Buffer" array at address $2100 in RAM. Now, when I use the debugger to check the contents of RAM address $2100 I see $CA, $FE in the first two bytes, and they never change. Why is this and where are the example words stored? Regards, Robert  Re: MC9S12XEP100 Flash burner question Hi, The topic has already been processes... https://community.nxp.com/t5/S12-MagniV-Microcontrollers/S12-X-MCU-Security/ta-p/1111118 https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Unsecuring-MC9S12XEP100MAG/m-p/617603 Best regards, Ladislav Re: MC9S12XEP100 Flash burner question Hi Ladislav, One more thing. I did some more research and I understand that in order for CW to be able to read the D-Flash the FSEC register needs to be set to $FE. I see that your code has done this, but I can't find out where and how you did it. Could you explain how I can do that in my code  please? Regards, Robert Re: MC9S12XEP100 Flash burner question Hi Ladislav, I have made some progress. To make a long story short, I discovered that my controller was secured. I don't know how that happened, but I was able to unsecure it and now your program is working the way you have shown in your last post. Now I am able to study your ASM code to make sure I understand it fully before I try to adapt  it it work in my code. I have one thing that is puzzling me though. If I am understanding you r code correctly, you have placed your test data to be burned to D-Flash, in RAM memory starting at Buffer: (address $2100). But when I look at that address all I ever see is $CA,$FE, repeat.  Why is this? Regards, Robert  Re: MC9S12XEP100 Flash burner question I have the memory set to refresh on halt, but no matter what I do, the memory never changes. I've tried setting breakpoints where I see you have highlighted, but nothing. I tired running the program and halting it at random points. No change. What am I doing wrong? Re: MC9S12XEP100 Flash burner question Hi, Do not step memory functions if the part of memory is displayed in the memory window of the debugger. Set refresh memory when halting First loop Second loop … after erase sector Second loop after writing data Second loop reading the data       Moreover, it is always suitable to disable possible interrupts to do not change registers. Create critical section which is not interrupted using CLI, SEI. Best regards, Ladislav Re: MC9S12XEP100 Flash burner question Hi again Ladislav, After stepping through the program again several times I noticed some other peculiar things. After running the FLASH_ERASE_VERIFY subroutine the returned "err" was $01. Which was expected. However, after any FLASH_PROGRAM subroutine "returned "err" was $40. The FLASH_READ  subroutine seems to work but it doesn't return the var_Data values I expected. It returns $FA, $CF first. $4 second. $BB $B6 third.  $46 $46 forth. The values at address $100000 are $FA, $CF, $00,$04,$BB, $B6, $46, $46. These are not the values that should have been burned to this address if I am understanding the program correctly. The values at address $2100 are $CA,$FE,$CA,$FE,$CA,$FE,$CA,$FE and they don't change. Something seems odd here. Regards, Robert  Re: MC9S12XEP100 Flash burner question Hi Ladislav, Thank you for that excellent attachment. It was just what I was looking for. It runs just fine on my controller, except for one thing. I can't seem to get the debugger to update the memory window, either for the RAM or the D-Flash. I when I single step through the program I expected to see the RAM addresses from $2100 to $2110 update with the appropriate steps. I'm not seeing this. I also expected to see the D-Flash addresses from $10000 to $100010 update as I step through, but I'm not seeing that either. Also, if I run the program and halt it, the memory locations are not updated. Are there some settings in the de-bugger that I don't have set right? Regards, Robert Re: MC9S12XEP100 Flash burner question I am very sorry but I see no issue to rebuilt C to ASM. C shows you principle and this C code is not a object oriented programming. It is simple Ansi C. Here you can see programming of D-Flash. (Not P-Flash, it is a little bit different but in principle very similar) ;************************************************************** ;* This stationery serves as the framework for a * ;* user application. For a more comprehensive program that * ;* demonstrates the more advanced functionality of this * ;* processor, please see the demonstration applications * ;* located in the examples subdirectory of the * ;* Freescale CodeWarrior for the HC12 Program directory * ;************************************************************** ; Include derivative-specific definitions INCLUDE 'derivative.inc' ; export symbols XDEF Entry, _Startup, main ; we use export 'Entry' as symbol. This allows us to ; reference 'Entry' either in the linker .prm file ; or from C/C++ later on XREF __SEG_END_SSTACK ; symbol defined by the linker for the end of the stack ;********************************************************************* OK EQU 0 ERASED EQU 1 NON_ERASED EQU 2 LENGTH_OUT_OF_RANGE EQU 3 ;********************************************************************* ; variable/data section MY_EXTENDED_RAM: SECTION ; Insert here your data definition. Buffer ds.w 4; Err ds.b 1; Addr ds.w 1; Cnt ds.b 1; var_i ds.b 1; var_j ds.b 1; var_Data ds.w 1; ;********************************************************************* ; code section MyCode: SECTION main: _Startup: Entry: ;--------------------------- LDS #__SEG_END_SSTACK ; initialize the stack pointer CLI ; enable interrupts ;--------------------------- EndlessLoop: ;--------------------------- ;EE_Init ... 0x0F //oscillator 16MHz -> divide by 0x0F to achieve FCLK 800kHz - 1.05MHz ;while(FSTAT_CCIF == 0); //wait if command in progress BRCLR FSTAT,#128,*+0 ;abs = 0001 ;FCLKDIV = fdiv; //osc = 16MHz LDAB #$0F STAB FCLKDIV ;--------------------------- ;DFLASH_Erase_Sector(0x0000); //erase first sector (256 bytes) MOVW #$0000,Addr CALL DFLASH_Erase_Sector ;--------------------------- ;err = DFLASH_Erase_Verify(0x0000, 16); //check if 16 words are erased - we will receive ERASED message MOVW #$0000,Addr MOVB #16,Cnt CALL DFLASH_Erase_Verify ; note there is a status of verification in the Err variable after execution of this command ;--------------------------- ;err = DFLASH_Program(0x0000, &buffer[0], 4); //write 4 words to D Flash address 0x0000 MOVW #$0000,Addr ; address to be written MOVB #4,Cnt ; number of words to be written ;for example data to be written into DFLASH are 0123, 4567, 89AB, CDEF LDX #Buffer ; Load the base address of the array into X register LDD #$0123 ; Load the value 0123 into A register STD 0,X ; Store the value at the 0th position of the array LDD #$4567 ; Load the value 4567 into A register STD 2,X ; Store the value at the 1st position of the array LDD #$89AB ; Load the value 89SB into A register STD 4,X ; Store the value at the 2nd position of the array LDD #$CDEF ; Load the value CDEF into A register STD 6,X ; Store the value at the 3rd position of the array CALL DFLASH_Program ; note there is a status of verifiction in the Err variable after execution of this command ;--------------------------- ;err = DFLASH_Program(0x0008, &buffer[0], 4); //write 4 words to eeprom address 0x0000 MOVW #$0008,Addr ; address to be written MOVB #4,Cnt ; number of words to be written ;for example data to be written into DFLASH are 0123, 4567, 89AB, CDEF LDX #Buffer ; Load the base address of the array into X register LDD #$DEAD ; Load the value 0123 into A register STD 0,X ; Store the value at the 0th position of the array LDD #$BEEF ; Load the value 4567 into A register STD 2,X ; Store the value at the 1st position of the array LDD #$C0DE ; Load the value 89SB into A register STD 4,X ; Store the value at the 2nd position of the array LDD #$CAFE ; Load the value CDEF into A register STD 6,X ; Store the value at the 3rd position of the array CALL DFLASH_Program ; note there is a status of verifiction in the Err variable after execution of this command ;--------------------------- ; get written data ;--------------------------- MOVW #$0000,Addr CALL DFLASH_Read STD var_Data MOVW #$0002,Addr CALL DFLASH_Read STD var_Data MOVW #$0004,Addr CALL DFLASH_Read STD var_Data MOVW #$0006,Addr CALL DFLASH_Read STD var_Data ;--------------------------- JMP EndlessLoop ; restart. ;--------------------------- ;********************************************************************* ;DFLASH_Read ;********************************************************************* DFLASH_Read: MOVB #$10, GPAGE LDX Addr GLDD X RTC ;********************************************************************* ;DFLASH_Program ;********************************************************************* DFLASH_Program: ;if((Cnt < 1) || (Cnt > 4)) LDAB Cnt CMPB #1 BCS LBL_DP1 CMPB #4 BLS LBL_DP2 ;return LENGTH_OUT_OF_RANGE; LBL_DP1: MOVB #LENGTH_OUT_OF_RANGE,Err RTC LBL_DP2: ;while(FSTAT_CCIF == 0); //wait if command in progress BRCLR FSTAT,#128,*+0 ;abs = 000e ;FSTAT = 0x30; //clear ACCERR and PVIOL MOVB #$30, FSTAT ;FCCOBIX = 0x00; CLR FCCOBIX ;FCCOB = 0x1110; MOVW #$1110,FCCOB ;FCCOBIX = 0x01; MOVB #$1,FCCOBIX ;FCCOB = address; MOVW Addr,FCCOB ;for(i=2; i<=Cnt+1; i++) //fill appropriate number of words to FCCOB CLRA LDX #Buffer LDAB Cnt INCB STAB var_j ; end variable of cycle LDAA #$2 ; start value of cycle LBL_DP3: ;FCCOBIX = A = 2 to {3,4,5}; STAA FCCOBIX ;FCCOB = *ptr; LDD 2,X+ STD FCCOB LDAA FCCOBIX INCA CMPA var_j BLS LBL_DP3 ;FSTAT_CCIF = 1; //launch command BSET FSTAT,#128 ;while(FSTAT_CCIF == 0); //wait for done BRCLR FSTAT,#128,*+0 ;abs = 004b ;return OK; MOVB OK,Err RTC ;********************************************************************* ;DFLASH_Erase_Verify ;********************************************************************* DFLASH_Erase_Verify: ;while(FSTAT_CCIF == 0); //wait if command in progress BRCLR FSTAT,#128,*+0 ;abs = 0001 ;FSTAT = 0x30; //clear ACCERR and PVIOL MOVB #$30,FSTAT ;FCCOBIX = 0x00; CLR FCCOBIX ;FCCOB = 0x1010; MOVW #$1010, FCCOB ;FCCOBIX = 0x01; MOVB #$1, FCCOBIX ;FCCOB = address; MOVW Addr, FCCOB ;FCCOBIX = 0x02; MOVB #$2, FCCOBIX ;FCCOB = number_of_bytes; MOVB Cnt,FCCOB ;FSTAT_CCIF = 1; //launch command BSET FSTAT,#128 ;while(FSTAT_CCIF == 0); //wait for done BRCLR FSTAT,#128,*+0 ;abs = 002b ;if(FSTAT_MGSTAT == 0) BRCLR FSTAT,#3,*+7 ;abs = 0037 BRA lbl_nonerased ;return ERASED; MOVB #ERASED, Err RTC lbl_nonerased: ;return NON_ERASED; MOVB #NON_ERASED, Err RTC ;********************************************************************* ;void DFLASH_Erase_Sector(unsigned int address) ;********************************************************************* DFLASH_Erase_Sector: ;while(FSTAT_CCIF == 0); //wait if command in progress BRCLR FSTAT,#128,*+0 ;abs = 0001 ;FSTAT = 0x30; //clear ACCERR and PVIOL MOVB #$30, FSTAT ;FCCOBIX = 0x00; CLR FCCOBIX ;FCCOB = 0x1210; MOVW #$1210, FCCOB ;FCCOBIX = 0x01; MOVB #$1, FCCOBIX ;FCCOB = address; MOVW Addr,FCCOB ;FSTAT_CCIF = 1; //launch command BSET FSTAT,#128 ;while(FSTAT_CCIF == 0); //wait for done BRCLR FSTAT,#128,*+0 ;abs = 0022 RTC ;********************************************************************* ;********************************************************************* ;********************************************************************* ;********************************************************************* ;********************************************************************* Re: MC9S12XEP100 Flash burner question I'm still working hard at trying to figure this "C" code out but getting nowhere. The code runs and says that the first 256 bytes in D Flash have been erased at $10_0000, but I don't see that. Then it says that buffer[0] has been written into $0_0000, $10_0008 and $10_0010, But I don't see that either. What am I missing here? Regards, Robert Re: MC9S12XEP100 Flash burner question I'm still not getting anywhere with this. I've tried to figure out the ASM by stepping through the code, but I really have to be able to understand what the program is doing in "C" first. I believe that it partitions the DFlash then erases it all. Then it writes 16 bytes that it had written into RAM into D FLash. I can find the bytes in RAM, but in no place in D Flash can I find where it has written them in.  Any suggestions would be greatly appreciated. Regards, Robert Re: MC9S12XEP100 Flash burner question Hi Ladislav, This is not easy stuff for me, but I was able to load your XEP100-DFLASH-CW47 program into my controller using a USBDM. I believe the program is running correctly. I expected to see the D-Flash address from $10_0000 loaded with $12, $34, $56, $78 $9A, $BC, $DE, $F0, but nothing is there. I also expected to see each of the remainder of the 256 byte sector loaded with $FF.  Perhaps my understanding of how the program is supposed to work is flawed? Regards, Robert Re: MC9S12XEP100 Flash burner question Hi Ladislav, Thanks again for your prompt reply and the files. I am not a "C" engineer and only have a basic knowledge of the language so the disassembly process will be challenging, but I'll give it my best shot. Regards, Robert Re: MC9S12XEP100 Flash burner question Hi, there are no similarities. It is 2 levels higher MCU with different memory organization. In this case I suggest to use DFLASH for data storage. There is no ASM code available but I believe it is not any problem to do it by disassembling C code. If you are C coding engineer it must be easy for you to rebuilt it to asm. Here is a C code and the project is attached. You can go/step through the ASM code in debugger to see how it works. I have also attached C code for PFLASH programming. Nothing easier but it does not require to  perform partitioning of this memory. There are some similarities in addresses but global address must be used for data E/W. Short (4000-7FFF) and PPAGE_Offset addresses are used for program execution. In the case of the MCU it will require more effort to understand how flash is organized and how it works. Moreover, to go from relocatable assembly of the single file project to the absolute assembly is easy. Directive EQU is used for data placement into RAM and ORG is used to place code in given PFLASH space. What is necessary to be understand is that for reading and writing DFLASH the global address must be used. However in the case of this memory it is solved easily because it has higher word (DPAFE ) always 0x10 so it is enough to send to the routine only offset in the range 0000-7FFF and full address is created in routine, for example DFLASH_Program.. I am sorry we do not have any empty space, resources or responsibility for such complex projects … plus in assembler. Best regards, Ladislav Re: MC9S12XEP100 Flash burner question Oops. I forgot to mention that when I try to erase the sectors I get an Access Error code. Regards, Robert Re: MC9S12XEP100 Flash burner question I'll try the attachment again

S32K1xx：Frequent access to eeprom sends hardfault Hello,     In the development process encountered a problem, frequent access to the S32K118 analog eeprom sent hardfault, I know frequent write eep without delay will occur errors, frequent read will also? The snippet code is as follows：     for (uint8 i = 0; i < 16u; i++)     {         u8slog[i] = *((uint8 *)(0x14000000) + i) ;     } Re: S32K1xx：Frequent access to eeprom sends hardfault Hi @ZEROOO, Reading the FlexRAM does not require any delay, even in the EEE mode, it is just an SRAM. But instead of valid data, the read access can return all 0xFF if there is an ECC error in the backup flash. So, the application should check if the data are valid before they are processed further. Writing does not require any delay per se, it requires the CCIF flag to be set before the FlexRAM in the EEE mode can be written. Regards, Daniel Re: S32K1xx：Frequent access to eeprom sends hardfault Hello, Yes, frequent reads from the S32K118's analog EEPROM, even without writes, can potentially lead to issues and even hard faults. Here's a breakdown of why and how to mitigate it: Understanding the S32K118 Analog EEPROM Not a Standard Memory: The analog EEPROM on the S32K118 is not like standard RAM or flash. It's an emulated EEPROM using flash memory, and it has specific characteristics that must be considered. Limited Endurance: Even read operations can contribute to the wear and tear of the underlying flash memory cells. While reads don't cause the same level of stress as writes, repeated reads over time can still degrade the flash. Access Timing: The analog EEPROM access, especially reads, might require specific timing considerations. If reads are performed too rapidly without allowing sufficient time for the memory to stabilize, it can lead to errors. Bus Conflicts: Very frequent reads can potentially cause bus conflicts or timing issues, especially if other peripherals or processes are also accessing the memory bus. This can manifest as a hard fault. Why Frequent Reads Can Cause Issues Flash Wear (Though Minor): While writes are the primary cause of flash wear, repeated reads can also contribute, albeit to a much lesser extent. The flash memory cells are still subjected to electrical stress during read operations. Timing and Bus Contention: The memory controller needs time to access and retrieve data from the flash memory. If reads are performed too rapidly, it might not be able to keep up, leading to data corruption or bus errors. If other peripherals are also accessing the memory bus, frequent reads can exacerbate bus contention, potentially leading to hard faults. Potential for Software Errors: If the read operation is not handled correctly in the software, it can lead to errors. For example, reading beyond the valid address range or not checking for errors can cause issues. Analyzing Your Code Snippet for (uint8 i = 0; i < 16u; i++) { u8slog[i] = *((uint8 *)(0x14000000) + i); } This code reads 16 bytes sequentially from the analog EEPROM address range starting at 0x14000000. If this code is executed very frequently without any delays, it could contribute to the problems mentioned above. Mitigation Strategies Introduce Delays: Add small delays between read operations to allow the memory controller to stabilize. The necessary delay will depend on the specific characteristics of the S32K118's analog EEPROM. Example:   #include "S32K118.h" // Include header file for delay functions. for (uint8 i = 0; i < 16u; i++) { u8slog[i] = *((uint8 *)(0x14000000) + i); //Add a small delay. for(volatile uint32_t delay = 0; delay < 1000; delay++){} //example delay. } Note that the delay amount will need to be tuned for your specific application. Using a timer based delay is preferable to a simple loop delay. Read Less Frequently: If possible, reduce the frequency of read operations. Cache the data in RAM if it doesn't change frequently. Check for Errors: Implement error checking to detect any read errors. The S32K118 might have status registers or flags that indicate memory access errors. Optimize Bus Usage: Minimize bus contention by optimizing the timing of other peripheral accesses. If possible, use DMA to reduce the CPU load during memory access. Refer to the Datasheet: Consult the S32K118 datasheet and reference manual for specific timing requirements and recommendations for analog EEPROM access. Verify Address Range: Ensure that the address range that you are reading from is valid. Reading from an invalid address range will cause a hardfault.

Inquiry About MCAL BSP Support for MPC5775B Dear NXP Support Team,     We recently purchased the MPC5775B BMS and VCU Reference Design (RDVCU5775EVM) under the assumption that a supporting MCAL BSP is available for the MPC5775B microcontroller. However, I was unable to find any MCAL package on your website for this specific controller. Could you kindly provide guidance on where I can obtain the MCAL BSP for this MCU? If it is not publicly available, please let me know the process to access it. Looking forward to your response. Re: Inquiry About MCAL BSP Support for MPC5775B Thanks for all the responses so far, I am good with tres os studio installation and supporting MCAL package for MPC5775B.Iam very much newbie to the tool and trying to configure pins, directions and drivers. The tool which I have installed is EB tresos 21.0. I am trying to configure the pins for SPI driver. Can someone help me out how to kick start? upon browsing I am supposed to configure port ID and direction. But I don't find any option to configure such. Kindly help me out with some genuine tutorial. Also will there be any kind of manual/input sheet for configuring drivers like SPI, CAN, NVM for the given product RDVCU5775EVM.  Re: Inquiry About MCAL BSP Support for MPC5775B Hello, When it is not suggested to use SDK how can I apply RTOS features now? Can I only use only RTOS feature of SDK or what would be the best approach? Well, if you want AUTOSAR spec OS, then you have to go to third party, like Elektrobit or Vector. As you can see on our web AUTOSAR OS is not available form NXP, as we were not participating on development of it. You can use FreeRTOS, but it is not AUTOSAR compliant. Best regards, Peter Re: Inquiry About MCAL BSP Support for MPC5775B Thanks for all the provided solutions. It worked and now I am able to configure the drivers for MCAL. But the only component I am concerned is about RTOS (Free RTOS). When it is not suggested to use SDK how can I apply RTOS  features now? Can I only use only RTOS feature of SDK or what would be the best approach? Re: Inquiry About MCAL BSP Support for MPC5775B Hello, Does the Power Architecture SDK support integration with MCAL? SDK is not autosar complaint. So I suppose such would not be possible. Also I would not recommend it, especially when MCAL is free of charge. https://www.nxp.com/docs/en/fact-sheet/S32SDKFS.pdf Is there an official MCAL package available for MPC5775B? If so, where can I download it? Yes, You can find it directly at the web of the MPC5775B. As I have expressed earlier. What is the recommended approach to integrate MCAL with EB tresos Studio for AUTOSAR compliance? Simply install it. MCAL is only software package supported by EB tresos configuration GUI. Not sure what you want to integrate into the GIU. Best regards, Peter Re: Inquiry About MCAL BSP Support for MPC5775B Hello , Please help me with above questions Re: Inquiry About MCAL BSP Support for MPC5775B When trying to extract the MCAL safety pack files, it is asking to browse for ".lic" file which is unknown. Could you please help me in locating the .lic file Re: Inquiry About MCAL BSP Support for MPC5775B Alright!! Thanks. Kindly help me with my other question as well Re: Inquiry About MCAL BSP Support for MPC5775B hello, Hmm, that's weird. You will need to get in touch with Elektribit support as Tresos is not NXP product and we do not have knowledge on such issues. Best regards, Peter Re: Inquiry About MCAL BSP Support for MPC5775B Kindly help me with these questions also please Re: Inquiry About MCAL BSP Support for MPC5775B I am doing the same . I entered the activation code and also able to acheive succesful activation. When I open the tresos studio it always for a license key which is not findable for me. Kindly help me with the solution Re: Inquiry About MCAL BSP Support for MPC5775B Hello, Hmm, the license file is generated from license admin app. Just enter the code and that is it: Best regards, Peter Re: Inquiry About MCAL BSP Support for MPC5775B Hello, Yes, those 2 devices share the same BSP. Best regards, Peter Re: Inquiry About MCAL BSP Support for MPC5775B Hello, I am working with the MPC5775B microcontroller and have imported the Power Architecture SDK for this device. I now need a compatible MCAL package to configure drivers and integrate with an RTOS. Could you please confirm: Does the Power Architecture SDK support integration with MCAL? Is there an official MCAL package available for MPC5775B? If so, where can I download it? What is the recommended approach to integrate MCAL with EB tresos Studio for AUTOSAR compliance? Any guidance or documentation references would be greatly appreciated. Thanks in advance! Re: Inquiry About MCAL BSP Support for MPC5775B Hello, I obtained a product key for tresos studio . I activated the license but not able to obtain the .lic file ad now not able to access the tresos studio . Kindly help me Re: Inquiry About MCAL BSP Support for MPC5775B Thanks for the reply. Re: Inquiry About MCAL BSP Support for MPC5775B Thanks for the quick reply, Are you sure the MCAL for the MPC5777C meets our requirements for the MPC5775B? The MCU series number is different. Re: Inquiry About MCAL BSP Support for MPC5775B Hello, Hmm seems like the MPC5777C is missing in the links list https://www.nxp.com/design/design-center/software/automotive-software-and-tools/autosar/autosar-4-0-x-classic-platform-software:AUTOSAR-4 MPC5775B/E and MPC5777C use the same package. As MPC5775 is only derivative of MPC5777C. Best regards, Peter

S32K344 bare-metal DMA initialization I've got a problem with DMA init. I was unable to initialize DMA by using bare-metal programming. The interrupt is not called and no data is passed. Meanwhile interrupt from SPI is working. Could you check my DMA configuration? I also set a "LPSPI_DER_RDDE" bit in "IP_LPSPI/n/->DER" register. This should set DMA for receive data.  void DMA_Init(volatile uint32_t rxBuffer) { /* For remaining S32K3xx devices: DMAMUX_0 channel 0-15 and DMAMUX_1 channel 0-15 are mapped to eDMA Transfer Control Descriptor(TCD) 0-15 and eDMA Transfer Control Descriptor(TCD) 16-31, respectively */ // TCD register init IP_TCD->TCD0_SADDR = 0U; IP_TCD->TCD0_SOFF = 0; IP_TCD->TCD0_ATTR = 0U; IP_TCD->NBYTES0.TCD0_NBYTES_MLOFFNO = 0U; IP_TCD->NBYTES0.TCD0_NBYTES_MLOFFYES = 0U; IP_TCD->TCD0_SLAST_SDA = 0; IP_TCD->TCD0_DADDR = 0U; IP_TCD->TCD0_DOFF = 0; IP_TCD->CITER0.TCD0_CITER_ELINKNO = 0U; IP_TCD->CITER0.TCD0_CITER_ELINKYES = 0U; IP_TCD->TCD0_DLAST_SGA = 0; IP_TCD->TCD0_CSR = 0U; IP_TCD->BITER0.TCD0_BITER_ELINKNO = 0U; IP_TCD->BITER0.TCD0_BITER_ELINKYES = 0U; //===== DMA MUX =====// // Enable a source without periodic triggering // 1. Determine the DMA channel with which the source is associated. // LPSPI1 DMA RX Request -> Source 46 // 2. Write 0 to CHCFGn[ENBL] and CHCFGn[TRIG] of the DMA channel. IP_DMAMUX_0->CHCFG[0] &= ~DMAMUX_CHCFG_ENBL_MASK; IP_DMAMUX_0->CHCFG[0] &= ~DMAMUX_CHCFG_TRIG_MASK; // 3. You can enable the DMA channel at this point. IP_DMAMUX_0->CHCFG[0] |= DMAMUX_CHCFG_ENBL_MASK; // 4. Select the source to be routed to the DMA channel. IP_DMAMUX_0->CHCFG[0] |= DMAMUX_CHCFG_SOURCE(46); //===== eDMA =====// // 1. Write to the CSR if a configuration other than the default is wanted. // 2. Write the channel priority levels to the CHn_PRI registers and group priority levels to the CHn_GRPRI registers if a // configuration other than the default is wanted. // 3. Enable error interrupts in the CHn_CSR[EEI] registers if they are wanted. // 4. Write the 32-byte TCD for each channel that may request service. // CH0_SBR_MID: Default master id -> 0b10 // Source address -> SPI receive buffer IP_TCD->TCD0_SADDR = IP_LPSPI_1->RDR; // Destination address IP_TCD->TCD0_DADDR = rxBuffer; // Source Address Offset IP_TCD->TCD0_SOFF = 4; // Destination Address Offset IP_TCD->TCD0_DOFF = 4; // Source size: 32-bit IP_TCD->TCD0_ATTR |= DMA_TCD_TCD0_ATTR_SSIZE(0b10); // Destination size: 32-bit IP_TCD->TCD0_ATTR |= DMA_TCD_TCD0_ATTR_DSIZE(0b10); // 4 byte transfer IP_TCD->NBYTES0.TCD0_NBYTES_MLOFFNO = 4; // Current Major Loop Count IP_TCD->CITER0.TCD0_CITER_ELINKNO = 1; // Beginning Major Loop Count IP_TCD->BITER0.TCD0_BITER_ELINKNO = 1; // Interrupt after transfer is complete IP_TCD->TCD0_CSR |= DMA_TCD_TCD0_CSR_INTMAJOR_MASK; // Enable interrupt __NVIC_ClearPendingIRQ(DMATCD0_IRQn); __NVIC_SetPriority(DMATCD0_IRQn, 0); __NVIC_EnableIRQ(DMATCD0_IRQn); // 5. Enable any hardware service requests via the CHn_CSR[ERQ] registers. IP_TCD->CH0_CSR |= DMA_TCD_CH0_CSR_ERQ_MASK; } void DMATCD0_Handler(void) { // Print rxBuffer printf("rxBuffer: %ld", rxBuffer); // Clear interrupt request IP_TCD->CH0_INT = 1; } Re: S32K344 bare-metal DMA initialization Hi @mateusz_swiszcz, Here is the offset of the registers: Re: S32K344 bare-metal DMA initialization Hi, @danielmartynek  Why does CHCFG[3] works and CHCFG[0] not when I'm using TCD0 and Channel 0 of DMA? How can i match numbers of CHCFG[n], TCDn, CHn in case of other instances of SPI or other peripheries? Re: S32K344 bare-metal DMA initialization Thanks for the help, it works Re: S32K344 bare-metal DMA initialization HI Mateusz, Thanks for the project. First, I enabled DMAMUX_0_CH0 at 4028_0000h + 0x3. IP_DMAMUX_0->CHCFG[3] = 0xAE; Then I saw that SBE = 1 Source bus error in the TCD0 descriptor. The TCD0_SADDR register was not configured (checked in the register view) IP_TCD->TCD0_SADDR = &IP_LPSPI_1->RDR; Now, it gets to the DMA handler: Regards, Daniel Re: S32K344 bare-metal DMA initialization Hi, @danielmartynek  The whole projects is in the attachment. Re: S32K344 bare-metal DMA initialization Hi @mateusz_swiszcz, Could you share the whole project so that I can test it? It can be shared privately via a support ticket. Re: S32K344 bare-metal DMA initialization Hi, I disabled a source address offset but nothing changed. There's no error flags in EDMA. I have buffers in non-cacheable SRAM.  NVIC->ISER[0] = 0x10; NVIC->ISER[5] = 0x40; NVIC->ICER[0] = 0x10; NVIC->ICER[5] = 0x40 EDMA->CSR = 0x300000 Other register fields in EDMA and NVIC are null. Re: S32K344 bare-metal DMA initialization Hi @mateusz_swiszcz, You should not offset the source address (TCD0_SOFF), but otherwise I don't see any issue in the code. Is there any error flag set in EDMA? Do you have the buffers in non-cacheable SRAM? Can you dump the EDMA and NVIC registers and share it? Thanks, Daniel

ADC Acquisition Issue with Triangular Signal Generated by DAC on NHS3152 I am using an NHS3152 device to generate a triangular waveform via the DAC and measure this signal with the ADC. The configuration is as follows The DAC output is configured on pin ANA0_5 using the function Chip_ADCDAC_SetMuxDAC with the parameter ADCDAC_IO_ANA0_5. The ADC input is configured on pin ANA0_3 using Chip_ADCDAC_SetMuxADC with the parameter ADCDAC_IO_ANA0_3. A cable physically connects ANA0_5 to ANA0_3 to loop the signal. Technical Details: The IOCON configuration for both pins is set to analog mode (IOCON_FUNC_1). The DAC is operated in SINGLE_SHOT mode to update the output on each write, although switching to CONTINUOUS mode does not resolve the issue—it only slightly affects the signal quality. The ADC runs in continuous mode, with detection thresholds set to 1500 (LOW_THRESHOLD) and 2000 (HIGH_THRESHOLD). The code generates a lookup table (LUT) for a triangular waveform (ranging from DAC_MIN_VALUE to DAC_MAX_VALUE), and a 16-bit timer periodically triggers the DAC update. Despite a clearly observable triangular signal on the output, no ADC interrupt is triggered and no ADC conversion result is recorded. Troubleshooting Steps Taken: I verified that the MUX selection functions (Chip_ADCDAC_SetMuxADC and Chip_ADCDAC_SetMuxDAC) use the correct channels (channel 3 for ADC and channel 5 for DAC) as specified in the documentation (Figure 90, Chapter 9.4 of the UM10876 manual). I confirmed that the IOCON settings for both pins are correctly set to analog mode (IOCON_FUNC_1) and that the cable connecting ANA0_5 to ANA0_3 is properly installed with a common ground. I tested modifying the check for the ADC conversion ready flag (ADCDAC_INT_CONVERSION_RDY_ADC) in the ADC interrupt routine, but this did not change the behavior. Changing the DAC mode between SINGLE_SHOT and CONTINUOUS has no significant effect on the issue, apart from a slight variation in the signal quality. Request for Assistance: I would appreciate your help in understanding whether: The current configuration using two different pins via the analog multiplexer is correct for the shared ADCDAC block on the NHS3152, considering it operates with a round-robin scheduler. There are additional constraints (such as timing or configuration sequence issues) that might prevent the ADC interrupts from being triggered in this setup. Alternative modifications, such as testing the ADC in single-shot mode or using the same channel for both ADC and DAC, could resolve the issue. Please find attached the complete code used for this configuration. Thank you in advance for your assistance and suggestions. Regards, Thomas Re: ADC Acquisition Issue with Triangular Signal Generated by DAC on NHS3152 I wanted to update you on the ticket I submitted. The main issues were: The triangular waveform generated by the DAC was too fast. This fast signal did not give the ADC enough time to capture the values correctly. I mistakenly used the wrong name for the interrupt handler. It must be named ADC_IRQHandler(void) instead of ADCDAC_IRQHandler(void). After lowering the frequency (or increasing the number of samples per period) and renaming the interrupt routine, the ADC started working as expected.

How S32G3 Linux BSP 35 enable ttyLF1 Hi NXP team, I referenced S32G399ardb3 and designed out custom board and use Linux BSP 35. Our S32G3 customized board can not receive UART data from PC,but PC can received UART data from S32G3 How do we know what function PINMUX FUNC X represents in device tree? If we enable UART2 how should PINMUX FUNC X be set? Below is our device tree (I follow BSP 43 to modify) uart1_pins: uart1_pins { uart1_pins_grp0 { pinmux = FUNC2)>; // PC_08 output-enable; slew-rate = ; }; uart1_pins_grp1 { pinmux = FUNC0)>; // PC_04 input-enable; slew-rate = ; }; uart1_pins_grp2 { pinmux = FUNC2)>; }; }; &uart1 { pinctrl-0 = <&uart1_pins>; pinctrl-names = "default"; status = "okay"; }; I use command in S32G3 to send data echo "Test" > /dev/ttyLF1 My PC can use command to received data cat /dev/ttyUSB1 Thanks 回复： How S32G3 Linux BSP 35 enable ttyLF1 Hi @GG0712, Thanks for share your solution.  回复： How S32G3 Linux BSP 35 enable ttyLF1 Hi @carlos_o , I solved this issue and thanks for your support. I modify Linux serial driver in "drivers/tty/serial/serial_core.c" normal->init_termios.c_cflag = B921600 | CS8 | CREAD | HUPCL | CLOCAL; normal->init_termios.c_ispeed = normal->init_termios.c_ospeed = 921600; Now, the ttyLF1 and ttyLF2 default baud rate is 921600 and serial console baud rate is 115200 Below is my test log (I jump the ttyLF2 and connect it to USB to TTL dongle) root@s32g399ardb3:~# stty -F /dev/ttyLF1 speed 921600 baud; line = 0; -brkint -imaxbel root@s32g399ardb3:~# echo "test" > /dev/ttyLF2 root@s32g399ardb3:~# root@s32g399ardb3:~# cat /dev/ttyLF2 PC to GW PC PC:~$ stty -F /dev/ttyUSB1 921600 -opost -onlcr -isig -icanon -iexten -echo -echoe -echok -echoctl -echoke -icrnl -inlcr PC:~$ PC:~$ cat /dev/ttyUSB1 test ^C PC:~$ PC:~$ echo "PC to GW" > /dev/ttyUSB1 Thanks 回复： How S32G3 Linux BSP 35 enable ttyLF1 Hi @GG0712, You are right the documentation I shared is to change the baudrate for the UART used as console. In this case the recommendation is to use the stty command to change to another standard baudrate. This because the serial driver used for the UART is the provided with linux.  回复： How S32G3 Linux BSP 35 enable ttyLF1 Hi @carlos_o , It looks like same as BSP 43 User Manual at chapter 29.6 My understanding is that this is to change the serial console and the baud rate of the default tty during the startup phase. But my requirement is that the baud rate of ttyLF0 is 115200 and still serves as the serial console. The baud rate of ttyLF1 needs to be changed from the default 9600 to other values. Thanks 回复： How S32G3 Linux BSP 35 enable ttyLF1 Hi @GG0712, You can find that information at the BSP 42 User Manual at chapter 27.5 Changing UART baud rate. 回复： How S32G3 Linux BSP 35 enable ttyLF1 Hi NXP team, Currently working correctly. But how do I set the baud rate without using stty comand? Note: ttyLF1 is internal UART instead of serial console 回复： How S32G3 Linux BSP 35 enable ttyLF1 Hi @GG0712, As you say, the FUNCX is described at the S32G3_IOMUX 2.xlsx file attached at the Reference Manual (it needs to be open with Acrobat Reader to open the attached files).  After changing this setting, is the UART working correctly? Let me know if you face any other issue with this.  回复： How S32G3 Linux BSP 35 enable ttyLF1 Hi NXP team, I found these issue in S32G3_IOMUX 2.xlsx file PC_04 PINMUX function "LIN Receive Data" SSS is 0000_0100, so it should be FUNC4 uart1_pins_grp2 { pinmux = FUNC4)>; }; Thanks

S32G3 Linux BSP 35如何启用ttyLF1 您好，NXP团队： 我参考了 S32G399ardb3 并设计了定制板并使用 Linux BSP 35。 我们的S32G3定制板无法接收PC的UART数据，但PC可以接收S32G3的UART数据 我们如何知道 PINMUX FUNC X 在设备树中代表什么功能？ 如果我们启用 UART2 ，应该如何设置 PINMUX FUNC X？ 下面是我们的设备树（我按照BSP 43进行修改） uart1_pins: uart1_pins { uart1_pins_grp0 { pinmux = FUNC2)>; // PC_08 output-enable; slew-rate = ; }; uart1_pins_grp1 { pinmux = FUNC0)>; // PC_04 input-enable; slew-rate = ; }; uart1_pins_grp2 { pinmux = FUNC2)>; }; }; &uart1 { pinctrl-0 = <&uart1_pins>; pinctrl-names = "default"; status = "okay"; }; 我使用S32G3中的命令发送数据 echo "Test" > /dev/ttyLF1 我的电脑可以使用命令来接收数据 cat /dev/ttyUSB1 谢谢！ 回复： S32G3 Linux BSP 35 如何启用ttyLF1 您好，NXP团队： 目前工作正常。 但是如何在不使用 stty 命令的情况下设置波特率？ 注意：ttyLF1 是内部 UART，而不是串行控制台 回复： S32G3 Linux BSP 35 如何启用ttyLF1 您好，NXP团队： 我在S32G3_IOMUX 2.xlsx文件中发现了这些问题 PC_04 PINMUX功能“LIN接收数据”SSS为0000_0100，因此应该是FUNC4 uart1_pins_grp2 { pinmux = FUNC4)>; }; 谢谢！

S32K344裸机DMA初始化 我的 DMA 初始化出现了问题。我无法使用裸机编程来初始化 DMA。未调用中断且未传递任何数据。同时，SPI 中断正在工作。你能检查一下我的 DMA 配置吗？我还在“IP_LPSPI/n/->DER”寄存器中设置了“LPSPI_DER_RDDE”位。这应该设置 DMA 来接收数据。 void DMA_Init(volatile uint32_t rxBuffer) { /* For remaining S32K3xx devices: DMAMUX_0 channel 0-15 and DMAMUX_1 channel 0-15 are mapped to eDMA Transfer Control Descriptor(TCD) 0-15 and eDMA Transfer Control Descriptor(TCD) 16-31, respectively */ // TCD register init IP_TCD->TCD0_SADDR = 0U; IP_TCD->TCD0_SOFF = 0; IP_TCD->TCD0_ATTR = 0U; IP_TCD->NBYTES0.TCD0_NBYTES_MLOFFNO = 0U; IP_TCD->NBYTES0.TCD0_NBYTES_MLOFFYES = 0U; IP_TCD->TCD0_SLAST_SDA = 0; IP_TCD->TCD0_DADDR = 0U; IP_TCD->TCD0_DOFF = 0; IP_TCD->CITER0.TCD0_CITER_ELINKNO = 0U; IP_TCD->CITER0.TCD0_CITER_ELINKYES = 0U; IP_TCD->TCD0_DLAST_SGA = 0; IP_TCD->TCD0_CSR = 0U; IP_TCD->BITER0.TCD0_BITER_ELINKNO = 0U; IP_TCD->BITER0.TCD0_BITER_ELINKYES = 0U; //===== DMA MUX =====// // Enable a source without periodic triggering // 1. Determine the DMA channel with which the source is associated. // LPSPI1 DMA RX Request -> Source 46 // 2. Write 0 to CHCFGn[ENBL] and CHCFGn[TRIG] of the DMA channel. IP_DMAMUX_0->CHCFG[0] &= ~DMAMUX_CHCFG_ENBL_MASK; IP_DMAMUX_0->CHCFG[0] &= ~DMAMUX_CHCFG_TRIG_MASK; // 3. You can enable the DMA channel at this point. IP_DMAMUX_0->CHCFG[0] |= DMAMUX_CHCFG_ENBL_MASK; // 4. Select the source to be routed to the DMA channel. IP_DMAMUX_0->CHCFG[0] |= DMAMUX_CHCFG_SOURCE(46); //===== eDMA =====// // 1. Write to the CSR if a configuration other than the default is wanted. // 2. Write the channel priority levels to the CHn_PRI registers and group priority levels to the CHn_GRPRI registers if a // configuration other than the default is wanted. // 3. Enable error interrupts in the CHn_CSR[EEI] registers if they are wanted. // 4. Write the 32-byte TCD for each channel that may request service. // CH0_SBR_MID: Default master id -> 0b10 // Source address -> SPI receive buffer IP_TCD->TCD0_SADDR = IP_LPSPI_1->RDR; // Destination address IP_TCD->TCD0_DADDR = rxBuffer; // Source Address Offset IP_TCD->TCD0_SOFF = 4; // Destination Address Offset IP_TCD->TCD0_DOFF = 4; // Source size: 32-bit IP_TCD->TCD0_ATTR |= DMA_TCD_TCD0_ATTR_SSIZE(0b10); // Destination size: 32-bit IP_TCD->TCD0_ATTR |= DMA_TCD_TCD0_ATTR_DSIZE(0b10); // 4 byte transfer IP_TCD->NBYTES0.TCD0_NBYTES_MLOFFNO = 4; // Current Major Loop Count IP_TCD->CITER0.TCD0_CITER_ELINKNO = 1; // Beginning Major Loop Count IP_TCD->BITER0.TCD0_BITER_ELINKNO = 1; // Interrupt after transfer is complete IP_TCD->TCD0_CSR |= DMA_TCD_TCD0_CSR_INTMAJOR_MASK; // Enable interrupt __NVIC_ClearPendingIRQ(DMATCD0_IRQn); __NVIC_SetPriority(DMATCD0_IRQn, 0); __NVIC_EnableIRQ(DMATCD0_IRQn); // 5. Enable any hardware service requests via the CHn_CSR[ERQ] registers. IP_TCD->CH0_CSR |= DMA_TCD_CH0_CSR_ERQ_MASK; } void DMATCD0_Handler(void) { // Print rxBuffer printf("rxBuffer: %ld", rxBuffer); // Clear interrupt request IP_TCD->CH0_INT = 1; } 回复：S32K344裸机DMA初始化 谢谢你的帮助，它有效 回复：S32K344裸机DMA初始化 你好， 我禁用了源地址偏移，但没有任何变化。EDMA 中没有错误标志。我在不可缓存的 SRAM 中有缓冲区。 NVIC->ISER[0] = 0x10; NVIC->ISER[5] = 0x40; NVIC->ICER[0] = 0x10; NVIC->ICER[5] = 0x40 EDMA->CSR = 0x300000 EDMA 和 NVIC 中的其他寄存器字段为空。

S32K344ベアメタルDMAの初期化 DMA init に問題があります。ベアメタル プログラミングを使用して DMA を初期化できませんでした。割り込みは呼び出されず、データは渡されません。その間、SPIからの割り込みは機能しています。DMAの設定を確認していただけますか?また、「IP_LPSPI/n/->DER」レジスタに「LPSPI_DER_RDDE」ビットを設定しました。これにより、受信データの DMA が設定されます。 void DMA_Init(volatile uint32_t rxBuffer) { /* For remaining S32K3xx devices: DMAMUX_0 channel 0-15 and DMAMUX_1 channel 0-15 are mapped to eDMA Transfer Control Descriptor(TCD) 0-15 and eDMA Transfer Control Descriptor(TCD) 16-31, respectively */ // TCD register init IP_TCD->TCD0_SADDR = 0U; IP_TCD->TCD0_SOFF = 0; IP_TCD->TCD0_ATTR = 0U; IP_TCD->NBYTES0.TCD0_NBYTES_MLOFFNO = 0U; IP_TCD->NBYTES0.TCD0_NBYTES_MLOFFYES = 0U; IP_TCD->TCD0_SLAST_SDA = 0; IP_TCD->TCD0_DADDR = 0U; IP_TCD->TCD0_DOFF = 0; IP_TCD->CITER0.TCD0_CITER_ELINKNO = 0U; IP_TCD->CITER0.TCD0_CITER_ELINKYES = 0U; IP_TCD->TCD0_DLAST_SGA = 0; IP_TCD->TCD0_CSR = 0U; IP_TCD->BITER0.TCD0_BITER_ELINKNO = 0U; IP_TCD->BITER0.TCD0_BITER_ELINKYES = 0U; //===== DMA MUX =====// // Enable a source without periodic triggering // 1. Determine the DMA channel with which the source is associated. // LPSPI1 DMA RX Request -> Source 46 // 2. Write 0 to CHCFGn[ENBL] and CHCFGn[TRIG] of the DMA channel. IP_DMAMUX_0->CHCFG[0] &= ~DMAMUX_CHCFG_ENBL_MASK; IP_DMAMUX_0->CHCFG[0] &= ~DMAMUX_CHCFG_TRIG_MASK; // 3. You can enable the DMA channel at this point. IP_DMAMUX_0->CHCFG[0] |= DMAMUX_CHCFG_ENBL_MASK; // 4. Select the source to be routed to the DMA channel. IP_DMAMUX_0->CHCFG[0] |= DMAMUX_CHCFG_SOURCE(46); //===== eDMA =====// // 1. Write to the CSR if a configuration other than the default is wanted. // 2. Write the channel priority levels to the CHn_PRI registers and group priority levels to the CHn_GRPRI registers if a // configuration other than the default is wanted. // 3. Enable error interrupts in the CHn_CSR[EEI] registers if they are wanted. // 4. Write the 32-byte TCD for each channel that may request service. // CH0_SBR_MID: Default master id -> 0b10 // Source address -> SPI receive buffer IP_TCD->TCD0_SADDR = IP_LPSPI_1->RDR; // Destination address IP_TCD->TCD0_DADDR = rxBuffer; // Source Address Offset IP_TCD->TCD0_SOFF = 4; // Destination Address Offset IP_TCD->TCD0_DOFF = 4; // Source size: 32-bit IP_TCD->TCD0_ATTR |= DMA_TCD_TCD0_ATTR_SSIZE(0b10); // Destination size: 32-bit IP_TCD->TCD0_ATTR |= DMA_TCD_TCD0_ATTR_DSIZE(0b10); // 4 byte transfer IP_TCD->NBYTES0.TCD0_NBYTES_MLOFFNO = 4; // Current Major Loop Count IP_TCD->CITER0.TCD0_CITER_ELINKNO = 1; // Beginning Major Loop Count IP_TCD->BITER0.TCD0_BITER_ELINKNO = 1; // Interrupt after transfer is complete IP_TCD->TCD0_CSR |= DMA_TCD_TCD0_CSR_INTMAJOR_MASK; // Enable interrupt __NVIC_ClearPendingIRQ(DMATCD0_IRQn); __NVIC_SetPriority(DMATCD0_IRQn, 0); __NVIC_EnableIRQ(DMATCD0_IRQn); // 5. Enable any hardware service requests via the CHn_CSR[ERQ] registers. IP_TCD->CH0_CSR |= DMA_TCD_CH0_CSR_ERQ_MASK; } void DMATCD0_Handler(void) { // Print rxBuffer printf("rxBuffer: %ld", rxBuffer); // Clear interrupt request IP_TCD->CH0_INT = 1; } Re: S32K344 ベアメタル DMA の初期化 助けてくれてありがとう、それは動作します Re: S32K344 ベアメタル DMA の初期化 こんにちは ソース アドレス オフセットを無効にしましたが、何も変更されていません。EDMA にはエラー フラグはありません。キャッシュ不可能な SRAM にバッファがあります。 NVIC->ISER[0] = 0x10;NVIC->ISER[5] = 0x40;NVIC->ICER[0] = 0x10;NVIC->ICER[5] = 0x40 EDMA->CSR = 0x300000 EDMA および NVIC の他のレジスター・フィールドはヌルです。

NHS3152 上的 DAC 产生三角信号的 ADC 采集问题 我正在使用NHS3152设备通过 DAC 生成三角波形，并使用 ADC 测量该信号。配置如下 使用带有参数 ADCDAC_IO_ANA0_5 的函数 Chip_ADCDAC_SetMuxDAC 在引脚ANA0_5上配置 DAC 输出。 使用 Chip_ADCDAC_SetMuxADC 和参数 ADCDAC_IO_ANA0_3 在引脚ANA0_3上配置 ADC 输入。 一根电缆将 ANA0_5 物理连接到 ANA0_3，以使信号循环。 技术细节： 两个引脚的 IOCON 配置均设置为模拟模式 (IOCON_FUNC_1)。 DAC 在SINGLE_SHOT模式下运行，以在每次写入时更新输出，但切换到CONTINUOUS模式并不能解决问题 - 它只会稍微影响信号质量。 ADC 以连续模式运行，检测阈值设置为1500 （LOW_THRESHOLD）和2000 （HIGH_THRESHOLD）。 代码为三角波形（范围从 DAC_MIN_VALUE 到 DAC_MAX_VALUE）生成查找表 (LUT)，并且 16 位计时器定期触发 DAC 更新。 尽管输出上可以清晰地观察到三角信号，但没有触发 ADC 中断，也没有记录 ADC 转换结果。 采取的故障排除步骤： 我已验证 MUX 选择功能（Chip_ADCDAC_SetMuxADC 和 Chip_ADCDAC_SetMuxDAC）使用正确的通道（ADC 为通道 3，DAC 为通道 5），如文档中所述（UM10876 手册第 9.4 章，图 90）。 我确认两个引脚的 IOCON 设置都正确设置为模拟模式（IOCON_FUNC_1），并且连接 ANA0_5 和 ANA0_3 的电缆已正确安装并具有公共接地。 我测试了修改 ADC 中断例程中 ADC 转换就绪标志（ADCDAC_INT_CONVERSION_RDY_ADC）的检查，但这并没有改变行为。 除了信号质量略有变化外，在 SINGLE_SHOT 和 CONTINUOUS 之间更改 DAC 模式对问题没有显著影响。 请求协助： 我希望您能帮助我了解： 考虑到它采用循环调度程序运行，通过模拟多路复用器使用两个不同引脚的当前配置对于 NHS3152 上的共享 ADCDAC 块是正确的。 还有一些其他限制（例如时序或配置序列问题）可能会阻止在此设置中触发 ADC 中断。 其他修改方法（例如以单次模式测试 ADC 或对 ADC 和 DAC 使用相同通道）可以解决该问题。 请参阅附件中用于此配置的完整代码。提前感谢您的帮助和建议。 问候， 托马斯 回复：NHS3152 上 DAC 生成三角信号的 ADC 采集问题 我想向您更新我所提交的票的情况。主要问题如下： DAC 产生的三角波形太快。这个快速信号没有给 ADC 足够的时间来正确捕获值。 我错误地使用了中断处理程序的错误名称。它必须命名为ADC_IRQHandler(void)而不是ADCDAC_IRQHandler(void) 。 降低频率（或增加每个周期的样本数）并重命名中断例程后，ADC 开始按预期工作。

关于 MPC5775B 的 MCAL BSP 支持咨询 尊敬的恩智浦支持团队，     我们最近购买了 MPC5775B BMS 和 VCU 参考设计(RDVCU5775EVM) 假设支持 MCAL BSP适用于 MPC5775B微控制器。但是，我无法在您的网站上找到针对此特定控制器的任何 MCAL 包。 您能否指导我在哪里可以获得 此 MCU 有MCAL BSP吗？如果它尚未公开，请让我知道访问它的过程。 期待您的回复。 回复：关于 MPC5775B 的 MCAL BSP 支持问题 感谢提供的所有解决方案。它起作用了，现在我可以配置 MCAL 的驱动程序了。 但我唯一关心的组件是 RTOS（免费 RTOS）。当不建议使用 SDK 时，我现在该如何应用 RTOS 功能？我只能使用 SDK 的 RTOS 功能吗？或者最好的方法是什么？ 回复：关于 MPC5775B 的 MCAL BSP 支持问题 你好，请帮我解决以上问题 回复：关于 MPC5775B 的 MCAL BSP 支持问题 好的！谢谢。也请帮助我解决其他问题 回复：关于 MPC5775B 的 MCAL BSP 支持问题 请帮助我解决这些问题 回复：关于 MPC5775B 的 MCAL BSP 支持问题 你好， 我正在使用 MPC5775B 微控制器，并已为该设备导入了 Power Architecture SDK。我现在需要一个兼容的 MCAL 包来配置驱动程序并与 RTOS 集成。 请您确认一下： Power Architecture SDK 是否支持与 MCAL 集成？ 是否有适用于 MPC5775B 的官方 MCAL 包？如果有的话，我可以在哪里下载它？ 将 MCAL 与 EB tresos Studio 集成以符合 AUTOSAR 要求的推荐方法是什么？ 任何指导或文档参考都将不胜感激。 提前致谢！ 回复：关于 MPC5775B 的 MCAL BSP 支持问题 您好，我获得了 tresos studio 的产品密钥。我激活了许可证，但无法获取 .lic文件广告现在无法访问 tresos 工作室。请帮助我 回复：关于 MPC5775B 的 MCAL BSP 支持问题 谢谢您的回复。 回复：关于 MPC5775B 的 MCAL BSP 支持问题 感谢您的快速回复， 您确定 MPC5777C 的 MCAL 满足我们对 MPC5775B 的要求吗？MCU系列号不同。

MCAL BSP for MPC5775B サポートに関するお問い合わせ NXPサポートチームの皆様へ     私たちは最近、 MPC5775B マイクロコントローラにサポート MCAL BSP が利用可能であるという前提で、 MPC5775B BMSおよびVCUリファレンスデザイン(RDVCU5775EVM)を購入しました。しかし、私はこの特定のコントローラーのあなたのウェブサイトでMCALパッケージを見つけることができませんでした。 このMCUの MCAL BSP をどこで入手できるかについて、ガイダンスを提供していただけますか?公開されていない場合は、アクセスするプロセスをお知らせください。 ご回答をお待ちしております。 Re: MPC5775BのMCAL BSPサポートに関するお問い合わせ 提供されたすべての解決策に感謝します。それはうまくいきました、そして今私はMCALのドライバーを構成することができます。 しかし、私が懸念している唯一のコンポーネントはRTOS(Free RTOS)についてです。SDKの使用が推奨されていない場合、RTOS機能をどのように適用できますか?SDKのRTOS機能のみを使用することはできますか、それともどのようなアプローチが最善のアプローチでしょうか? Re: MPC5775BのMCAL BSPサポートに関するお問い合わせ こんにちは、上記の質問で私を助けてください Re: MPC5775BのMCAL BSPサポートに関するお問い合わせ 了解致しました！！感謝。親切に私の他の質問についても私を助けてください Re: MPC5775BのMCAL BSPサポートに関するお問い合わせ 親切にこれらの質問で私を助けてください Re: MPC5775BのMCAL BSPサポートに関するお問い合わせ こんにちは MPC5775B マイクロコントローラを使用しており、このデバイス用の Power Architecture SDK をインポートしました。ドライバーを構成し、RTOSと統合するために、互換性のあるMCALパッケージが必要になりました。 確認していただけますか: Power Architecture SDK は MCAL との統合をサポートしていますか? MPC5775Bできる公式のMCALパッケージはありますか?その場合、どこでダウンロードできますか? AUTOSARに準拠するために、MCALをEB tresos Studioと統合するための推奨されるアプローチは何ですか? ガイダンスやドキュメントの参照があれば幸いです。 よろしくお願いします! Re: MPC5775BのMCAL BSPサポートに関するお問い合わせ こんにちは、tresos studioのプロダクトキーを取得しました。ライセンスをアクティブ化しましたが、.lic を取得できませんファイル広告がトレソススタジオにアクセスできなくなりました。親切に助けてください Re: MPC5775BのMCAL BSPサポートに関するお問い合わせ 返信ありがとうございます。 Re: MPC5775BのMCAL BSPサポートに関するお問い合わせ 迅速な返信をありがとう、 MPC5777CのMCALは、MPC5775Bの要件を満たしていると確信していますか?MCUのシリーズ番号が異なります。

S32G3 Linux BSP 35 で ttyLF1 を有効にする方法 こんにちは、NXPチームの皆様、 S32G399ardb3を参照し、カスタムボードを設計し、Linux BSP 35を使用しました。 当社の S32G3 カスタマイズボードはPCから UARTデータを受信できません が、PCはS32G3からUARTデータを受信できます PINMUX FUNC Xがデバイスツリーでどのような機能を表しているかをどうやって知ることができますか? UART2を有効にした場合、 PINMUX FUNC Xはどのように設定すればよいですか? 以下はデバイスツリーです(BSP 43に従って変更します) uart1_pins: uart1_pins { uart1_pins_grp0 { pinmux = FUNC2)>; // PC_08 output-enable; slew-rate = ; }; uart1_pins_grp1 { pinmux = FUNC0)>; // PC_04 input-enable; slew-rate = ; }; uart1_pins_grp2 { pinmux = FUNC2)>; }; }; &uart1 { pinctrl-0 = <&uart1_pins>; pinctrl-names = "default"; status = "okay"; }; S32G3のコマンドを使用してデータを送信します echo "Test" > /dev/ttyLF1 私のPCは、受信したデータにコマンドを使用できます cat /dev/ttyUSB1 ありがとうございます 回复: S32G3 Linux BSP 35 で ttyLF1 を有効にする方法 こんにちは、NXPチームの皆様、 現在正常に動作しています。 しかし、stty コマンドを使用せずにボーレートを設定するにはどうすればよいですか? ノート: ttyLF1 はシリアルコンソールではなく内部 UART です 回复: S32G3 Linux BSP 35 で ttyLF1 を有効にする方法 こんにちは、NXPチームの皆様、 私は これらの問題をS32G3_IOMUX 2で見つけました。xlsx ファイル PC_04 PINMUX関数「LINデータ受信」SSSは0000_0100なので、FUNC4である必要があります uart1_pins_grp2 { pinmux = FUNC4)>; }; ありがとうございます