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L4Re compile fail Hi, NXP Experts, According to the description of the L4Re build environment in section ‘5.9.2.3 Build Environment‘ of the ‘UG_S32ZE_GreenVIP.pdf‘, the L4Re source code pulled via Hammer has not been modified. However, when attempting to compile the project, the following error is reported. How to solve this issue?   Re: L4Re compile fail Thanks, Liek. L4Re works good now. Re: L4Re compile fail Hi Siyan, Seems the SW package on github is not correct. I already send you the one which is OK on my side.
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MCUXpreso は J-Link または CMSIS-DAP 経由で MIMXRT1060-EVKB ボードに接続できません これはMIMXRT1060-EVKBでの私の最初の試みです。例の「helo word」を実行しようとしましたが、プログラムをアップロードできませんでした。J-Link、CMSIS-DAPもMIMXRT1060-EVKBには接続しません。次に何をすべきかわかりません。私に何ができるか助けてください。
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Unable to use Codewarrior debugging for BL2 (button grayed out) Hello, I am using an LS1046ardb board, and I'm attempting to use Codewarrior to debug my BL2 image. I'm booting from qspi flash, and I would like to attach to the running program. I've been following this guide for U-Boot: https://community.nxp.com/t5/CodeWarrior-for-QorIQ-Knowledge/Use-CodeWarrior-for-ARMv8-to-Debug-U-boot-and-Linux-Kernel-and/ta-p/1114872 The issue is when I setup the debug configuration profile I get an error message and the "debug" button is grayed out: As you can see, I'm trying to use the "GDB hardware debugging" configuration with my bl2.elf symbol image, but cannot select the debug button. My TAP works correctly, I am able to inspect the running system and read/write the flash, so I don't understand why this doesn't work. Please find my codewarrior version below: Thank you for your help! Re: Unable to use Codewarrior debugging for BL2 (button grayed out) I have found the solution. The problem is I had the target connection activated under the "Target connections" tab. The solution was to go to the "Target Connections" tab, then select the active connection, then press "Deactivate", then import the bl2.elf using the steps provided by @yipingwang. The target connection will be specified in the debug configuration under the "Debugger" tab, and will automatically connect when the debug configuration is run. So there is no need to use the "Target Connections" window and there should be no active connection.   Re: Unable to use Codewarrior debugging for BL2 (button grayed out) Please open CodeWarrior IDE in a new workspace, then import bl2.elf to create a bare board project. Then click Run->Debug Configurations, the debug button should be active. If your problem persists, please try to install CodeWarrior for ARMv8 on another PC to do verification. Re: Unable to use Codewarrior debugging for BL2 (button grayed out) @yipingwang  Thank you for the document. Unfortunately I am facing the same error message and the button is still greyed out Re: Unable to use Codewarrior debugging for BL2 (button grayed out) @yipingwang  Thank you for the document. Unfortunately I am facing the same error and the button is still greyed out: Re: Unable to use Codewarrior debugging for BL2 (button grayed out) For atf debugging, please refer to my latest step by step document. https://community.nxp.com/t5/Layerscape-Knowledge-Base/Debugging-ATF-and-u-boot-with-CodeWarrior-for-ARMv8/ta-p/1684233
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SJA1110 SDK installation Hi I want to install SJA1110 RTD SDK. i've installed S32DS FOR S32 PLATFORM V3.5.12, I have downloaded and installed SW32G_SJA11XX_ETH_SWITCH_4.4_1.0.0_DS_updatesite_D2306.zip, SW32SJA1110_XJA11XX_ETH_PHY_4.4_1.0.5_DS_updatesite_D2405.zip, SJA11XX_RTD_4.4_1.0.1_P01_D2404_DS_updatesite.zip, SJA11XX_RTD_4.4_1.0.1_D2312_DS_updatesite.zip, SJA11XX_ETH_SWITCH_4.4_1.0.0_DS_updatesite_D2306.zip, but I still can't find the ‘switch_config_s32g_vnp_rdb’ examples in Re: SJA1110 SDK installation Hi, I struggled using the SDK because some (outdated?) documents told me it should show up in the S32 Design Studio for S32 Platform Help -> S32 DS Extensions and Updates list. This is NOT the case. I needed to install the S32 SDK via file extraction of the .zip and then Help -> Install new software ... -> "Add..." and then "Local...". I did not try "Archive..." and .zip selection, may be this works also. Best regards Re: SJA1110 SDK installation Hi,  this example is within SJA1110 SDK, can be downloaded from https://www.nxp.com/webapp/swlicensing/sso/downloadSoftware.sp?catid=SWSJA1110-SDK01E, latest version is S32 SDK for SJA1110 RTM 1.0.2. Download update zip package and add it to your S32DS. Read package release note document for the info about installation. BR, Petr
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MCUXpreso cannot connect to MIMXRT1060-EVKB board via J-Link or CMSIS-DAP This is my first attempt with MIMXRT1060-EVKB. I tried to run the example "helo word" and I could not upload the program. J-Link and CMSIS-DAP do not connect to MIMXRT1060-EVKB either. I do not know what to do next. Please help me what I can do. Re: MCUXpreso cannot connect to MIMXRT1060-EVKB board via J-Link or CMSIS-DAP Thanks for the quick response. A little effort and I solved the problem. Everything was in the article "Using J-Link with MIMXRT1060-EVKB or MIMXRT1040-EVK" https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/Using-J-Link-with-MIMXRT1060-EVKB-or-MIMXRT1040-EVK/ta-p/1452717 J-Link works ok. Ryszard Re: MCUXpreso cannot connect to MIMXRT1060-EVKB board via J-Link or CMSIS-DAP Hi @Ryszard  Are you using the MCUXpresso IDE? If you use it. You can download the SDK_2_15_100_MIMXRT1060-EVKB SDK on the NXP official site. Select Board | MCUXpresso SDK Builder (nxp.com) And import the downloaded SDK in MCUXpresso. And import the example in SDK. And click the debug to run the hello world. Hope this will help you. BR Hang
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SJA1110 SDK安装 您好,我想安装 SJA1110 RTD SDK。我已经安装了S32DS FOR S32 PLATFORM V3.5.12,我已经下载并安装了 SW32G_SJA11XX_ETH_SWITCH_4.4_1.0.0_DS_updatesite_D2306.zip、SW32SJA1110_XJA11XX_ETH_PHY_4.4_1.0.5_DS_updatesite_D2405.zip、SJA11XX_RTD_4.4_1.0.1_P01_D2404_DS_updatesite.zip,SJA11XX_RTD_4.4_1.0.1_D2312_DS_updatesite.zip、SJA11XX_ETH_SWITCH_4.4_1.0.0_DS_updatesite_D2306.zip,但我仍然无法在《S32G-VNP-RDB2以太网启用指南》中找到“switch_config_s32g_vnp_rdb”示例 回复:SJA1110 SDK 安装 你好, 我在使用 SDK 时遇到了困难,因为一些(过时的?)文档告诉我它应该出现在 S32 Design Studio 的 S32 平台帮助 -> S32 DS 扩展和更新列表中。 事实并非如此。我需要通过提取.zip文件来安装S32 SDK然后帮助->安装新软件...->“添加...”然后“本地...”。我没有尝试“存档...”和.zip选择,也许这也是有效的。 此致
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Change HSE Lifecycle Hi, I'm developing software based on S32K3xx Demo app. In order to Update Secure Life Cycle, ADKP need to be is programmed. After ADKP is programmed, the secure debug feature is enabled. I got 2 questions: Does the secure debug feature always enabled when HSE Life cycle is OEM_PROD/IN_FIELD? Can secure debug feature be disabled when HSE Life cycle is OEM_PROD/IN_FIELD? (No debug authorization script needed) Thanks a lot. Re: Change HSE Lifecycle Hi @HaiHoangSoftware  Here are two screenshots from the manual:   So, it is mandatory to configure ADKP when advancing the life cycle and it's not possible to disable secure debug because it's programmed to OTP. Regards, Lukas
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SHE Keys configuration in S32K3xx Hello, I am using Crypto_43_HSE module from RTD v5.0.0, and I would like to configure the SHE keys according to the AUTOSAR standard. Is there any example or demo project provided by NXP that shows how to do so with EB TResos or with the S32DS Configuration tool (.mex) file? I did not find anything useful in the available examples. Re: SHE Keys configuration in S32K3xx Many thanks. Re: SHE Keys configuration in S32K3xx Hi @strofald  I have an example for older RTD 2.0.2 which uses SHE keys. See please attachment. Regards, Lukas
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S32K344-If the DERR_SUP field is set to 1, will a single-bit error be repaired? Hello I read in the chip manual that if the DERR_SUP field in register PFCR4 is set to 1, single-bit and double-bit ECC events will not be reported. Will single-bit errors be repaired? BestRegards, Simon Re: S32K344-If the DERR_SUP field is set to 1, will a single-bit error be repaired? Yes, it has nothing to do with a single-bit ECC. Regards, Daniel Re: S32K344-If the DERR_SUP field is set to 1, will a single-bit error be repaired? Hello @danielmartynek  Thank you for your answer. I have a similar question: If the DMEEE bit in the same register PFCR4 is set, will a single-bit error be repaired? BestRegards, Simon Re: S32K344-If the DERR_SUP field is set to 1, will a single-bit error be repaired? Hi @Simon-Liu, Single bit errors are still corrected. Regards, Daniel
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Fs26 keeps mcu(s32k344-wb) in sleep mode. Hi, Some time ago i've uploaded the S32k3_wb_f26 example to the whiteboard. It worked! I could press buttons to toggle sleep mode. But then I pressed the wrong button(s). And now I can't wake up my whiteboard ( S32K344-WB)  My board looked like this; for the jumpers. You can also check the led on the board. If I measure the FS26_VLDO1 on J7 (pin2), I get 5.0v(So the FS26 is powering LDO1). When removing the Jumper on J89. The following lights up  But then the MCU reset(JTAG_RST(PTA5_MCU_RESETB)) keeps high. Even when pulled low(by pressing the SW1 btn)? When measuring RSTB on the FS26 its at a low level; same as for the FS0B, which states it is in error mode? (nr off errors exceeds allowed number of errors). Re: Fs26 keeps mcu(s32k344-wb) in sleep mode. Yea you're right... VCC2_5V0 is pulling 0.8A. And the FS26 gets really hot.  thnx for the help. Re: Fs26 keeps mcu(s32k344-wb) in sleep mode. As long as VDD_HV_A is connected to FS26_VLDO1, D11 is off. I'm afraid that VDD_HV_A consumes too much current (maybe S32K3 is damaged), causing the FS26_VLDO1 voltage to drop and D11 to turn off. It is recommended to measure the FS26_VLDO1 voltage. Or measure the current consumed by VDD_HV_A through J89 to see if it is too large. Re: Fs26 keeps mcu(s32k344-wb) in sleep mode. 1. I was testing Standby mode. 2. LED1(D28 PTF8) and LED2(D29 PTF9) are always off. Even when rebooting. 3. Yes, ive got an 12V 1A power supply. (i dont turn on the HB200X) 4. When measuring pin 2 of J7 i get 5V. TP2 does generate an interrupt.   Re: Fs26 keeps mcu(s32k344-wb) in sleep mode. Hi Please read the description of this demo application. Connect the wires as described below. 1. STANDBY mode or LPOFF mode test? 2. After power-on, MCU is normal running. Then user need push button SW3(WB) to trigger entry of Standby mode or LPOFF mode depending on MACRO definition. If you do not press SW3, what is the status of LED1(D28 PTF8) and LED2(D29 PTF9)? I see that the program turns off LED1(D28 PTF8) and LED2(D29 PTF9) to indicate MCU enters Standby only after pressing SW3. 3. Did you apply 12v and then turn on the switch SW10? 4. Strange, I don't see D11 light up red. According to what you said, FS26_VLDO1 has measured 5V from J7 or J89. 5. Do not remove J89, this power the VDD_HV_A which is used to support standby mode. Best Regards, Robin ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "ACCEPT AS SOLUTION" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. -------------------------------------------------------------------------------
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S32K311 Bootloader Code Example Similar to Shared Link Hi , I'm currently working on a project using the NXP S32K311 and I'm looking for a bootloader code example for this MCU. I came across a useful implementation elsewhere, and I'm trying to find something similar here on the NXP Community or through official resources. The following link is the project I used. Unified bootloader Demo - NXP Community Specifically, I'm looking for: A working bootloader for S32K311 (preferably CAN-based) Any guidance or documentation related to flash routines, Memory layout and linker configuration (for application and bootloader), or security handling in bootloader Proper clock configuration (for system/core/peripherals) Correct pin initialization (especially for UART/CAN interfaces used for communication) Startup/initialization issues to watch for (e.g., ITCM, MPU, etc.) If anyone has worked on something similar or can point me to a shared project, SDK example, or GitHub repo, I’d really appreciate it. Thanks in advance for your help! Re: S32K311 Bootloader Code Example Similar to Shared Link Hi @DiaDev, There are some examples for S32K312 for a bootloader to application jump in this post: Example S32K312 Bootloader to Application Jump DS3.5 RTD300 - NXP Community. But as far as I know, the unified bootloader is the only example with CAN support. There are no examples specifically for the S32K311, since we need to test them in our evaluation boards, but the S32K312 derivative is fairly similar, the Unified Bootloader and the examples I shared previously both support the S32K312. You must port the example over to the S32K311 yourself. If you have any issues while implementing CAN or the bootloader, you can ask in the community and we will help you. But, if you have questions about the application itself, you can contact the owner through their GitHub page: GitHub - ecubus/EcuBus-Pro: A powerful automotive ECU development tool. UDS, CAN-TP, DOIP, LIN , Script(TS) like CAPL, HIL Test. Best regards, Julián
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imx8M mini Quad LPDDR4 Yocto project Hi  I tried to build the image for Myir JX8MMA7 based on imx8m Mini quad, following the users guide i.MX Yocto Project User's Guide (nxp.com.cn) revision 6.6.3. But there is something wrong with checksum. i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Re: imx8M mini Quad LPDDR4 Yocto project this fetch error is related to the network, pls check your network or firewall and try again, sometimes you need try to download more times
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S32G3内存支持列表 嗨,恩智浦的同事们 我看到数据表中的 S32G3 支持 DDR ,NOR Flash 和 EMMC,但您能否提供经过兼容性测试的 DDR 和其他存储器的列表? 如果市场上任何符合 LPDDR4 协议的 DRAM 都可以与最大密度为 4GB 的 S32G3 连接,您是否没有进行过适应性测试? 期待回复。 谢谢! 回复:S32G3内存支持列表 ----这个不太常规,虽然LPDDR4协议是标准的,但是各个DDR厂家也确实有些差异,这也是为什么很多SOC提供了列表,理论上可以,但是并不适合直接使用的原因。 ----其他EMMC和NOR也是这样吗?
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S32G3 memory support list Hi, NXP colleagues I see DDR ,NOR Flash and EMMC are supported by S32G3 in datasheet, but can you provide a list of DDR and other memories that have been tested for compatibility? If any LPDDR4 protocol compliant DRAM in the market can be interfaced with  S32G3 with max density of 4GB ,have you not done fitness testing? Expecting a reply. Thank you . Re: S32G3 memory support list Hello, @Chenxu1  Thanks for your kindly suggestions. BR Chenyin Re: S32G3 memory support list Hi ,  Please make suggestions to your internal company, because the memory fitting test  of DDR and EMMC is very important to us. Thanks. Re: S32G3 memory support list Hi, @Chenxu1  Thanks for the reply. Yes, from the information I could understand, there are not such lists for EMMC/Nors. I apologize for the inconvenience. BR Chenyin Re: S32G3 memory support list ----This is not very conventional, although the LPDDR4 protocol is standard, but each DDR manufacturer also does some differences, which is the reason why many SOCs provide list, in theory, but not suitable for direct use. ----Is this true of other EMMCs and NOR? Re: S32G3 memory support list Hello, @Chenxu1  Thanks for the questions. Sorry that seems there is not such list, NXP recommends any LPDDR4 DRAM of 4GB max density which is complaint with LPDDR4 protocol and follow JEDEC specs. Best Regards Chenyin
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s32k314 Lpspi_Ip_SyncTransmit and Lpspi_Ip_AsyncTransmit transmit issue I am testing SPI communication on S32K314. It was confirmed that the correct data was output through Lpspi_Ip_SyncTransmit.        status = Lpspi_Ip_SyncTransmit(&SLAVE_EXTERNAL_DEVICE, pTxData, pRxData, length, 1000);     if( LPSPI_IP_STATUS_SUCCESS == status ) {         retval = true;     } However, even if Interrupt is set, the Finish interrupt does not occur.         status = Lpspi_Ip_Init( &Lpspi_Ip_PhyUnitConfig_SpiPhyUnit_0_Instance_0 );         if( status != LPSPI_IP_STATUS_SUCCESS ) {         }         IntCtrl_Ip_InstallHandler(LPSPI0_IRQn, Lpspi_Ip_LPSPI_0_IRQHandler, NULL_PTR);         IntCtrl_Ip_EnableIrq(LPSPI0_IRQn);       Lpspi_Ip_UpdateTransferMode(SLAVE_EXTERNAL_DEVICE.Instance, LPSPI_IP_INTERRUPT);     So, we are trying to communicate through Lpspi_Ip_AsyncTransmit. However, correct data is not output through Lpspi_Ip_AsyncTransmit. Values ​​0x01, 0x02 ~ 0x20 are being transmitted as test values, but it appears that only the first 3 bytes are transmitted as correct values, and the rest are transmitted as garbage values. If there is anything you can help me with, please do so. Re: s32k314 Lpspi_Ip_SyncTransmit and Lpspi_Ip_AsyncTransmit transmit issue Yes, I solved the problem by using RM. In order to use DMA in SPI, dmamux must be used, but my project did not use mcal. Since there is no way to add dmamux in projects that do not use mcal in SDK components, I had no choice but to add mcal. I confirmed that it works well by registering dmamux in rm. Re: s32k314 Lpspi_Ip_SyncTransmit and Lpspi_Ip_AsyncTransmit transmit issue Hi Please refer to the Example S32K312 SPI Transmit & Receive Using DMA DS3.5 RTD300 Lpspi_Ip_AsyncTransmit is used in this project. Best Regards, Robin ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. ------------------------------------------------------------------------------- Re: s32k314 Lpspi_Ip_SyncTransmit and Lpspi_Ip_AsyncTransmit transmit issue Thank you for the source code. I am referring to it. Since our project doesn't use MCAL, we don't use Rm. Is it necessary to use the Cache_Ip_InvalidateByAddr function? Currently, I am transmitting using the Lpspi_Ip_AsyncTransmit function, but when I read it with Lpspi_Ip_GetStatus, LPSPI_IP_FIFO_ERROR occurs. Do you know how to resolve LPSPI_IP_FIFO_ERROR? Re: s32k314 Lpspi_Ip_SyncTransmit and Lpspi_Ip_AsyncTransmit transmit issue I’m sorry for delayed response, we are heavily overloaded now. Cache_Ip_InvalidateByAddr is for when DMA is used. If you don’t use DMA, then there is no need to call it. If RTD 3.0.0 and DMA is used, then DMAMUX must be configured in Rm regardless of whether MCAL is used. (Rm->RmConfigSet->Dma Mux) Would you please send me a simplified test project privately? Re: s32k314 Lpspi_Ip_SyncTransmit and Lpspi_Ip_AsyncTransmit transmit issue Install another C:\NXP\S32DS.3.5_RTD300 separately Then install RTD3.0.0. Re: s32k314 Lpspi_Ip_SyncTransmit and Lpspi_Ip_AsyncTransmit transmit issue But I installed RTD4.0, and this routine was not found Re: s32k314 Lpspi_Ip_SyncTransmit and Lpspi_Ip_AsyncTransmit transmit issue Is there an SDK for RTD3.0 installed? Can it coexist with 4.0? Re: s32k314 Lpspi_Ip_SyncTransmit and Lpspi_Ip_AsyncTransmit transmit issue Can you send me a sample code? I'm also working on a SPI project recently and have been having difficulties. I'd like to learn from it. Re: s32k314 Lpspi_Ip_SyncTransmit and Lpspi_Ip_AsyncTransmit transmit issue Could you please send me the RTD3.0 file? I can't find it on the official website. Also, do you mean installing two S32DS software?
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s32k314 Lpspi_Ip_SyncTransmit issue Test SPI communication using the Lpspi_Ip_SyncTransmit issue in S32K314 In the Freertos development environment, When transmitting SPI data, sometimes corrupted data occurs. 0x7F should be output, but 0x7E seems to be output. Why does this happen? Please let me know if there is anything I need to check. Re: s32k314 Lpspi_Ip_SyncTransmit issue I solved it by modifying the Tx timing in my code. Re: s32k314 Lpspi_Ip_SyncTransmit issue Hi @jwkang, If this is a sporadic occurrence, can you measure the bus with an analog oscilloscope? I see the baudrate is 10MHz. What type of pins do you use? The GPIO AC specification can be found in the DS. Table 26. 5.0V (4.5V - 5.5V) GPIO Output AC Specification Table 27. 3.3V (2.97V - 3.63V) GPIO Output AC Specification Regards, Daniel
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S32k324 bootloader linker (a tale of two linker files) I have a bootloader / application setup on the S32k324. It ran well enough until we needed to change the map to scavenge ram. We are only using core0 at the moment. The second core is disabled. When the linker files match (bootloader (0x400000)to application (0x420080)) there is no issue. I can redefine the offset for the application flash (currently at 0x420080) without issue. If I deviate from the initial sram/itcm/dtcm  settings used in the bootloader to re-purpose the disabled Core1's ram, the application hardfaults. If I load the application from the bootloader (0x400000) offset the application works fine with the new linker file. What would cause the issue? Re: S32k324 bootloader linker (a tale of two linker files) We've found a possible solution and are testing. Added the following to startup_cm7.s /*GetCoreID*/ ldr  r0, =0x40260004 ldr  r1,[r0] /*Disable mpu if enabled*/ movs    r2, #0 mov.w   r0, #3758153728 /* 0xe000e000 */ mov     r1, r2 str.w   r2, [r0, #3476] /* 0xd94*/ ldr  r0, =MAIN_CORE cmp  r1,r0 beq        SetCore0Stack b SetCore1Stack Re: S32k324 bootloader linker (a tale of two linker files) Dtyree, MPU is ARM IP, and hence is documented in the armv7-m architecture reference Does the generic linker (linker_flash_s32k324.ld) work for you? This does not reserve SRAM space for core 1: MEMORY { int_pflash : ORIGIN = 0x00400000, LENGTH = 0x003D4000 /* 4096KB - 176KB (sBAF + HSE)*/ int_dflash : ORIGIN = 0x10000000, LENGTH = 0x00020000 /* 128KB */ int_itcm : ORIGIN = 0x00000000, LENGTH = 0x00008000 /* 32KB */ int_dtcm : ORIGIN = 0x20000000, LENGTH = 0x0000F000 /* 60KB */ int_stack_dtcm : ORIGIN = 0x2000F000, LENGTH = 0x00001000 /* 4KB */ int_sram : ORIGIN = 0x20400000, LENGTH = 0x0002FF00 /* 192KB, needs to include int_sram_fls_rsv */ int_sram_fls_rsv : ORIGIN = 0x2042FF00, LENGTH = 0x00000100 int_sram_no_cacheable : ORIGIN = 0x20430000, LENGTH = 0x0000FF00 /* 64KB, needs to include int_sram_results */ int_sram_results : ORIGIN = 0x2043FF00, LENGTH = 0x00000100 int_sram_shareable : ORIGIN = 0x20440000, LENGTH = 0x00004000 /* 16KB */ ram_rsvd2 : ORIGIN = 0x20444000, LENGTH = 0 /* End of SRAM */ } Note that, ITCM and DTCM do not get extended, as these are local to each core. I would try to link against this file instead of the C0, C1. It should be in the same eclipse/plugins/Platform_ /build_files/ / as the c0 and c1 variants. As for the MPU, It may be a good idea to disable this before configuration as this will prevent issues/faults during configuration itself. The only requirement to write these registers is privileged run mode (which is the default unless you are manually switching to user mode). Best, Bryan Re: S32k324 bootloader linker (a tale of two linker files) When we set the Base address of the application to 0x400000. It loads and runs.  When the application base address is set to 0x420080 and jumped to from the bootloader we get hard fault on memory that was not initialized by the bootloader on first use, or initialization.  I checked the rasr and rbar registers, and can see them being changed in ram. Also see the values within ‘S32_MPU’ being updated with the rasr and rbar value, but have no way of telling if they are actually being applied. However, I see MPU (memory protection unit) is already enabled before we attempt to reconfigure the memory. It then attempts to enable the MPU before reenabling the cache. Do we need to set MPU->CTRL[0] to 0 before we can modify these values? I was unable to find a reference to that in the data sheet. Re: S32k324 bootloader linker (a tale of two linker files) Yes, the application can re-initialize SRAM memory. But if it was already initialized by bootloader, it's unnecessary operation. Re: S32k324 bootloader linker (a tale of two linker files) Is it possible for the application to re-initialize memory if the bootloader runs first? My startup files are based on S32K3_RTD_2_0_0_D2203_ASR_REL_4_4_REV_0000_20220331 for both applications. Re: S32k324 bootloader linker (a tale of two linker files) Hi @dtyree  Similar issues are usually caused by wrong or missing SRAM initialization. It is mandatory to initialize the SRAM as described in the S32K3 reference manual: You can find initialization code in startup_cm7.s: And the addresses are defined in linker file: When the code crashes, you can check the SRAM content. If your debugger shows something like ‘XX‘ or ‘??’ instead of valid data, it’s caused by this SRAM initialization. You need to ensure that whole SRAM is initialized appropriately. If you have bootloader and application or multicore application, you need to decide who and when will initialize the SRAM. Regards, Lukas
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S32G3メモリ対応一覧 こんにちは、NXPの同僚 データシートには S32G3 で DDR、NOR フラッシュ、および EMMC がサポートされているようですが、互換性がテストされた DDR およびその他のメモリのリストを教えてください。 市場に出回っているny LPDDR4プロトコル準拠のDRAMが最大密度4GBのS32G3と接続できる場合、フィットネステストを行っていませんか? 返信を期待しています。 いつもご利用いただき、ありがとうございます。 Re:S32G3メモリサポートリスト ----LPDDR4プロトコルは標準ですが、これはあまり従来型ではありませんが、各DDRメーカーもいくつかの違いがあります。これが、多くのSOCが理論的にはリストを提供していますが、直接の使用には適していません。 ----これは他のEMMCやNORにも当てはまりますか?
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尝试更改设备树文件名后,U-Boot 无法启动 我正准备使用带有 Linux 的 i.MX 8M Plus 片上系统 (SoC) 启动我的定制板。为了实现这一点,我创建了一个元层并建立了一个基于现有 imx8mp-lpddr4-evk.conf 的 custom-machine.conf 文件。此外,我修改了 u-boot-imx_2024.04.bbappend 文件中的 SRC_URI 变量,使其指向我的 GitHub 存储库,其中包含基于原始 u-boot-imx 修改后的 U-Boot 源代码。 在验证新机器和 U-Boot 是否正常运行的初始阶段,我复制或修改了与 i.MX 8MP EVK 相关的文件,并做了最少的改动。我主要更改了电路板名称、地址和其他必要的详细信息,以测试其在 i.MX 8MP EVK 上的运行。您可以在此处查看所有修改。 只要不对从 imx8mp_evk_defconfig 复制的 custom_board_defconfig 文件进行任何修改,我就可以在评估套件 (EVK) 上成功启动 U-Boot。但是,当我尝试仅更改设备树名称时,U-Boot 无法在 EVK 上启动,并且串行控制台上没有输出。 具体变化如下: - CONFIG_DEFAULT_DEVICE_TREE :从“imx8mp-evk”更改为“imx8mp-ifs” - CONFIG_DEFAULT_FDT_FILE :从“imx8mp-evk.dtb”更改为“imx8mp-ifs.dtb” 回复:尝试更改设备树文件名后,U-Boot 无法启动 你好, 请将 arch/arm/dts/imx8mp-evk-u-boot.dtsi 复制到 arch/arm/dts/imx8mp-ifs-u-boot.dtsi,然后重试。 此致, 志明
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S32k324 ブートローダ リンカ (2 つのリンカ ファイルの物語) S32k324にブートローダー/アプリケーションのセットアップがあります。マップをスカベンジラムに変更する必要が生じるまでは、十分に動作しました。現時点ではcore0のみを使用しています。2 番目のコアは無効です。 リンカファイルが一致(ブートローダー(0x400000)とアプリケーション(0x420080))が一致していれば問題ありません。アプリケーションのフラッシュ(現在は0x420080)のオフセットを問題なく再定義できます。ブートローダーで使用される最初のsram / itcm / dtcm設定から逸脱して、無効になっているCore1のRAMを再利用すると、アプリケーションがハードエラーになります。ブートローダー(0x400000)オフセットからアプリケーションをロードすると、アプリケーションは新しいリンカファイルで正常に動作します。 問題の原因は何ですか? Re: S32k324 ブートローダ リンカ (2 つのリンカ ファイルの物語) アプリケーションのベースアドレスを0x400000に設定したとき。ロードして実行します。 アプリケーションのベースアドレスが 0x420080 に設定され、ブートローダーからジャンプすると、最初の使用時または初期化時にブートローダーによって初期化されなかったメモリにハード フォールトが発生します。 rasr レジスタと rbar レジスタを確認したところ、RAM で変更されていることがわかります。 また、'S32_MPU' 内の値が rasr と rbar の値で更新されているのも確認できますが、それらが実際に適用されているかどうかはわかりません。 しかし、メモリを再構成する前に、MPU(メモリ保護ユニット)はすでに有効になっているようです。次に、キャッシュを再度有効にする前に、MPUを有効にしようとします。 これらの値を変更する前に、MPU->CTRL[0]を0に設定する必要がありますか?データシートにはそれに関する参照を見つけることができませんでした。 Re: S32k324 ブートローダ リンカ (2 つのリンカ ファイルの物語) はい、アプリケーションはSRAMメモリを再初期化できます。ただし、すでにブートローダーによって初期化されている場合は、不要な操作です。 Re: S32k324 ブートローダ リンカ (2 つのリンカ ファイルの物語) ブートローダーが最初に実行された場合、アプリケーションがメモリを再初期化することは可能ですか? 私のスタートアップファイルは、どちらのアプリケーションでもS32K3_RTD_2_0_0_D2203_ASR_REL_4_4_REV_0000_20220331に基づいています。
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