What is the use of the dcf_config.c file under the board folder of the S32K396 project? Re: What is the use of the dcf_config.c file under the board folder of the S32K396 project? Hi .@danielmartynek, Is there a way to modify DCF clients using DCD tools? Re: What is the use of the dcf_config.c file under the board folder of the S32K396 project? Hi @qingwang_a, There is S32K3xx_DCF_clients.xlsx attached to the Reference Manual. You can refer to these excel calculators for MPC57xx, It is similar to the S32K3 DCF. https://community.nxp.com/t5/MPC5xxx-Knowledge-Base/MPC57xx-DCF-records/ta-p/1114884 Here is this C40_Ip RTD example that writes a new DCF record. https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-DCF-POR-WDG-EN-DS35-RTD300/ta-p/1849816 Regards, Daniel Re: What is the use of the dcf_config.c file under the board folder of the S32K396 project? Thank you for your reply. Do you have any examples or documentation on using DCD_tool to modify dcf_client? Re: What is the use of the dcf_config.c file under the board folder of the S32K396 project? Hi @qingwang_a, This is configurable in DCD Regards, Daniel

How to flush the uart FIFO with CTS enabled for S32K146 Hi support team, We're using UART Tx FIFO function with CTS feature enabled. After having checked with the errata file of S32K146, we find that the ERR051629 is related to our case. My understanding of this issue is that if the CTS pin is changed to low during the tx FIFO is flushing with CTS feature enabled, the transmit complete bit will not be set, the workaround is to clear the MODIR[TXCTSE] bit before setting FIFO[TXFLUSH] bit to 1 if the CTS feature is enabled, and then set the MODIR[TXCTSE] bit again, such as the following code changes based on the NXP RTD code: /** * @brief : Flush Tx Buffer * * This function causes all data that is stored in the transmit FIFO/buffer to be flushed. * * * @Param Base LPUART Base pointer */ static inline void Lpuart_Uart_Ip_FlushTxBuffer(LPUART_Type * Base) { Base->MODIR &= 0xFFFFFFFEu; /*Clear (MODIR[TXCTSE]) bit*/ Base->FIFO |= 0x00008000u; /*reset the transmit FIFO (FIFO[TXFLUSH] = 0b1)*/ Base->MODIR |= 0x00000001u; /*Set (MODIR[TXCTSE]) bit*/ } Is my understanding correct? If it's not correct, how should I handle this problem?  Re: How to flush the uart FIFO with CTS enabled for S32K146 HI @snowy, CTS_B is asserted when the input voltage level goes LOW. The CTS_B pin must assert for longer than one bit period to guarantee that a new transmission is started when the transmitter is idle. The transmitter checks the state of the CTS signal each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the TXD signal remains in the mark state and transmission is delayed until CTS is asserted. So, it will not stop transmitting, it will send the data present in the FIFO. Regards, Daniel Re: How to flush the uart FIFO with CTS enabled for S32K146 Hi Daniel, Thank you very much for your reply. Could you please help check the following question? If the CTS pin is changed to low during writing data into tx FIFO, will the data stop transmitting until the CTS pin be changed back to high? Or the tx will be abort directly with data lost? Re: How to flush the uart FIFO with CTS enabled for S32K146 Helle @snowy, Yes, this is correct. If you have any specific question, let me know, BR, Daniel

如何为S32K146启用CTS刷新UART FIFO 嗨，支持团队， 我们正在使用启用了 CTS 功能的 UART Tx FIFO 功能。在检查了S32K146的勘误表文件后，我们发现ERR051629与我们的案例有关。我对这个问题的理解是，如果在启用 CTS 功能的情况下在 tx FIFO 刷新期间将 CTS 引脚更改为低，则不会设置发送完成位，解决方法是在启用 CTS 功能的情况下将 FIFO[TXFLUSH] 位设置为 1 之前清除 MODIR[TXCTSE] 位，然后再次设置 MODIR[TXCTSE] 位，例如以下基于 NXP RTD 代码的代码更改： /** * @brief：刷新Tx缓冲区 * * 此功能导致存储在传输 FIFO/缓冲区中的所有数据都被刷新。 * * * @Param Base LPUART基指针 */ 静态内联void Lpuart_Uart_Ip_FlushTxBuffer（LPUART_Type * Base） { Base->MODIR &= 0xFFFFFFFEu; /*清除（MODIR[TXCTSE]）位*/ Base->FIFO |= 0x00008000u; /*重置传输 FIFO (FIFO[TXFLUSH] = 0b1)*/ Base->MODIR |= 0x00000001u; /*设置（MODIR[TXCTSE]）位*/ } 我的理解正确吗？如果不正确，我该如何处理这个问题？

LPDDR5 application with i.MX 9 series Hi NXP, How many LPDDR5 chips can be connect with i.MX 94 or i.MX 95?  Thank you. Re: LPDDR5 application with i.MX 9 series Thanks for your information! Re: LPDDR5 application with i.MX 9 series Hello, Please note that both chips are still under pre-prodcution stage so any specifications and information herein are subject to change without notice. For additional information contact your sales representative. For the i.MX94 Up to 4.2GT/s x32 LPDDR4/LPDDR5 (with Inline ECC) are supported. For the i.MX95 Up to 6.4GT/s x32 LPDDR5/LPDDR4X (with Inline ECC & Inline Encryption) Best regards/Saludos, Aldo.

MPC5746R User Mode Machine Check Exception on Accessing SIUL2 ports Good Afternoon I am attempting to run application code in USER mode but every time I attempt to write to an SIUL2 port register I get a machine check error.  The OS is relatively simple and accesses the application through a jump block after setting up the base system for the application to run (I hope). No memory protection blocks are changed from their default values except the AIPS which (for now) I have set to maximum permissions (everything is usable by everyone) but I still get a machine check exception each time I try to initialise an SIUL2 port. I have no issues with the DSPI block or the TPU blocks so I don't think it is a general peripheral issue. I have attached what I hope are the relevant parts of the OS and application, I apologise it is so little but I had to fight to be able to send this. The two OS files attached are the relevant startup code and the OS code is the first file the application runs when initialising. Any suggestions or better yet absolute answers would be much appreciated. Re: MPC5746R User Mode Machine Check Exception on Accessing SIUL2 ports Peter Thanks for the quick response. Chapter 80 took some figuring out but in the end I managed to get my head around what it was saying and implemented you suggestion and this works fine. Regards David Re: MPC5746R User Mode Machine Check Exception on Accessing SIUL2 ports Hello, I expect that the issue is in register protection. As you can see SIUL is protected, but DSPI or eTPU are not. You need to allow access in user mode to SIUL module registers in register protection. Set UAA bit for SIUL to 1. Best regards, Peter

Request for S32 Design Studio V2.2 License extension Hello, My S32DS V2.2 license has expired Can you please extend my license? Thank you. Catalog Item Name S32 Design Studio for ARM v2.2 Additional Details Order ID / Line # S32DS-IDE-ARM-V2-X_159704827 / 1 Fulfilled Quantity 1 Activation Code 096E-3C68-5CE0-FE68 Product S32 Design Studio for ARM v2.2 Host   Order Date May 13, 2020 Re: Request for S32 Design Studio V2.2 License extension Thank you, my S32DS is working well  Re: Request for S32 Design Studio V2.2 License extension Hi,  your S32DS license has been extended. 

MPC5746R ユーザー モード SIUL2 ポートへのアクセス時のマシン チェック例外 こんにちは USER モードでアプリケーション コードを実行しようとしていますが、SIUL2 ポート レジスタに書き込もうとするたびにマシン チェック エラーが発生します。 OSは比較的シンプルで、アプリケーションを実行するための基本システムを設定した後、ジャンプブロックを介してアプリケーションにアクセスします(私は願っています)。メモリ保護ブロックは、(今のところ)最大権限(すべてが誰でも使用可能)に設定したAIPSを除いて、デフォルト値から変更されていませんが、SIUL2ポートを初期化しようとするたびにマシンチェック例外が発生します。DSPIブロックまたはTPUブロックに問題はないので、一般的な周辺機器の問題ではないと思います。 OSとアプリケーションの関連部分であることを願っていますものを添付しましたが、それはとても少ないですが、これを送信できるようにするために戦わなければなりませんでした。 添付されている 2 つの OS ファイルは関連するスタートアップ コードであり、OS コードは初期化時にアプリケーションが実行する最初のファイルです。 どんな提案やもっと良いことに絶対的な答えでも大歓迎です。

MPC5746R 用户模式机器检查访问 SIUL2 端口时的异常 下午好 我试图在用户模式下运行应用程序代码，但每次我尝试写入 SIUL2 端口寄存器时都会出现机器检查错误。 该操作系统相对简单，在设置应用程序运行的基本系统后，通过跳转块访问应用程序（我希望）。除了 AIPS 之外，没有任何内存保护块从其默认值更改，目前我已将 AIPS 设置为最大权限（所有内容都可以供所有人使用），但每次我尝试初始化 SIUL2 端口时仍然会收到机器检查异常。我对 DSPI 块或 TPU 块没有任何问题，所以我不认为这是一个一般外围设备问题。 我已附上我希望的操作系统和应用程序的相关部分，很抱歉内容太少，但我不得不努力才能发送这些内容。 附加的两个 OS 文件是相关的启动代码，OS 代码是应用程序初始化时运行的第一个文件。 任何建议或更好的绝对答案都将不胜感激。

VLSS3からウェイクアップした後、MKL03がクラッシュします。 こんにちはNXPサポート。   私はMKL03Z32VFK4R用に作られたアプリケーションをデバッグしています。 システムは3ボルトのバッテリーで駆動され、ほとんどの場合、VLSS3の低消費モードのままです。 このMCU(マイクロコントローラ)ではPTB0であるLLWU_P4ピンは、正のエッジでのウェイクアップとして構成されています。 PTB0にはスイッチが接続されており、押すと正のエッジが発生し、MCUがウェイクアップします。 ウェイクアップ後、いくつかのタスクが実行され、最後にVLLS3モードに戻ります。   アプリケーションは正常に動作しますが、断続的にクラッシュすることがあります。 Nordic SemiconductorsのPPK2(Power Profiler Kit 2)を使用していくつかのキャプチャを作成しました。   バッテリーの代わりに3ボルト電源として構成されたPPK2を接続しました。 このようにして、バッテリー残量が少なくなる可能性を排除します。 また、PPK2の2つ目のUSBを接続して、最大1000mAの供給容量を保証しました。 また、マイコンからのI/OピンをPPK2のデジタル入力D0に接続しました。 I/Oピンは、実行された各コード行を切り替えるようにプログラムしましたが、最初はどこでスタックしているのかを見つける目的でした。   以下に一連の図を示します。   図01:PTB0スイッチの連続した押下サイクルを示しています。   図02:うまくいったサイクルを詳しく示しています。   図03:タイムラインを観察して停止したサイクルを示していますが、この場合は停止するのに5分28秒以上かかりました。   図04:クラッシュサイクルを示していますが、MCUは回復しています。   図05:ほぼ停止したサイクルの最後の部分をズームで示しています。D0 は、明らかに figure04 と同様に、トゥーグル ダイナミクスを示し始めます。   私はいくつかのテストを行い、問題が断続的であることがわかりました。 クラッシュは最初の数サイクルで発生することもあれば、この場合のように5分以上後に発生するように、長い時間がかかることもあります。 私はいくつかの仮説を考えました。 1 - VLLS3 のウェイクアップ後に ACKISO フラグが "クリア" されていない可能性があると思いました。 しかし、MCUはクラッシュし続け、ACKISOの旗を無条件に「クリア」することさえありました。 ACKISOをクリアする行をコメントアウトしたのは、MCUをクラッシュさせることができるかどうかを確認するためだけです。 驚いたことに、MCUはクラッシュせず、まるで違いを生まないように機能しました。   2 - 最初に、プログラムはピン LLWU_P4 (PTB0) の正のエッジを検出するように LLWU を構成し、LLWU 割り込みを有効にする関数 "InitLLWU" を呼び出しました。 次に、関数 enter_vlls(3) が呼び出されて VLSS3 モードに入ります。 「enter_vlls(3)」関数の中に「InitLLWU」関数を配置してみましたが、この場合は「InitLLWU」を1行前に置いて__WFI。 クラッシュの原因は、マイコンがVLSS3モードに入る前にLLWUの割り込みが起こったからだと思っていましたが、この変更後もクラッシュが発生しています。   3 - 最初は、図03に示されているクラッシュは、MCUがウェイクアップし、再起動によってMCUが破損してクラッシュしたことを示していると思いました。 また、図04や図05のようにクラッシュしたようなケースもありましたが、MCUはなんとか立ち直ることができました。 図 04 の最初の部分ではトグルは発生しませんが、図 05 に示す最後の部分では、トグルのダイナミクスは図 02 と非常によく似ています。 最初は、VLLS3に入る前の設定が不十分であることが問題の原因だと思いました。 サイクルが有効ではなかったにもかかわらず、MCUはなんとか回復したので、パーシャルリセットの失敗か、初期化の失敗など、ウェイクアップ後に問題が発生していると思います。   以上が、私がこれまでに導き出したテストと結論でした。 どなたか同様の経験があり、私に何か提案をいただける方がいらっしゃいましたら、ありがたいです。   よろしくお願いいたします。 Re:VLSS3からウェイクアップした後、MKL03がクラッシュします。 こんにちはCeleste_Liu、返信が遅れてすみません。 なんとか問題を発見することができました。 この問題は低電力モードに関連していたのではなく、MKL03Z32VFK4Rのピン19に関連していました。 ウェイクアップ後に発生するパーシャルリセットの後、ピン19がデフォルトの構成であるNMI(Non-Maskable Interrupt)機能に戻ることを発見しました。 ピン19をGPIO入力、つまりPTB5として使用して、スイッチの状態を読み取ります。 リセット後、ピンを PTB5 として構成する前に、ノイズによって NMI ハンドラーがアクティブになっていたと思います。 私はNMI関数を使用しないので、デフォルトのNMIハンドラはプロセッサをロックするwhile(1){}ループであることがわかりました。 私は、投稿で見つけたガイダンスに従って、NMIオプションを無効にすることで問題を解決しました https://community.nxp.com/t5/MCUXpresso-General/debug-problem-on-KL03Z8/m-p/949741 私はFlash_Configワード4を0xFFFF3BFEに変更し、問題が解決したことを確認するために多くのテストを行いました。 ご支援いただき、誠にありがとうございます。 Re:VLSS3からウェイクアップした後、MKL03がクラッシュします。 こんにちはCeleste_Liu、フィードバックをいただきありがとうございます。 プロジェクトで CMP コンパレータ モジュールを使用していません。 それでも、ERR008010正誤表は関連性があると思いますか? とにかく、回避策によって提案されたコードがどのように見えるかを教えてもらえますか? よろしくお願いいたします。

S32K312 LIN Communication as Master mode Dear NXP Team. I try to Lin communication for master mode using linstack v2.0.4.  However I face the problem slave not responding.  Master publish frame is normal workiong,  however subscribe message has not working. In detailed, CANoe interface as slave side is not respone from physical layer. When I checked waveform at osiloscope, and I think timing is not problem. I attached my configuration project. Could you pleae give to me any advice? * Project Information - S32K312 172Pin EVB - RTD v4.0.0 - Lin stack v2.0.4 - Referenced project is Lin stack example for S32K344 Best regards. Re: S32K312 LIN Communication as Master mode Hi, I just added it to be able to compile your project. BR, Petr Re: S32K312 LIN Communication as Master mode Hi @PetrS  Thanks for your reply. I checked and normal working.  Sorry for late check. Because I'm out of office last week. When I checked code, OsIf_internal.h file below need to be modified manually in the lin_commontl_proto.c ? Thanks, BR Re: S32K312 LIN Communication as Master mode Hi, I did below modifications of your code and it responds accordingly to data published by slave, see attached video. - uncomment lin_dal_timeout_service(LI0) in Lin_Schedule_Ctrl - check Motor1Temp flag and read its data in lin_master_task I used PLIN View and load ldf there to work as Motor1 slave BR, Petr

LPSPI after Lpspi_Ip_AsyncTransmit stays in BUSY state Lpspi_Ip_AsyncTransmit() call gets executed once with expected  SPI waveforms. Other calls are rejected because drives stays in LPSPI_IP_BUSY state. I have a workaround to call Lpspi_Ip_Cancel() when BUSY state is reported: if (Lpspi_Ip_GetStatus() == LPSPI_IP_BUSY) Lpspi_Ip_Cancel(); Lpspi_Ip_AsyncTransmit(); This works but I won't want to keep using that cancel call. What can keep driver in BUSY state even after all needed data are properly Tx/Rx by SPI? I use RTD 4.0.0, SPI with Tx/Rx DMA channels. DMA does not have global/transfer/scatter configs, also no interrupt callback. S32 SDK for S32V Re: LPSPI after Lpspi_Ip_AsyncTransmit stays in BUSY state I ended up with writing my own function using synchronous transmit as example. It was possible to use fifo and have function that does not use interrupts(well, almost) and dma and returns immediately. That works similar to Lpspi_Ip_AsyncTransmit for my project. Re: LPSPI after Lpspi_Ip_AsyncTransmit stays in BUSY state Please create a new thread, Thank you, Daniel Re: LPSPI after Lpspi_Ip_AsyncTransmit stays in BUSY state Hello Daniel, We have the same issue For S32k44, configured LPSPI using EB tresos and tried to transmit data using Lpspi_Ip_AsyncTransmit() call gets executed once Other calls are rejected because the drives stays in LPSPI_IP_BUSY state . Can please share Example project of S32K344(with EB tresos configuration) for Lpspi_Ip_AsyncTransmit(); using Dma ? Re: LPSPI after Lpspi_Ip_AsyncTransmit stays in BUSY state Try enabling Global config in the in the DMA driver. Please share the whole project (or a test project that can demonstrate the issue,) so that I can test it. Thank you, BR, Daniel Re: LPSPI after Lpspi_Ip_AsyncTransmit stays in BUSY state Hello, I added DMA ISRs (I use same DMA channels as the example) to IntCtrl_Ip Nothing changed after that, and I didn't see that any of those interrupts were called. Re: LPSPI after Lpspi_Ip_AsyncTransmit stays in BUSY state Hi @sstelmak, The driver requires the DMA interrupts. Have a look at the Lpspi_Flexio_Ip_Transfer_S32K344 example, where the FlexIO_SPI driver uses DMA. BR, Daniel Re: LPSPI after Lpspi_Ip_AsyncTransmit stays in BUSY state Hello, I can't post entire project per company policies, it would be ok to email it directly. Attached is the mex and few relevant c files.  DMA or SPI interrupts are not configured. This is because I have restriction for micro throughput and looking for possibility to skip unnecessary calls. Re: LPSPI after Lpspi_Ip_AsyncTransmit stays in BUSY state Hi @sstelmak, I understand the driver never becomes IDLE after the transfer. It would help if you could share the project so that I can test it. Did you enable DMA interrups in the IntCtrl_Ip driver? Regards, Daniel

MKL03 从 VLSS3 唤醒后崩溃。 您好，NXP 支持人员。   我正在调试为 MKL03Z32VFK4R 制作的应用程序。 该系统由 3 伏电池供电，大部分时间保持 VLSS3 低功耗模式。 LLWU_P4 引脚（在该 MCU（微控制器）中为 PTB0）配置为在上升沿唤醒。 有一个开关连接到 PTB0，按下时会产生上升沿，从而唤醒 MCU。 唤醒后，执行一些任务，最后返回VLLS3模式。   应用程序运行正常，但有时会间歇性崩溃。 我使用 Nordic Semiconductors 的 PPK2（Power Profiler Kit 2）进行了一些捕获。   我连接了配置为 3 伏电源的 PPK2 来代替电池。 这样我就排除了电池电量低的可能性。 我还连接了 PPK2 的第二个 USB，以保证高达 1000 mA 的供电能力。 我还将 MCU 的 I/O 引脚连接到 PPK2 上的数字输入 D0。 我对 I/O 引脚进行了编程，以切换每行执行的代码，最初的目的是找出它卡在了哪里。   下面我给出一组数字：   图 1：显示连续成功的 PTB0 开关按压循环；   图 2：详细显示了有效的循环。   图03：显示停止的循环，观察时间线，在这种情况下，停止需要5分28秒多一点的时间；   图04：显示崩溃循环，但MCU已恢复；   图 5：放大显示几乎停止的循环的最后部分。注意，D0 开始显示出 toogle 动态，显然与图 04 类似。   我做了几次测试，发现该问题是间歇性的。 有时崩溃会在最初几个周期内发生，有时会持续很长时间，就像本例一样，崩溃发生在 5 分钟以上之后。 我想到了几个假设： 1 - 我认为可能是 VLLS3 唤醒后 ACKISO 标志未被“清除”。 但 MCU 继续崩溃，甚至无条件“清除” ACKISO 标志。 我注释掉了清除 ACKISO 的行，只是为了看看是否会导致 MCU 崩溃。 令人惊讶的是，MCU 并没有崩溃，并且像没有造成任何影响一样正常工作。   2 - 最初，程序调用函数“InitLLWU”，该函数配置LLWU以检测引脚LLWU_P4（PTB0）上的正边沿并启用LLWU中断。 然后调用函数“enter_vlls(3)”进入VLSS3模式。 我尝试将“InitLLWU”函数放在“enter_vlls(3)”函数中，在这种情况下，我在调用__WFI之前放置了“InitLLWU”一行。 我认为崩溃的原因是在 MCU 进入 VLSS3 模式之前发生的 LLWU 中断，但即使在这一改变之后，崩溃仍然发生。   3-一开始我以为图03所示的崩溃表示MCU被唤醒，重启损坏并导致MCU崩溃。 还有一些情况，例如图 04 和 05 中所示的情况，看起来像是崩溃的情况，但 MCU 设法恢复了。 尽管图 04 的初始部分没有出现切换，但在图 05 所示的最终部分中，切换动态与图 02 所示的非常相似。 起初我以为问题可能是由于进入 VLLS3 之前的设置不当造成的。 尽管循环无效，但 MCU 设法恢复，所以我认为问题发生在唤醒之后，可能是部分重置不成功，或者某些初始化失败。   这些是我迄今为止进行的测试和得出的结论。 如果有人有过类似的经历并能给我任何建议，我将不胜感激。   此致。 回复：从 VLSS3 唤醒后 MKL03 崩溃。 你好 Celeste_Liu，抱歉这么晚才回复。 我设法发现了这个问题。 问题与低功耗模式无关，而是与 MKL03Z32VFK4R 的第 19 个引脚有关。 我发现，在唤醒后发生部分复位后，引脚 19 恢复为默认配置，即 NMI（不可屏蔽中断）功能。 我使用引脚 19 作为 GPIO 输入，即作为 PTB5 来读取开关的状态。 我相信重置后，在将引脚配置为 PTB5 之前，一些噪音会激活 NMI 处理程序。 由于我不使用 NMI 函数，我看到默认的 NMI 处理程序是一个锁定处理器的 while(1){} 循环。 根据我在帖子中找到的指导，我通过禁用 NMI 选项解决了该问题： https://community.nxp.com/t5/MCUXpresso-General/debug-problem-on-KL03Z8/mp/949741 我将Flash_Config word4改为0xFFFF3BFE，并做了多次测试，确认问题已经解决。 我感谢你们的支持。 回复：从 VLSS3 唤醒后 MKL03 崩溃。 你好 Celeste_Liu，非常感谢你的反馈。 我在我的项目中没有使用 CMP 比较器模块。 您是否认为即使如此，ERR008010 勘误表仍然有意义？ 无论如何，您能向我展示解决方法所建议的代码是什么样的吗？ 此致。

MKL03 crashing after waking up from VLSS3. Hello NXP support.   I'm debugging an application made for the MKL03Z32VFK4R. The system is powered by a 3 volt battery and remains in VLSS3 low consumption mode most of the time. The LLWU_P4 pin, which in this MCU (microcontroller) is PTB0, is configured as wake-up on a positive edge. There is a switch connected to PTB0 and when pressed, it causes a positive edge that wakes up the MCU. After waking up, some tasks are executed and at the end it returns to VLLS3 mode.   The application works correctly, but sometimes crashes intermittently. I made some captures using a PPK2 (Power Profiler Kit 2) from Nordic Semiconductors.   I connected the PPK2 configured as a 3 volt power supply in place of the battery. This way I rule out the possibility of a low battery. I also connected the second USB of the PPK2 to guarantee up to 1000 mA of supply capacity. I also connected an I/O pin from the MCU to digital input D0 on the PPK2. I programmed the I/O pin to toggle each executed line of code, initially with the aim of finding out where it was stuck.   Below I present a set of figures:   figure01: shows a succession of successful PTB0 switch pressing cycles;   figure02: shows in detail a cycle that worked.   figure03: shows the cycle that stopped, observing the timeline, in this case it took a little more than 5 minutes and 28 seconds to stop;   figure04: shows a crash cycle, but the MCU has recovered;   figure05: shows in zoom the final part of the cycle that almost stopped. Notice that D0 starts to show toogle dynamics, apparently similar to figure04.   I did several tests and found that the problem is intermittent. Sometimes the crash occurs in the first few cycles and sometimes it takes a long time, as in this case, which occurred after more than 5 minutes. I thought of several hypotheses: 1 - I thought it could be the ACKISO flag not being "cleared" after the wake-up of VLLS3. But the MCU continued to crash, even "clearing" the ACKISO flag unconditionally. I commented out the line that clears ACKISO, just to see if I could crash the MCU. Surprisingly, the MCU didn't crash and worked as if it didn't make a difference.   2 - Initially the program called a function "InitLLWU" that configures the LLWU to detect positive edge on pin LLWU_P4 (PTB0) and enables the LLWU interrupt. Then a function "enter_vlls(3)" is called to enter VLSS3 mode. I tried placing the "InitLLWU" function inside the "enter_vlls(3)" function, in this case, I placed "InitLLWU" one line before calling __WFI. I thought the reason for the crash would be an LLWU interruption happening before the MCU entered VLSS3 mode, but even after this change, the crash occurred.   3 - At first I thought that the crash shown in figure 03 indicated that the MCU woke up and the restart corrupted and crashed the MCU. There were also cases like the one seen in figures 04 and 05 that looked like a case of crash, but the MCU managed to recover. Although toggles do not occur in the initial part of figure 04, in the final part, seen in figure 05, the toggle dynamics are very similar to those seen in figure 02. At first I thought the problem could be due to poor settings before entering VLLS3. Even though the cycle was not valid, the MCU managed to recover, so I think the problem is happening after waking up, perhaps the unsuccessful partial reset, or some failed initialization.   These were the tests and conclusions I have drawn so far. If anyone has had a similar experience and can give me any suggestions, I would be grateful.   Best Regards. Re: MKL03 crashing after waking up from VLSS3. Hi Celeste_Liu, sorry for the delay in responding. I managed to discover the problem. The problem was not related to the low power mode, but rather to pin 19 of the MKL03Z32VFK4R. I discovered that pin 19 returns to the default configuration, which is the NMI (Non-Maskable Interrupt) function, after the partial reset that occurs after wake-up. I use pin 19 as GPIO input, that is, as PTB5 to read the state of a switch. I believe that after the reset, some noise was activating the NMI handler before it was possible to configure the pin as PTB5. As I don't use the NMI function, I saw that the default NMI handler is a while(1){} loop that locks the processor. I solved the problem by disabling the NMI option, according to the guidance I found in the post: https://community.nxp.com/t5/MCUXpresso-General/debug-problem-on-KL03Z8/m-p/949741 I changed Flash_Config word4 to 0xFFFF3BFE and did many tests to confirm that the problem had been resolved. I thank you for the support. Re: MKL03 crashing after waking up from VLSS3. Hello carlos, You are correct. Since CMP was not used, it should have nothing to do with this errata. I would suggest you refer to the power manager demo under the SDK installation folder SDK_2.3.1_FRDM-KL03Z\boards\frdmkl03z\demo_apps\power_manager This demo application demonstrates the use of power modes in the SDK. and use source pin to wake up from VLLS3. SDK download link: Select Board | MCUXpresso SDK Builder Hope it can help you. BRs, Celeste Re: MKL03 crashing after waking up from VLSS3. Hi Celeste_Liu, thank you very much for the feedback. I am not using the CMP comparator module in my project. Do you think that even so, the ERR008010 errata would be relevant? Anyway, could you show me what the code suggested by the workaround would look like? Best Regards. Re: MKL03 crashing after waking up from VLSS3. Hello @carlos_takeo_ta , Thanks for your post. I think this may be related to ERR008010. Please check whether PMC_REGSC[ACKISO] is cleared and whether the corresponding flag of the comparator in the LLWU_Fx register is cleared. Correspondingly, it provides a workaround. KL03Z Errata Link: KL03Z_1N86K  Hope it help you. If you have any further questions or need more information, please let me know. Best Regards, Celeste -------------------------------------------------------------------------------------- Note: If this post answers your question, please click the "ACCEPT AS SOLUTION" button. Thank you! --------------------------------------------------------------------------------------

S32k146 read data from SD-card with SPI Hi, we need to read data from our micro-SD card. Is there any example for the communication between s32k146 and a sd-card via SPI without SDK? Best regards Sandra Re: S32k146 read data from SD-card with SPI Hi LBowen, I used the project "S32K144_Project_LPSPI" which is posted on the bottom of the following topic https://community.nxp.com/t5/S32-SDK/S32K144-Fatfs/m-p/1205126/highlight/true#M2016 as base. You have to use f_read instead of f_write to read data from the sd-card.  Best regards Re: S32k146 read data from SD-card with SPI Hi @12914A  As the S32K family does not directly support SD cards (not expected use-case), we do not have such example or drivers for this device. The driver must be written by the user. We have an application note (S32K1xx Series Cookbook) that provides software examples and describes the necessary startup steps needed to get started with S32K1xx series MCUs.  Also, we can help with the LPSPI module and problems with communication such as not transmitting words as programmed or not receiving expected words. BR, VaneB Re: S32k146 read data from SD-card with SPI I want to ask, has it been solved? I also need this routine, thank you

Issue with MIMXRT1170 Flashloader When trying to start a debug session or run the GUI flash tool, I'm running into issues with the supplied flashloader. We typically start debug sessions on our devices from serial downloader boot mode which has stopped working. An attempt will result in a failure to reset the flash loader, with a timeout reached. Here's the LinkServer console output: Executing flash operation 'Erase' (Erase flash) - Tue Jul 23 13:29:09 PDT 2024 Checking MCU info... Scanning for targets... Executing flash action... MCUXpresso IDE RedlinkMulti Driver v11.10 (Jul 2 2024 19:33:51 - crt_emu_cm_redlink.exe build 741) ( 0) Reading remote configuration Wc(03). No cache support. Found chip XML file in C:/---/MIMXRT1172xxxxx.xml ( 5) Remote configuration complete Reconnected to existing LinkServer process. ============= SCRIPT: RT1170_connect_M7.scp ============= RT1170 Connect M7 Script DpID = 6BA02477 APID = 0x84770001 View cores on the DAP AP TAP 0: 6BA02477 Core 0: M7 APID: 84770001 ROM Table: E00FD003* ============= END SCRIPT ================================ Probe Firmware: MCU-LINK (r0FF) CMSIS-DAP V3.146 (NXP Semiconductors) Serial Number: JZ4FND0JCLDTD VID:PID: 1FC9:0143 USB Path: 0001:0008:00 Using memory from core 0 after searching for a good core ( 30) Emulator Connected ( 40) Debug Halt ( 50) CPU ID debug interface type = CoreSight DP (DAP DP ID 6BA02477) over SWD TAP 0 processor type = Cortex-M7 (CPU ID 00000C27) on DAP AP 0 number of h/w breakpoints = 8 number of flash patches = 0 number of h/w watchpoints = 4 Probe(0): Connected&Reset. DpID: 6BA02477. CpuID: 00000C27. Info: Debug protocol: SWD. RTCK: Disabled. Vector catch: Disabled. Content of CoreSight Debug ROM(s): RBASE E00FD000: CID B105100D PID 000008E88C ROM (type 0x1) ROM 1 E00FE000: CID B105100D PID 04000BB4C8 ROM (type 0x1) ROM 2 E00FF000: CID B105100D PID 04000BB4C7 ROM (type 0x1) ROM 3 E000E000: CID B105E00D PID 04000BB00C Gen SCS (type 0x0) ROM 3 E0001000: CID B105E00D PID 04000BB002 Gen DWT (type 0x0) ROM 3 E0002000: CID B105E00D PID 04000BB00E Gen (type 0x0) ROM 3 E0000000: CID B105E00D PID 04000BB001 Gen ITM (type 0x0) ROM 2 E0041000: CID B105900D PID 04001BB975 CSt ARM ETMv4.0 type 0x13 Trace Source - Core ROM 2 E0042000: CID B105900D PID 04004BB906 CSt type 0x14 Debug Control - Trigger, e.g. ECT ROM 1 E0043000: CID B105900D PID 04001BB908 CSt CSTF type 0x12 Trace Link - Trace funnel/router NXP: MIMXRT1172xxxxx DAP stride is 1024 bytes (256 words) Inspected v.2 External Flash Device on SPI using SFDP JEDEC ID MIMXRT1170_SFDP_QSPI.cfx Image 'iMXRT1170_SFDP_FlexSPI1_A_QSPI Jul 2 2024 18:28:49' Opening flash driver MIMXRT1170_SFDP_QSPI.cfx Sending VECTRESET to run flash driver AFTER driver startup timeout (302 5ms retries) Driver Addresses Start: 20000000 Entry: 2000009D End: 20000834 Stack: 20002838 Mailbox:2000A838 Driver Register State R0: 400CC000 R1: 00000008 R2: 20000574 R3: 00000001 R4: 00000002 R5: 00000000 R6: 0000C270 R7: 00000000 R8: 00000000 R9: 00000000 R10: 00000000 R11: 00000000 R12: 00000004 SP: 200027E8 LR: 2000034B PC: 0021A114 xPSR: 61000000 MSP: 200027E8 PSP: 20002838 CFBP: 00000001 (CONTROL=0x0, FAULTMASK=0x0, BASEPRI=0x0, PRIMASK=0x1) Flash Driver V.2 startup failed - rc Ef(34): Timed-out initializing flash. chip initialization failed - Ef(34): Timed-out initializing flash. failed to initialize flash driver MIMXRT1170_SFDP_QSPI.cfx ( 65) Chip Setup Complete (100) Target Operation Failed Unable to perform operation! Command failed with exit code 1 I've tried the supplied flashloader of the 11.9 and 11.10 releases and they both do not work in serial downloader boot mode. The flashloader supplied with 11.8 (I think LinkServer v1.0.9) and it will work just fine. I've already tried changing the reset handling from a VECTRESET to SYSRESETREQ to no avail. I've also occasionally seen hard faults in the EPSR but not consistently. Is there some other configuration required now that I'm missing? Thanks Re: Issue with MIMXRT1170 Flashloader We checked your use case on our side and we confirm the issue. You're right about the change of functionality between 11.8.0 and 11.10.0. However, booting from flash does not exhibit the same issue on our side. We're also working on a fix. Thank you, Adrian Re: Issue with MIMXRT1170 Flashloader Unfortunately no change in behavior there. Not sure that that would explain the GUI Flash Tool not working as well. The configuration of the project hasn't changed between 11.8 and 11.8/11.10, just which flashloader is being used. I pointed MCUXpresso 11.10 to the 11.8 flashloader for the RT1170 and that will also work as expected, so maybe a change to the flashloader is causing this? I did see that they were updated in 11.9 changelog for this processor. Thanks!  Re: Issue with MIMXRT1170 Flashloader Would you please try to configure the board to boot from flash and let us know the result? We'll double-check on our side as well. Thank you, Adrian

MIMXRT1170 Flashloader の問題 デバッグ セッションを開始したり、GUI フラッシュ ツールを実行したりすると、付属のフラッシュローダーで問題が発生します。通常、デバイスのデバッグセッションは、動作を停止したシリアルダウンローダーブートモードから開始されます。フラッシュ ローダーのリセットは失敗し、タイムアウトに達します。 LinkServer コンソールの出力を次に示します。 Executing flash operation 'Erase' (Erase flash) - Tue Jul 23 13:29:09 PDT 2024 Checking MCU info... Scanning for targets... Executing flash action... MCUXpresso IDE RedlinkMulti Driver v11.10 (Jul 2 2024 19:33:51 - crt_emu_cm_redlink.exe build 741) ( 0) Reading remote configuration Wc(03). No cache support. Found chip XML file in C:/---/MIMXRT1172xxxxx.xml ( 5) Remote configuration complete Reconnected to existing LinkServer process. ============= SCRIPT: RT1170_connect_M7.scp ============= RT1170 Connect M7 Script DpID = 6BA02477 APID = 0x84770001 View cores on the DAP AP TAP 0: 6BA02477 Core 0: M7 APID: 84770001 ROM Table: E00FD003* ============= END SCRIPT ================================ Probe Firmware: MCU-LINK (r0FF) CMSIS-DAP V3.146 (NXP Semiconductors) Serial Number: JZ4FND0JCLDTD VID:PID: 1FC9:0143 USB Path: 0001:0008:00 Using memory from core 0 after searching for a good core ( 30) Emulator Connected ( 40) Debug Halt ( 50) CPU ID debug interface type = CoreSight DP (DAP DP ID 6BA02477) over SWD TAP 0 processor type = Cortex-M7 (CPU ID 00000C27) on DAP AP 0 number of h/w breakpoints = 8 number of flash patches = 0 number of h/w watchpoints = 4 Probe(0): Connected&Reset. DpID: 6BA02477. CpuID: 00000C27. Info: Debug protocol: SWD. RTCK: Disabled. Vector catch: Disabled. Content of CoreSight Debug ROM(s): RBASE E00FD000: CID B105100D PID 000008E88C ROM (type 0x1) ROM 1 E00FE000: CID B105100D PID 04000BB4C8 ROM (type 0x1) ROM 2 E00FF000: CID B105100D PID 04000BB4C7 ROM (type 0x1) ROM 3 E000E000: CID B105E00D PID 04000BB00C Gen SCS (type 0x0) ROM 3 E0001000: CID B105E00D PID 04000BB002 Gen DWT (type 0x0) ROM 3 E0002000: CID B105E00D PID 04000BB00E Gen (type 0x0) ROM 3 E0000000: CID B105E00D PID 04000BB001 Gen ITM (type 0x0) ROM 2 E0041000: CID B105900D PID 04001BB975 CSt ARM ETMv4.0 type 0x13 Trace Source - Core ROM 2 E0042000: CID B105900D PID 04004BB906 CSt type 0x14 Debug Control - Trigger, e.g. ECT ROM 1 E0043000: CID B105900D PID 04001BB908 CSt CSTF type 0x12 Trace Link - Trace funnel/router NXP: MIMXRT1172xxxxx DAP stride is 1024 bytes (256 words) Inspected v.2 External Flash Device on SPI using SFDP JEDEC ID MIMXRT1170_SFDP_QSPI.cfx Image 'iMXRT1170_SFDP_FlexSPI1_A_QSPI Jul 2 2024 18:28:49' Opening flash driver MIMXRT1170_SFDP_QSPI.cfx Sending VECTRESET to run flash driver AFTER driver startup timeout (302 5ms retries) Driver Addresses Start: 20000000 Entry: 2000009D End: 20000834 Stack: 20002838 Mailbox:2000A838 Driver Register State R0: 400CC000 R1: 00000008 R2: 20000574 R3: 00000001 R4: 00000002 R5: 00000000 R6: 0000C270 R7: 00000000 R8: 00000000 R9: 00000000 R10: 00000000 R11: 00000000 R12: 00000004 SP: 200027E8 LR: 2000034B PC: 0021A114 xPSR: 61000000 MSP: 200027E8 PSP: 20002838 CFBP: 00000001 (CONTROL=0x0, FAULTMASK=0x0, BASEPRI=0x0, PRIMASK=0x1) Flash Driver V.2 startup failed - rc Ef(34): Timed-out initializing flash. chip initialization failed - Ef(34): Timed-out initializing flash. failed to initialize flash driver MIMXRT1170_SFDP_QSPI.cfx ( 65) Chip Setup Complete (100) Target Operation Failed Unable to perform operation! Command failed with exit code 1 11.9リリースと11.10リリースの付属のフラッシュローダーを試しましたが、どちらもシリアルダウンローダーブートモードでは機能しません。フラッシュローダーは11.8(LinkServer v1.0.9だと思います)に付属しており、問題なく動作します。リセット処理を VECTRESET から SYSRESETREQ に変更しようとしましたが、無駄でした。また、EPSRにハードフォールトが見られることもありますが、一貫しているわけではありません。私が欠落している他の構成が必要ですか?感謝 Re: MIMXRT1170 Flashloader の問題 私たちはあなたのユースケースを私たち側で確認し、問題を確認しました。11.8.0と11.10.0の間の機能の変更については正しいです。しかし、フラッシュからの起動では、私たちの側では同じ問題は発生しません。また、修正にも取り組んでいます。 ありがとうございました。 エイドリアン Re: MIMXRT1170 Flashloader の問題 残念ながら、そこでの動作に変更はありません。それがGUIフラッシュツールがうまく機能しないことを説明するかどうかはわかりません。プロジェクトの設定は 11.8 と 11.8/11.10 の間で変更されていません。どのフラッシュローダーが使用されているかだけです。MCUXpresso 11.10をRT1170の11.8フラッシュローダーに向けましたが、それも期待どおりに動作するので、フラッシュローダーの変更がこれを引き起こしているのでしょうか?このプロセッサの11.9変更ログで更新されたことを確認しました。感謝！ Re: MIMXRT1170 Flashloader の問題 フラッシュから起動するようにボードを構成してみて、結果をお知らせください。私たち自身も再確認します。 ありがとうございました。 エイドリアン

S32K344 - Peak LINとMCU間のLIN通信 ねえ皆さん 私はプロジェクトでS32K344 MCUを使用しており、Lin_MasterFrameTransfer_S32K344例を使用してMCUからPCへのLPUART通信を開始することができました。マイコンからPCへのLINフレームの転送に成功しました。 しかし、Peak-LINを使用してPC(Master)とMCU(Slave)からフレームを送信できません。メッセージが Peak Lin でエコーされているのがわかりますが、PC から MCU へのデータ受信方法に関するコードや設定が見つかりません。 AUTOSAR 4.4 - R21-11 RTD 3.0.0 で使用できた例をいくつか試しました 私はここでの初心者です。正しい方向を指し示してください。 ありがとうございます

MIMXRT1170 Flashloader 的问题 当尝试启动调试会话或运行 GUI 闪存工具时，我遇到了所提供的闪存加载器的问题。我们通常从已停止工作的串行下载器启动模式开始在我们的设备上进行调试会话。尝试重置闪存加载程序将失败，并导致超时。 以下是 LinkServer 控制台输出： Executing flash operation 'Erase' (Erase flash) - Tue Jul 23 13:29:09 PDT 2024 Checking MCU info... Scanning for targets... Executing flash action... MCUXpresso IDE RedlinkMulti Driver v11.10 (Jul 2 2024 19:33:51 - crt_emu_cm_redlink.exe build 741) ( 0) Reading remote configuration Wc(03). No cache support. Found chip XML file in C:/---/MIMXRT1172xxxxx.xml ( 5) Remote configuration complete Reconnected to existing LinkServer process. ============= SCRIPT: RT1170_connect_M7.scp ============= RT1170 Connect M7 Script DpID = 6BA02477 APID = 0x84770001 View cores on the DAP AP TAP 0: 6BA02477 Core 0: M7 APID: 84770001 ROM Table: E00FD003* ============= END SCRIPT ================================ Probe Firmware: MCU-LINK (r0FF) CMSIS-DAP V3.146 (NXP Semiconductors) Serial Number: JZ4FND0JCLDTD VID:PID: 1FC9:0143 USB Path: 0001:0008:00 Using memory from core 0 after searching for a good core ( 30) Emulator Connected ( 40) Debug Halt ( 50) CPU ID debug interface type = CoreSight DP (DAP DP ID 6BA02477) over SWD TAP 0 processor type = Cortex-M7 (CPU ID 00000C27) on DAP AP 0 number of h/w breakpoints = 8 number of flash patches = 0 number of h/w watchpoints = 4 Probe(0): Connected&Reset. DpID: 6BA02477. CpuID: 00000C27. Info: Debug protocol: SWD. RTCK: Disabled. Vector catch: Disabled. Content of CoreSight Debug ROM(s): RBASE E00FD000: CID B105100D PID 000008E88C ROM (type 0x1) ROM 1 E00FE000: CID B105100D PID 04000BB4C8 ROM (type 0x1) ROM 2 E00FF000: CID B105100D PID 04000BB4C7 ROM (type 0x1) ROM 3 E000E000: CID B105E00D PID 04000BB00C Gen SCS (type 0x0) ROM 3 E0001000: CID B105E00D PID 04000BB002 Gen DWT (type 0x0) ROM 3 E0002000: CID B105E00D PID 04000BB00E Gen (type 0x0) ROM 3 E0000000: CID B105E00D PID 04000BB001 Gen ITM (type 0x0) ROM 2 E0041000: CID B105900D PID 04001BB975 CSt ARM ETMv4.0 type 0x13 Trace Source - Core ROM 2 E0042000: CID B105900D PID 04004BB906 CSt type 0x14 Debug Control - Trigger, e.g. ECT ROM 1 E0043000: CID B105900D PID 04001BB908 CSt CSTF type 0x12 Trace Link - Trace funnel/router NXP: MIMXRT1172xxxxx DAP stride is 1024 bytes (256 words) Inspected v.2 External Flash Device on SPI using SFDP JEDEC ID MIMXRT1170_SFDP_QSPI.cfx Image 'iMXRT1170_SFDP_FlexSPI1_A_QSPI Jul 2 2024 18:28:49' Opening flash driver MIMXRT1170_SFDP_QSPI.cfx Sending VECTRESET to run flash driver AFTER driver startup timeout (302 5ms retries) Driver Addresses Start: 20000000 Entry: 2000009D End: 20000834 Stack: 20002838 Mailbox:2000A838 Driver Register State R0: 400CC000 R1: 00000008 R2: 20000574 R3: 00000001 R4: 00000002 R5: 00000000 R6: 0000C270 R7: 00000000 R8: 00000000 R9: 00000000 R10: 00000000 R11: 00000000 R12: 00000004 SP: 200027E8 LR: 2000034B PC: 0021A114 xPSR: 61000000 MSP: 200027E8 PSP: 20002838 CFBP: 00000001 (CONTROL=0x0, FAULTMASK=0x0, BASEPRI=0x0, PRIMASK=0x1) Flash Driver V.2 startup failed - rc Ef(34): Timed-out initializing flash. chip initialization failed - Ef(34): Timed-out initializing flash. failed to initialize flash driver MIMXRT1170_SFDP_QSPI.cfx ( 65) Chip Setup Complete (100) Target Operation Failed Unable to perform operation! Command failed with exit code 1 我已经尝试过 11.9 和 11.10 版本提供的闪存加载器，它们都无法在串行下载器启动模式下工作。闪存加载器配备 11.8（我认为是 LinkServer v1.0.9），它可以正常工作。我已经尝试将重置处理从 VECTRESET 更改为 SYSRESETREQ，但没有成功。我偶尔也会在 EPSR 中看到硬故障，但并不是一直存在。现在是否还需要一些我遗漏的其他配置？谢谢 回复：MIMXRT1170 Flashloader 问题 我们检查了您的使用案例并确认了该问题。您对 11.8.0 和 11.10.0 之间的功能变化的看法是正确的。然而，从闪存启动并没有出现我们这边的相同问题。我们也正在努力修复。 谢谢！ 阿德里安 回复：MIMXRT1170 Flashloader 问题 不幸的是，那里的行为没有改变。不确定这是否能解释 GUI Flash Tool 无法正常工作。项目的配置在 11.8 和 11.8/11.10 之间没有变化，只是使用了哪个 flashloader。我将 MCUXpresso 11.10 指向 RT1170 的 11.8 闪存加载器，它也能按预期工作，所以也许是闪存加载器的更改导致了这种情况？我确实看到它们在该处理器的 11.9 更新日志中进行了更新。谢谢！ 回复：MIMXRT1170 Flashloader 问题 您能否尝试将主板配置为从闪存启动并让我们知道结果？我们也会进行仔细检查。 谢谢！ 阿德里安

S32K344 - Lin communication between Peak LIN and MCU Hi Everyone, Iam using the S32K344 MCU in my project and I have managed to start LPUART communication from the MCU to my PC using the Lin_MasterFrameTransfer_S32K344 example. I was successful in transferring LIN frames from the MCU to the PC. However iam unable to send frames from my PC (Master) and the MCU (Slave) using Peak-LIN. I see my messages are getting Echoed in the Peak Lin but iam unable to find any code or configurations regarding how to receive data from the PC to the MCU. i have tried some of the examples that were available in the AUTOSAR 4.4 - R21-11 RTD 3.0.0 Iam just a beginner here. Please point me in the right direction. Thanks Re: S32K344 - Lin communication between Peak LIN and MCU Update: Got it figured out . Thanks for the help @PetrS  Thanks Re: S32K344 - Lin communication between Peak LIN and MCU Update: I chose "keep existing" and my code compiled successfully. I loaded the LDF file in Peak LIN and my Peak LIN reads the current motor temperature as 30 (HEX: 1E) as seen in the image. There are specific parts in the code that seem to rise and lower temperature as shown below. How am i supposed to change the temperature / call the function. Is there any LIN command that i need to send from my Peak LIN ?  Re: S32K344 - Lin communication between Peak LIN and MCU Hi, Thanks for the brief steps. Appreciated ! Yes Iam using RTD 4.0.0 with 2.0.4 Lin Stack and it is a custom board with S32K344 chip. But without making any changes, when i compile the project, as per the LINStack user manual chapter 6 Known issues and limitations, I clicked "Compare" and "Copy all Non-Conflicting changes" and "commit" i seem to get these errors: Please advise. Thank you Re: S32K344 - Lin communication between Peak LIN and MCU Hi, 1) if S32K344EVB is used, or custom board with similar HW connection, then so changes are needed. Just open example, and do code update, build and download into MCU sucessfully. Not sure of the RTD and stack version you have, but I tried the one in RTD4.0.0, stack 2.0.4 and the only steps I did was -mex file modification in external editor before opening in S32DS, search for src\LIN21.ldf and change it to src/LIN21.ldf - during code update allow changes for generated LinIf.h and LInIf.c as described in LINStack user manual chapter 6 Known issues and limitations Then project can be built and elf generated 2) in PCAN LIN you need to load ldf file from project, select Master node and then select and run Schedule Table from that ldf file. YOu can read PLIN VIew manual for more info. 3) I got similar errors in S32DS, however elf was succesfully generated. YOu can try to clean project, build again and/or close/reopen S32DS. BR, Petr Re: S32K344 - Lin communication between Peak LIN and MCU Hi, Thanks for the examples. Iam going ahead with the Lin_Slave_S32K344_Example_DS from the Linstack. Instead of the Master in another board, I want to use Peak LIN as master.  1. What are the changes that i need to make ? 2. Can you provide me step wise instructions on what i need to do to make it communicate with Peak LIN  3. Iam getting multiple errrors like the parameter McuClockSettingConfig_0 could not be resolved. I did not make any changes in peripheral except for changing the LPUART5 to LPUART1 and adding couple of Dio pins I also made sure that the Update_code is done thank you so much !!! Re: S32K344 - Lin communication between Peak LIN and MCU Hi, there are two RTD demos you can refer to, where LPUART is used as LIN Slave - "Lin_Ip_FrameTransfer_S32K344"...  simple application which shows a communication between a Lin Master and a Lin Slave of both Lpuart Ip and Flexio Ip  - "Lin_Slave_S32K344_Example_DS" ... LINStack example demonstrating the LIN communication between S32K344 Slave and other board Master using unconditional frames. BR, Petr Re: S32K344 - Lin communication between Peak LIN and MCU Hi Peter, Thanks for your response. I would like to have an example or code of a LIN slave demo where MCU responds according to the Frames sent from the Peak LIN.  Thanks Re: S32K344 - Lin communication between Peak LIN and MCU Hi, so do you want to add receive part into that master example? Means master is sending header and Peak-LIN responds with payload. Or you would like to rather have LIN slave demo, where Peak-LIN is initiating frames and K344 respond accordingly, receive payload or respond to request? BR, Petr

S32K344 - Peak LIN 与 MCU 之间的 Lin 通信 大家好， 我在我的项目中使用 S32K344 MCU，并且我已设法使用 Lin_MasterFrameTransfer_S32K344 示例启动从 MCU 到我的 PC 的 LPUART 通信。我已成功将 LIN 帧从 MCU 传输到 PC。 但是我无法使用 Peak-LIN 从我的 PC（主站）和 MCU（从站）发送帧。我看到我的消息在 Peak Lin 中得到回响，但我找不到有关如何从 PC 接收数据到 MCU 的任何代码或配置。 我已经尝试了 AUTOSAR 4.4 - R21-11 RTD 3.0.0 中的一些示例 我在这里只是一个初学者。请给我指出正确的方向。 谢谢！