请解释一下MC33665A比较表 我附上了 MC33665A 产品页面上提到的比较表，其中有 2 个 IC 可用。 我不明白这个参考中的网关到底是什么意思。 这是否意味着带有 CAN-FD 网关的 IC 将通过 CAN_FD 与 MCU 通信，SPI 也是如此？ 回复：请解释一下MC33665A比较表 谢谢

[imx8mp][android] WebGL Aquarium rendering issue As the title says, we encountered flickering and graphical issues when running the WebGL Aquarium demo on our NXP i.MX8MP SoC custom board with Android 12-15. I also tested it on an NXP i.MX8MP EVK board with the 15.0.0_1.0.0_DEMO_8MP Android prebuilt images, and the issue remains. Previously, we tested the same setup on our NXP i.MX8MP SoC custom board running Android 12-14 about a year ago, and it was working fine at that time. However, the issue seems to have appeared this year. We have attached a recording from our NXP i.MX8MP SoC custom board running Android 15 to showing the issue. IMX8MPLUS  Re: [imx8mp][android] WebGL Aquarium rendering issue Correct! is a known issue on Android devices. Regards Re: [imx8mp][android] WebGL Aquarium rendering issue Hello, Yes, I have tested it on our Yocto 5.0 OS, and it worked fine. The flickering issue seems to occur only on Android. Is this a known issue on Android? regards Re: [imx8mp][android] WebGL Aquarium rendering issue Hello, Weston is one process using GPU. It's able to see chromium-bin in the process list of gputop also. When browsering "webglsamples.org/aquarium/aquarium.html", we can see GPU usage going high. If chromium runs with "chromium --no-sandbox --disable-gpu", we can observe chromium-bin is not in GPU process list and usage is null. Also the web shows empty with "webglsamples.org/aquarium/aquarium.html". That proves GPU is enabled without "--disable-gpu". regards

Deploying trained model on FRDM-MCXN947 Hello,  I just bought the MCXN947 board, and I have my own pre-trained model as a TFLite file. I want to know the steps to implement it on my device because Im lost in the tutorials. MCXN Re: Deploying trained model on FRDM-MCXN947 thank you Harry, for your help I followed the links and i’m making progress. Re: Deploying trained model on FRDM-MCXN947 Hi @Abdu_  I think the following link will help you. eIQ FAQ - NXP Community eIQ Neutron NPU Lab Guides - NXP Community MCXN947: How to Train and Deploy Customer ML model to NPU - NXP Community Getting Started with TensorFlow Lite for Microcontrollers on i.MX RT - NXP Community BR Harry

How to know if the CPU is not working Hey, I have a question. Because my device needs a power saving mechanism. After 10 minutes, the user needs to enter suspend mode when not using the device. How do we know the user is not operating the device? Or do you know if the i.MX8M CPU has a register and can let us know? i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Re: How to know if the CPU is not working 1. user can use the command below to check if the system is in idle state. root@imx8mpevk:~# top -bn1 | grep -iE "Tasks|load|%Cpu" top - 07:40:26 up 15 min, 2 users, load average: 0.00, 0.02, 0.05 Tasks: 152 total, 1 running, 151 sleeping, 0 stopped, 0 zombie %Cpu(s): 0.0 us, 2.2 sy, 0.0 ni, 97.8 id, 0.0 wa, 0.0 hi, 0.0 si, 0.0 st when the "% idle" consistently is above 90% (here the example is 97.8 id), it means the system is in idle state. 2. User can test it with the examples below. - run command "echo mem > /sys/power/state" or "echo freeze > /sys/power/state". (press SW1 button to wakeup it on imx8mpevk) - run command "rtcwake -u -s 120 -m mem" to put the system into suspend to save power and then automatically wake up it after the specified time 120 seconds. Re: How to know if the CPU is not working Sorry, I forgot to say that. The operating system is yocto.

比較表MC33665A説明してください MC33665Aの製品ページに記載の2つのICが入手可能な比較表を添付しました。 このリファレンスでゲートウェイが正確に何を意味するのか理解できません。 CAN-FDゲートウェイ付きのICは、CAN_FDでMCUと通信し、SPIも同じということですか? Re:比較表MC33665A説明してください 感謝

Please explain MC33665A Comparison Table I have attached a comparison table mentioned on the product page of MC33665A where 2 IC are available. I am not able to understand what exactly gateway means in this reference. Does it mean that IC with CAN-FD gateway will communicate with MCU via CAN_FD and the same for SPI? Re: Please explain MC33665A Comparison Table thanks Re: Please explain MC33665A Comparison Table Dear Rohan, there are two MC33665A versions. There used to be three versions, but MC33665A UART to TPL transceiver was withdrawn from production. There are left CAN FD to TPL transceiver (or gateway MC33665ATF4AE) and the SPI to TPL transceiver (or gateway ). Both of them are used for controlling of more, than one BCC (Battery Cell Controller e.g. MC33774A) with one MCU. Please refer to white paper which can be downloaded from the MC33774A product page.  In the prinscreen below the MC33665 is the SPI to TPL gateway. With Best Regards, Jozef

Added support for GD25LQ128D qspi flash Now I am developing based on BSP34 branch and want to add GD25LQ128D qspi flash support under uboot. The device tree configuration is as follows, but I failed to read JEDEC, and I found that only macronix and micron products are supported based on this branch. What do I need to do if I want to support GD25LQ128D? Re: Added support for GD25LQ128D qspi flash Hello, Yes, you have to add you hardware to the device tree and create the drivers is needed it, but the BSP include driver for SPI you must check it. Regards

Can bus example on iMXRT1170-EVKB board Hi, I'm struggling to get one of  the CAN examples on my IMXRT1170-EVKB board to send messages over CAN bus. On the board I've connected CAN3 to a local test CAN bus going into a Teensy via a CAN transceiver with termination resistors. I am monitoring the RX and TX signals on the Teensy via a logic analyser. I ensure that the bus speed matches at both ends (1Mb/s) I've tried various examples for example "evkbmimxrt1170_flexcan_interrupt_transfer_cm7". When I run the example I see: * A breakpoint set in the interrupt "flexcan_callback" is never hit. * After selecting node "a" the code is stuck in the while (!txComplete) - which never completes as "txComplete" is set in the interrupt which is never called. * I don't see any signals on the logic analyser. * However, if I swap the IMXRT1170-EVKB for an IMXRT1064-EVK board I have and use the same example, the message is sent successfully.  I see the message arrive in the Teensy, appear on the logic analyser and the breakpoint is hit in the interrupt routine. So I don't think its my hardware setup. Any thoughts about what could be wrong and how to debug further. Thanks Nick Re: Can bus example on iMXRT1170-EVKB board Hi, I'm struggling to get one of the CAN examples on my IMXRT1170-EVKB board Transmit code is completed without interrupt ,but reception is not completed with or without interrupt,i have fallowing the same process as like transmitions. Re: Can bus example on iMXRT1170-EVKB board i have used same setup but its not working Re: Can bus example on iMXRT1170-EVKB board Here's the image I meant to attach Re: Can bus example on iMXRT1170-EVKB board Can you explain a little more about your setup. The setup that works for me is: * From MCUXpresso choose "import SDK example" and select "canfd_interrupt_transfer_cm7" * Connect CANH and CANL to CAN3 header - J47 see attached image * Connect another board to receive/transmit on CAN id: 0x123 or 0x321 (see sample), ensure the CAN data rate is setup identically at both ends * Connect a logic analyser to monitor what is happening on the CAN bus * Stick a break point in the code sample interrupt routine. * Run the sample. * Observe the message in the logic analyser and see the break point being hit in the interrupt routine. Hope this helps Nick  Re: Can bus example on iMXRT1170-EVKB board we face same issue and also try by removing jumpers j102 and j103 still not working Re: Can bus example on iMXRT1170-EVKB board For anyone that might suffer similar difficulties in the future the solution is to "Remove J102 and J103 jumpers.". I found this in the docs/readme.md associated with the CAN example ... I should have read the manual!

SPC5604 - How can I JTAG password lock ? Hello. I looking for some examples or documents for JTAG password lock in SPC5604. How can I JTAG password lock in SPC5604B ? Best Regards, SEAN SUNG Re: SPC5604 - How can I JTAG password lock ? Hello, Not sure here. I never tried it using CW. @stanish could you have a look at this? best regards, Peter Re: SPC5604 - How can I JTAG password lock ? Hello, Not sure what you mean. But if you are asking if SW can write to the shadow flash, then yes. Shadow flash is same as any other flash block, but used for configuration of device. Best regards, Peter Re: SPC5604 - How can I JTAG password lock ? Sorry, but there's another question. Can I directly inject the required configuration into the corresponding NVSCC0-1 and NVPWD0-1 register of censorship shadow flash through software injection? Re: SPC5604 - How can I JTAG password lock ? Hello, I am now encountering a problem, I am in the system initialization unlock erase and reprogram shadow flash (using the demo provided by your company), the startup process is Flash memory boot, censorship control register's config is SC == 55AA,CW !=55AA and I set a private password. Now the problem is that when the initialization is completed, when I enter the configured private password when debugging with CW 10.6, the following error will be reported, please help me answer the question of whether I should not directly operate the shadow flash during initialization. I hope you can help with this answer. Re: SPC5604 - How can I JTAG password lock ? Hello, You simply program censorship registers as described in reference manual: You will use common flash programming procedure as for any other flash. Best regards, Peter 回复： SPC5604 - How can I JTAG password lock ? How to write to the register NVPWD0 and NVPWD1 and NVSCI0 and NVSCI1？ 回复： SPC5604 - How can I JTAG password lock ? https://community.nxp.com/t5/MPC5xxx-Knowledge-Base/Example-MPC5604B-Shadow- Flash-Reprogramming/ta-p/1119903, this answers can write shadow block success

FreeMaster LITE 许可证不起作用 您好，我下载了 freeMaster Lite，当我在安装时输入许可证代码时收到此错误消息： 本站已使用 freemaster_lite 3.2 的软件激活码 然后安装程序回滚并且不允许我安装。 如何解决这个问题？ 谢谢 

FreeMaster LITEライセンスが機能しない こんにちは、私はインストールにライセンスコードを置くときにfreeMaster Liteをダウンロードしましたが、次のエラーメッセージが表示されます。 ソフトウェアアクティベーションコードは、このステーションでfreemaster_lite 3.2用にすでに使用されています その後、分割払いがロールバックされ、インストールできません。 これを解決する方法は? よろしくお願いします。

Bus fault investigate Hi NXP team, now I encounter a problem about Bus fault as below, I use the S32K148 MCU. how can I find this Bus fault address so that I go on investigate the root cause. Re: Bus fault investigate The address 0x805FFE55 is not implemented, any access there is invalid, refer to S32K1xx_Memory_Map.xlsx that is attached to the RM. Since the bus fault is precise, you can find the program counter address of the instruction that accesses the address on the Stack. Then, locate the program counter address in the disassembly window, it is probably a Load or Store instruction. Thanks, Daniel Re: Bus fault investigate Hi Daniel, the possible Bus fault location 0x805FFE55. Could you give me a hint what does this address(0x805FFE55) means?  Thanks Re: Bus fault investigate Hi @linton, This is a precise bus fault exception. Probably the program runs away and accesses this unimplemented memory. Stack overflow can be a possible root cause. You can find the PC address of the fault instruction on the Stack, follow this document: https://community.nxp.com/t5/S32K-Knowledge-Base/Fault-handling-on-S32K14x/ta-p/1114447 Regards, Daniel Re: Bus fault investigate the photo is not clear before, please see this:

I.MX8 MINI的PCIE问题 您好，我们使用i.MX 8M Mini Quad作为产品的主控制器，考虑到它不支持USB3.0的功能，我们就计划使用它的PCIE接口配合UPD720202K8-711-BAA-A芯片来实现USB3.0的功能。但是我在“i.MX 8M Mini Hardware Developer’s Guide”中看到“使用适当的外部 PCIe 参考时钟发生器”。我想了解一下为何要建议使用外部的PCIe时钟发生器呢？在我的这个方案中如果不作用外部时钟发生器可以吗？会有什么影响？ （我目前的设计是没有使用外部时钟发生器，UPD720202K8和I.MX8的PCIE_TX,PCIE_RX通过0.1uF电容相连，PCIE_CLK是直连的。） i.MX 8 Family | i.MX 8QuadMax (8QM) | 8QuadPlus i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Re: I.MX8 MINI的PCIE问题 现在我也是想要使用内部参考时钟，在设备树中将ext_osc属性改为了0，但是还是没有时钟输出可能是什么原因呢，使用的是Linux4.14.78版本的内核 Re: I.MX8 MINI的PCIE问题 Hi @mytemp  我们不建议客户使用内部时钟。根据我们的测试，内部时钟的抖动比标准高出约 30%。 不过内部PLL可以通过PCIe Gen 2 一致性测试，也有其他客户用内部时钟。还是建议你在测试阶段保留外部时钟，如果内部时钟无法达到你们的稳定性要求，可以切换到外部时钟。

FreeMaster LITE License not working Hello, I downloaded freeMaster Lite when I put the license code on the installation I get this error message: software activation code is already used on this station for freemaster_lite 3.2 Then the instalation rolls back and doesnt let me install. How to solve this? Thanks  Re: FreeMaster LITE License not working Hi @GabeLogan, Could you double check that the activation code is meant for your FreeMASTER Lite version. Latest version of FreeMASTER Lite is 1.3. During  the installation process you should be prompted to visit NXP site (the link is also available in the product description in the component selection of the installation process). You need to access that link only once when installing a newer version of FreeMASTER Lite. After this is done, you will see your license entitlement next to other product versions: Hope it help, Iulian

SPC5604 - 如何锁定JTAG密码？ 您好。 我正在寻找 SPC5604 中的 JTAG 密码锁的一些示例或文档。 如何在 SPC5604B 中锁定 JTAG 密码？ 顺祝商祺！ 肖恩·宋 回复：SPC5604 - 如何锁定 JTAG 密码？ 抱歉，还有一个问题。能否通过软件注入的方式直接将需要的配置注入到审查影子闪存对应的NVSCC0-1和NVPWD0-1寄存器中呢？ 回复： SPC5604 - How can I JTAG password lock ? 如何写入寄存器 NVPWD0 和 NVPWD1 以及 NVSCI0 和 NVSCI1？ 回复： SPC5604 - How can I JTAG password lock ? https://community.nxp.com/t5/MPC5xxx-Knowledge-Base/Example-MPC5604B-Shadow- Flash-Reprogramming/ta-p/1119903，此答案可成功写入阴影块

SPC5604 - JTAGパスワードをロックするにはどうすればよいですか? こんにちは、 SPC5604でJTAGパスワードロックの例やドキュメントを探しています。 JTAGのパスワードをSPC5604Bでロックするにはどうすればいいですか? よろしくお願いいたします。 ショーン・ソン Re:SPC5604 - JTAGパスワードロックはどのようにできますか? 申し訳ありませんが、別の質問があります。ソフトウェアインジェクションを通じて、対応する NVSCC0-1 および NVPWD0-1 レジスタに必要な設定を直接挿入できますか? 回复： SPC5604 - How can I JTAG password lock ? レジスタ NVPWD0 と NVPWD1 および NVSCI0 と NVSCI1 に書き込むにはどうすればいいですか? 回复： SPC5604 - How can I JTAG password lock ? https://community.nxp.com/t5/MPC5xxx-ナレッジベース/例-MPC5604B-シャドウ- Flash-Reprogramming/ta-p/1119903、この回答はシャドウブロックの成功をCAN

EB Tresos 激活失败 您好，我尝试使用 EB Client License Administrator V1.5.1 激活 EB Tresos，激活码为： 20EA-CB05-14E2-FC19（有效期至 2024 年 6 月 30 日） ，但失败了，以下是激活日志： 信息：可信存储初始化完成。 激活 NodeLocked 许可证 20EA-CB05-14E2-FC19，许可证数量：1 状态：4，正在创建请求 状态：5，请求已创建 状态：6，上下文已创建 状态：7，已连接到远程服务器 状态：8，请求已发送 状态：9，轮询响应 状态：10，等待响应 状态：9，轮询响应 状态：10，等待响应 状态：9，轮询响应 状态：10，等待响应 状态：9，轮询响应 状态：10，等待响应 状态：9，轮询响应 状态：10，等待响应 状态：9，轮询响应 状态：10，等待响应 状态：9，轮询响应 状态：10，等待响应 状态：9，轮询响应 状态：10，等待响应 状态：9，轮询响应 状态：10，等待响应 状态：9，轮询响应 状态：10，等待响应 状态：9，轮询响应 状态：10，等待响应 状态：9，轮询响应 状态：10，等待响应 状态：9，轮询响应 状态：10，等待响应 状态：9，轮询响应 状态：10，等待响应 状态：9，轮询响应 状态：10，等待响应 状态：9，轮询响应 状态：10，等待响应 状态：9，轮询响应 状态：11，完成 错误：flxActAppActivationSend (50040,41147,10249) 无法获取锁：ELKB，CertificateQuantity，178844298 与 FlexNet Operations Server 的连接失败。 我该如何解决呢，谢谢！ 回复：EB Tresos 激活失败 您好，什么时候可以拿到新的激活码？ 回复：EB Tresos 激活失败 非常感谢

PN7150天线模型测量与仿真 您好，我正在尝试根据 AN12810 使用 nanovna 将我的 PN7150 系统与 Taoglas FXC.30.52.0075X.A.dg nfc 天线进行匹配，但我不确定我是否正确地完成了单独测量天线的第一步。 我调用了 nanovna 并将其直接连接到没有匹配电路的天线，得到了我所附的结果，它与预期的 AN12810.fig18 类似。 但是构建 rfsim99 模型时我使用了天线 ds 中给出的值，但我不知道如何让 sim 模型与测量结果相匹配作为起点。 我能得到一些关于如何改进模型的建议吗？ 回复：PN7150天线模型测量与模拟 嗨，托马斯，谢谢，这很有帮助！ 供其他关注的人参考，rfsim99 似乎只导入了 s1p 的前 2000 个点，因此您需要相应地裁剪或减少文件。 回复：PN7150天线模型测量与模拟 谢谢，我忘了说，作为这个项目的一部分，我正在考虑将设计从 PN7150 更新到 PN7160。关于这方面没有问题。 但是您是否读过我的问题并且对改进我的天线模型有什么见解？ 回复：PN7150天线模型测量与模拟 你好@gwctree42 希望你一切都好。 请注意，不建议将PN7150用于新设计。我们建议改用PN7160 。 您需要根据从天线测量的值来计算 EMC 滤波器和匹配网络的组件。 请查看PN7150 天线设计和匹配指南。第 3 章描述了天线匹配的程序。此外， NFC 天线工具可能对您非常有帮助。 此外，请参考NFC 天线设计培训，这是一个在线培训系列，可以帮助您了解天线的关键方面、优化和调试以及测试，以获得最适合产品的天线。 问候， 爱德华多。

When is SSRAM accessible before s32_ssram_clear? Hi Sir, enum reset_cause {     CAUSE_POR,     CAUSE_DESTRUCTIVE_RESET_DURING_RUN,     CAUSE_DESTRUCTIVE_RESET_DURING_STANDBY,     CAUSE_FUNCTIONAL_RESET_DURING_RUN,     CAUSE_FUNCTIONAL_RESET_DURING_STANDBY,     CAUSE_WAKEUP_DURING_STANDBY,     CAUSE_ERROR,     CAUSE_MAX_NUM }; Which reset reason is SSRAM accessible before s32_ssram_clear function? Best regards, Jeff Huang Re: When is SSRAM accessible before s32_ssram_clear? Hello @Jeff-CF-Huang, Thanks for the clarification, I did understand the question differently. To know when exactly the SSRAM content is retained please check the section 28.7 Chip status on reset exit of the Reference manual [page 1150, S32G2 Reference Manual, Rev. 8, February 2024]: Please check the reference manual for full information. In the table I mentioned before you can see the resets that are of type functional: About the status of the SSRAM you can check the 35.3.5 Platform RAM Status Register (PRAMSR) register to know if it was successfully initialized and therefore can be accessed [page 1436, S32G2 Reference Manual, Rev. 8, February 2024]: You can learn more about how to initialize the SSRAM in section 35.1.4 Initialization, under Chapter 35 SRAM Controller (SRAMC) [page 1427, S32G2 Reference Manual, Rev. 8, February 2024]: My understanding is that with a functional reset (this is when the information is retained) the SSRAM should not loose the initialization status and therefore you should be able to read it without problems. Please note that the SSRAM depends on the STANDBY power domain (VDD_IO_STBY), so that voltage needs to be kept in order to retain the SSRAM data. I used the S32G2 RM as reference since I do not know which component you are using. Let me know if this information solved your question. Re: When is SSRAM accessible before s32_ssram_clear? Hi Alejandro, It seems there’s a misunderstanding. The s32_ssram_clear function initializes and clears the SSRAM in BL2 of ATF. If we want to retrieve data from SSRAM after an XXX reboot, we need to access SSRAM before this function is called. However, we are unsure which type of reboot allows SSRAM to be safely read. From what we know, reading SSRAM before s32_ssram_clear during a POR scenario results in a system fault. Best regards, Jeff Huang Re: When is SSRAM accessible before s32_ssram_clear? Hello @Jeff-CF-Huang,  Checking the reference manual for the registers value for reset (MC_RGM_DES and MC_RGM_DES) which are read in function  static enum reset_cause get_reset_cause(void) [.../arm-trusted-firmware/plat/nxp/s32/s32cc/s32g/s32g_bl2_el3.c][page 1139, S32G2 Reference Manual, Rev. 8, February 2024] (please check the full table in the document for better reference): I was not able to find any error directly related to the a SSRAM access. Please provide the following information to have better context of your setup: Have you experienced problems when accessing the SSRAM before clearing it?  Are you using a S32G2 or S32G3? Which version of the BSP are you using? Are you using a multicore setup? this is M7 and A53 cores which boot type are you using? QSPI, SD, eMMC, serial Are you using a custom board or a RDB board? Are you using the GCC version indicated in your BSP user manual? Thanks for the information in advance.

TJA1029Tk - How to interpret hysteresis specification for TXD and SLP_N? Hi, In the datasheet of TJA1029  at pg no: 11, we could find Vhys hysteresis voltage max mentioned as 400mV How to use this data for logic level compatibility check with other ICs? What is the use of this hysteresis voltage being mentioned? Should we do like below? VIH = 2V + 0.4V  = 2.4V VIL = 0.8V - 0.4V = 0.4V Please guide Thanks, Sri Viswa Re: TJA1029Tk - How to interpret hysteresis specification for TXD and SLP_N? Hi, The hysteresis voltage is used to ensure noise immunity and stable operation. It ensures that the input signal has a clear margin to avoid false triggering due to noise. You do not need to adjust VIH and VIL using the hysteresis voltage. Instead, ensure that the driving IC's output levels meet the VIH and VIL requirements of the TJA1029TK. BRs, Tomas