Exporting S32CT .mex configuration to EB Tresos Hello NXP support, is there a way to export/transform an S32CT configuration .mex file into something that can be read/imported/consumed by EB TRESOS?  I need to switch to EB tresos without manually transferring every configuration item. I have attached an example .mex file from my projects as references. Re: Exporting S32CT .mex configuration to EB Tresos Hello @DirkEtzler Unfortunately, there is no automatic conversion tool or plugin to migrate S32DS (.mex) configurations into EB tresos (.arxml) format. S32 Configuration Tools use the .mex format, while EB Tresos follows the .arxml AUTOSAR standard and differs significantly in schema and constraints.   The recommended approach is to recreate the configuration in EB tresos manually, using the .mex configuration and generated driver code as a reference. You can follow the RTD MCAL Based in Tresos Training for some guidance.   In case you come up with any issues during migration, you submit your query and we will be happy to assist.   Best regards, Julián Re: Exporting S32CT .mex configuration to EB Tresos Hello @Julián_AragónM , thanks for the quick reply.  I will follow the guidelines, and when I hit a roadblock post my question(s).

i.MX8MM eMMC sd3 时钟 dse en 转换速率设置 上述打击垫控制设置并未在参考手册中描述。我们为什么要测试/调整这些设置？以及如何测试/调整这些设置？ Re: i.MX8MM eMMC sd3 clk dse en slew rate setting 你好@NLFOHE 希望你一切都好。 实际上，该焊盘位于寄存器名称下方：IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B。 Manuel_Salas_0-1785352172806.png 多路复用模式寄存器应配置为 uSDHC3 (IOMUXC_SW_MUX_CTL_PAD_NAND_WE_B): Manuel_Salas_1-1785352244434.png 顺祝商祺！ 萨拉斯。 Re: i.MX8MM eMMC sd3 clk dse en slew rate setting 你好，萨拉斯， 由于假期原因，问题尚未解决。是否有关于如何在这个特定时钟信号上使用 SCC 的应用笔记？

i.MX8MM eMMC sd3 clk dse en slew rate setting The above mentioned pad control settings are not described in the reference manual. Why and how can we test / trim these settings? Re: i.MX8MM eMMC sd3 clk dse en slew rate setting Hello @NLFOHE  Hope you are doing very well. Actually, that pad is under the register's name: IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B. Manuel_Salas_0-1785352172806.png Mux mode register should be configured as uSDHC3 (IOMUXC_SW_MUX_CTL_PAD_NAND_WE_B): Manuel_Salas_1-1785352244434.png Best regards, Salas. Re: i.MX8MM eMMC sd3 clk dse en slew rate setting Hello Salas, Issue not yet solved due holiday period. Is there any application note how to use SCC on this specific clock signal?

S32K144 GPT 通知回调在 SRTC 通道上未触发信号 - MCAL RTM 1.0.6 (AUTOSAR 4.2) + EB 您好，NXP团队， 我正在使用以下 S32K144 进行项目开发： MCAL 软件包：S32K1XX_MCAL4_2_RTM_1_0_6 AUTOSAR 版本：4.2.2 EB Tresos 版本：29.0 设备：S32K144 我遇到的问题是，尽管计时器本身似乎运行正常，但 GPT 通知回调却没有收到触发信号。 GPT 配置 EB Tresos 中 GPT 通道的配置如下： 硬件模块：SRTC 频道：SRTC_0_CH_0 模式：连续 通知：已启用 extern void Gpt_Notification(void); static CONST(Gpt_ChannelConfigType, GPT_CONST) Gpt_InitChannelPB[1] = { { （布尔值）FALSE， &Gpt_Notification， ... （Gpt_ChannelModeType）（GPT_CH_MODE_CONTINUOUS）， { (uint8)(SRTC_0_CH_0), (uint8)(GPT_SRTC_MODULE) ... } } }; Gpt_GetTimeElapsed()（在应用程序代码中使用）返回的值在运行时持续增加，这表明： GPT初始化成功。 GPT定时器启动成功。 SRTC计时器计数正常。 然而： Gpt_Notification() 函数从未被调用。 Gpt_Notification() 函数内部的断点永远不会被触发。 请问您能否帮忙澄清一下： S32K1XX_MCAL4_2_RTM_1_0_6 中 SRTC_0_CH_0 上的 GPT 通知是否存在已知问题？ 基于 SRTC 的 GPT 是否需要在 GPT 模块配置之外进行任何额外的 NVIC 或中断配置？ 或者其他任何可能被遗漏的要点。 此致， 艾西瓦娅 Re: S32K144 GPT Notification Callback Not Triggering on SRTC Channel - MCAL RTM 1.0.6 (AUTOSAR 4.2) 嗨@Aishwr 请检查： EB Tresos 中的 GptIsrEnable - 转到 Gpt -> GptHw配置-> GptHwInterruptChannel。找到 SRTC_0_CH_0 的条目。检查 GptIsrEnable 和 GptChannelIsUsed 是否都已启用。这两个值的默认值均为 false，因此必须显式启用，否则 SRTC 信道的 ISR 将不会激活。 在应用程序代码中调用 Gpt_EnableNotification() - 仅仅在 EB Tresos 中配置通知功能是不够的。在 Gpt_StartTimer() 之后，必须在应用程序中显式调用 API Gpt_EnableNotification(GptConf_GptChannelConfiguration_ )。如果没有这个调用，即使定时器正确触发，司机也不会发送通知。 中断控制器初始化 – 根据用户手册中提到的驱动程序偏差 SWS_Gpt_00355 和 SWS_Gpt_00356，集成代码必须在使用 GPT 驱动程序之前启用 NVIC 中的 RTC/SRTC 中断线。这不是 Gpt_Init() 函数能做到的。请检查此操作是否在您的启动代码或集成代码中执行，以及是否在调用 Gpt_StartTimer() 之前执行。 此致， Lukas

S32K144 GPT Notification Callback Not Triggering on SRTC Channel - MCAL RTM 1.0.6 (AUTOSAR 4.2) + EB Hello NXP Team, I am working on an S32K144 project using: MCAL Package: S32K1XX_MCAL4_2_RTM_1_0_6 AUTOSAR Version: 4.2.2 EB Tresos Version: 29.0 Device: S32K144 I am facing an issue where a GPT notification callback is not being triggered, although the timer itself appears to be running correctly. GPT Configuration The GPT channel is configured in EB Tresos as: Hardware Module: SRTC Channel: SRTC_0_CH_0 Mode: Continuous Notification: Enabled extern void Gpt_Notification(void); static CONST(Gpt_ChannelConfigType, GPT_CONST) Gpt_InitChannelPB[1] = { { (boolean)FALSE, &Gpt_Notification, ... (Gpt_ChannelModeType)(GPT_CH_MODE_CONTINUOUS), { (uint8)(SRTC_0_CH_0), (uint8)(GPT_SRTC_MODULE), ... } } }; The value returned by Gpt_GetTimeElapsed()(used in application code ) continuously increases during runtime, indicating that: GPT initialization is successful. GPT timer starts successfully. SRTC timer is counting correctly. However: Gpt_Notification() is never called. Breakpoint inside Gpt_Notification() is never hit. Could you please help clarify: Is there any known issue with GPT notifications on SRTC_0_CH_0 in S32K1XX_MCAL4_2_RTM_1_0_6? Does SRTC-based GPT require any additional NVIC or interrupt configuration outside the GPT module configuration? or any other point, that may have missed. Regards, Aishwarya Re: S32K144 GPT Notification Callback Not Triggering on SRTC Channel - MCAL RTM 1.0.6 (AUTOSAR 4.2) Hi @Aishwr  Please check: GptIsrEnable in EB Tresos - Go to Gpt -> GptHwConfiguration -> GptHwInterruptChannel. Find the entry for SRTC_0_CH_0. Check that both GptIsrEnable and GptChannelIsUsed are enabled. The default value for both of these is false, so they must be explicitly turned on, otherwise the ISR for the SRTC channel will not be active. Gpt_EnableNotification() call in your application code - Configuring the notification function in EB Tresos is not enough on its own. The API Gpt_EnableNotification(GptConf_GptChannelConfiguration_ ) must be called explicitly in your application after Gpt_StartTimer(). Without this call, the driver will not deliver the notification even if the timer fires correctly. Interrupt controller initialization – per driver deviations SWS_Gpt_00355 and SWS_Gpt_00356 mentioned in user manual, integration code must enable the RTC/SRTC interrupt line in the NVIC before using the GPT driver. This is not done by Gpt_Init(). Please check whether this is done in your startup or integration code, and whether it happens before Gpt_StartTimer() is called. Regards, Lukas

Will multiple Ara240's support P2P communication? Subject says everything. Can you connect multiple Ara240's through an appropriate PCIe switch and use P2P communication to run larger models? Re: Will multiple Ara240's support P2P communication? db16122_0-1785805134624.png The online resource for ARA24 is quite limited but it would be helpful with BAR2 content

对基于SoM设计的iMX95 PMIC输出存在疑问 我想制作一个基于 iMX95 的定制 PCB，我以 iMX95 SoM 原理图作为参考，引用原理图。 据我了解，PF09 将是主电源管理芯片，它将产生除 SoC 和 ARM 内核电压之外的所有电压，这些内核电压由 pf530x 产生。 我的疑问是： 1.在 PF09 的参考原理图中，LDO3 也构成了 VDD_SoC 电压线，这是为什么呢？ 2. 数据显示它只能提供最高 200mA 的电流，但 SoC 的电流需求远高于此，如果 PF09 和 PF530x 都输出相同的电压，那就相当于电源线短路了，在这种情况下，PF09 的引脚会吸收电流并导致问题吗？ 3. 我是否可以移除 Pf09 低压差线性稳压器\(LDO\) 的电源输出，只使用另一个低压差线性稳压器\(LDO\)，这样可以吗？（请就“我是否应该删除”或“我是否可以删除”给出明确的建议） 下面附上图片供参考。 PF09 输出 PF530x 用于 VDD_SOC 生成

Skywell BE11 Head unit Brick mode Hello, I am Attila Potondi from Hungary. I would like to ask for your help in restoring the head unit to its original state. I bought the car used in Germany, but I have not received any response to my letters to the Skywell dealership. The VIN number is: LMELBL1P4NRC03065 Skywell BE11 NXP i.MX8QXP proc. Unfortunately, neither the distributor in either country nor the manufacturer answers the questions, so I am turning to you. I would like to delete some APKs via terminal, which crashed the system and asked for a password via the terminal. Thank you Attila Re: Skywell BE11 Head unit Brick mode Hello, I’d be very careful with this, especially since the head unit is already unstable. On an i.MX8QXP-based system, deleting system APKs or changing files from the terminal can easily leave Android unable to boot. Without the exact Skywell firmware/build and the correct recovery procedure, I wouldn’t recommend guessing the terminal password or removing more packages.

LIN to CAN in MBD I am using NXP MBD blockset and getting feedback from a LIN slave on CANoe using LIN receive frame block,and i am trying to publish the LIN feedback in CAN bus using CAN send block.To do this,I am using demux to the data which is giving me an dimension error and i am unable to use ldf file also and i tried storing the data in a storage and reading it from the storage,which doesnt give me any error but i am unable to publish the data. Re: LIN to CAN in MBD Hello, What MATLAB do you use? What toolbox do you use? If possible, can you try to send a snippet of the model and the received error? Best regards, Sorin Bancila

mcxn947 dma传输开启后没有进入回调 #include "fsl_debug_console.h" #include "pin_mux.h" #include "clock_config.h" #include "board.h" #include "app.h" #include "fsl_flexio_spi_edma.h" #include "board.h" //#include "app.h" #include "fsl_debug_console.h" void BOARD_InitHardware(void); #include "fsl_debug_console.h" #include "fsl_flexio.h" #include "fsl_edma.h" #include "fsl_inputmux.h" #include "fsl_common.h" /* 硬件常数定义 */ #define DEMO_FLEXIO_BASE FLEXIO0 #define DEMO_DMA_BASE    DMA0 #define DEMO_DMA_CH      0  /* 使用 DMA 通道 61 */ #define CHANNEL_COUNT    20  /* 20路并行引脚 */ #define BIT_DEPTH        24  /* 24位深度 */ #define SHIFTERS_USED    8   /* 每次 DMA 填充 8 个 Shifter */ /* 数据缓冲区：必须对齐以优化 DMA 性能 */ SDK_ALIGN(uint32_t g_dac_buffer[BIT_DEPTH], 32); edma_handle_t g_edma_handle; volatile bool g_transfer_done = false; /* DMA 完成回调 */ void EDMA_Callback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds) {    if (transferDone)    {        /* 确保 FlexIO 最后一组数据已从移位寄存器彻底发出 */        while (!(FLEXIO_GetShifterStatusFlags(DEMO_FLEXIO_BASE) & 0x01U));        /* 立即关闭 DMA 请求，防止产生虚假触发 */        FLEXIO_EnableShifterStatusDMA(DEMO_FLEXIO_BASE, 1 << 0, false);        g_transfer_done = true;    } } void Init_FlexIO_DAC(void) {    flexio_config_t fxioConfig;    flexio_shifter_config_t shConfig = {0};    flexio_timer_config_t timConfig = {0};    FLEXIO_GetDefaultConfig(&fxioConfig);    FLEXIO_Init(DEMO_FLEXIO_BASE, &fxioConfig);    FLEXIO_Reset(DEMO_FLEXIO_BASE);    /* 配置 8 个 Shifter 并行输出 */    for (uint8_t i = 0; i < SHIFTERS_USED; i++)    {        shConfig.timerSelect   = 0;        shConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive;        shConfig.pinConfig     = kFLEXIO_PinConfigOutput;        shConfig.pinSelect     = 0;  /* 引脚从 D0 开始 */        shConfig.pinPolarity   = kFLEXIO_PinActiveHigh;        shConfig.shifterMode   = kFLEXIO_ShifterModeTransmit;        shConfig.inputSource   = kFLEXIO_ShifterInputFromPin;        shConfig.shifterStop   = kFLEXIO_ShifterStopBitDisable;        shConfig.shifterStart  = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;        shConfig.parallelWidth = CHANNEL_COUNT - 1U; /* 20路并行宽度 */        FLEXIO_SetShifterConfig(DEMO_FLEXIO_BASE, i, &shConfig);    }    /* 配置 Timer 0 作为 SCLK 时钟源 */    timConfig.triggerSelect   = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(0);    timConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow;    timConfig.triggerSource   = kFLEXIO_TimerTriggerSourceInternal;    timConfig.pinConfig       = kFLEXIO_PinConfigOutput;    timConfig.pinSelect       = 20; /* 时钟信号输出在 D20 */    timConfig.timerMode       = kFLEXIO_TimerModeDual8BitBaudBit;    timConfig.timerDisable    = kFLEXIO_TimerDisableOnTimerCompare;    timConfig.timerEnable     = kFLEXIO_TimerEnableOnTriggerHigh;    /* 8个位 = 16个边沿 (15), 频率分频 = 10 */    timConfig.timerCompare    = (15U << 8U) | 10U;    FLEXIO_SetTimerConfig(DEMO_FLEXIO_BASE, 0, &timConfig); } void Init_DMA_DAC(void) {    edma_config_t edmaConfig;    /* 修正后的 MCXN947 InputMux 连接 */    /* 如果 kINPUTMUX_Flexio0Shift0ToDma0Ch61Ena 依然报错，       请尝试 kINPUTMUX_Flexio0Request0ToDma0Ch61Ena */    INPUTMUX_Init(INPUTMUX0);    //INPUTMUX_EnableSignal(INPUTMUX0, kINPUTMUX_Flexio0Shift0ToDma0Ch61Ena, true);    INPUTMUX_EnableSignal(INPUTMUX0, kINPUTMUX_FlexIO0ShiftRegister0RequestToDma0Ch61Ena, true);    EDMA_GetDefaultConfig(&edmaConfig);    EDMA_Init(DEMO_DMA_BASE, &edmaConfig);    EDMA_CreateHandle(&g_edma_handle, DEMO_DMA_BASE, DEMO_DMA_CH);    EDMA_SetCallback(&g_edma_handle, EDMA_Callback, NULL); } void DAC_Transmit(void) {    edma_transfer_config_t xferConfig;    edma_minor_offset_config_t offsetConfig;    g_transfer_done = false;    /*       参数修正说明：       1. bytesEachRequest = 32  (每次触发搬运 8 个 Shifter，每个 4 字节)       2. transferBytes = 96     (总共 24 位数据，每位 4 字节，24 * 4 = 96)       这样 96 % 32 == 0，断言即可通过。    */    EDMA_PrepareTransferConfig(&xferConfig,                               (void *)g_dac_buffer,                /* srcAddr */                               4,                                   /* srcWidth: 4字节 */                               4,                                   /* srcOffset: 4 */                               (void *)&(DEMO_FLEXIO_BASE->SHIFTBUF[0]), /* destAddr */                               4,                                   /* destWidth: 4字节 */                               4,                                   /* destOffset: 4 */                               32,                                  /* bytesEachRequest: 32 */                               96                                   /* transferBytes: 96 (！！！修正点) */                               );    /* 提交配置 */    EDMA_SubmitTransfer(&g_edma_handle, &xferConfig);    /* 配置地址回退：Minor Loop 结束后，目的地址减去 32 字节回到 SHIFTBUF[0] */    offsetConfig.enableSrcMinorOffset  = false;    offsetConfig.enableDestMinorOffset = true;    offsetConfig.minorOffset           = -32;    EDMA_SetMinorOffsetConfig(DEMO_DMA_BASE, DEMO_DMA_CH, &offsetConfig);    /* 启动 DMA 和 FlexIO 请求 */    EDMA_StartTransfer(&g_edma_handle);    FLEXIO_EnableShifterStatusDMA(DEMO_FLEXIO_BASE, 1 << 0, true); } int main(void) {    /* 基础硬件初始化 (时钟/引脚) */    BOARD_InitHardware();    Init_FlexIO_DAC();    Init_DMA_DAC();    /* 示例数据填充 */    for(int i=0; i<BIT_DEPTH; i++) g_dac_buffer[i] = 0xAAAAA;    while (1)    {        DAC_Transmit();        /* 等待回调执行 */        while(!g_transfer_done);        /* 间隔 */        SDK_DelayAtLeastUs(1000, SystemCoreClock);    } }     程序卡死在    while(!g_transfer_done);  没有往下走 。 请问哪里出了问题 Communication & Control(I3C | I2C | SPI | FlexCAN | Ethernet | FlexIO) Re: mcxn947 dma传输开启后没有进入回调 The callback was not executed. Which channel should be used for DMA here? Channel 61 won't pass the assertion; it cannot exceed 16. If the DMA channel is set to 0, the DMA callback will not be entered at all. Re: mcxn947 dma传输开启后没有进入回调 Hi @justdomyself 1) Set breakpoints for debugging and check if the eDMA interrupt and callback functions have been entered. 2) Confirm which eDMA channel is being used. #define DEMO_DMA_CH      / * Using DMA channel 61 */ It seems that channel 0 is being used here. INPUTMUX_EnableSignal(INPUTMUX0, kINPUTMUX_FlexIO0ShiftRegister0RequestToDma0Ch61Ena, true); However, judging from the comments and this line of code, it seems to be using Chaanel 61. BR Alice

imx95 + la12xx hi NXP Problem Description: I'm currently using an IMX95 and a LA1234 connected via PCIe. I've compiled the kernel driver for hostsw_la12xx and loaded yami.ko, but I can't detect the LA1234 device using LSPCI. 1. I don't have a program for burning into my LA1234. Do I need to burn the program before I can view it via LSPCI? How do I burn the program? Re: imx95 + la12xx Based on the observed phenomena, the current problem is most likely not caused by the yami.ko compilation or loading process on the host side. lspci The premise for seeing LA1234 is that LA1234 has already started normally as a PCIe Endpoint and the PCIe link has been successfully trained. If no programs have been flashed/booted on the LA1234, it's reasonable that the i.MX95 side cannot see the LA1234 via lspci . The LA1234 needs to boot from a supported boot source to run the LA12xx BSP/FreeRTOS/PCIe EP firmware, completing the PCIe Endpoint initialization, before the i.MX95, as the Root Complex, can enumerate the device. hostsw_la12xx/kernel_driver/yami.ko This is the host Linux-side LA12xx PCIe driver. It typically handles further LA12xx initialization after the PCIe device has been enumerated by the host, such as PCIe inbound/outbound windows, e200 OS boot, VSPA image boot, IPC/RFIC, etc. It cannot allow the device to appear directly in lspci if the PCIe EP is not fully enabled on the LA1234 side. We recommend checking in the following directions first: Verify that the LA1234 boot mode/boot source is correct, and that the LA1234 has started the LA12xx BSP/FreeRTOS image containing the PCIe Endpoint driver. Confirm that the LA1234 PCIe controller is configured as EP, and the i.MX95 side is configured as RC. Check if PCIe REFCLK, PERST#, power sequence, SerDes lane settings, and lane width/speed are matched. The i.MX95 side first executes dmesg | grep -i pcie , echo 1 > /sys/bus/pci/rescan , and lspci -nn -vv to check if there are any endpoint enumerations. If there is still no device, it is recommended to first connect to the i.MX95 with a known working PCIe endpoint to confirm that the i.MX95 RC side hardware and device tree/kernel configuration are correct; then go back to the LA1234 side to check EP boot and hardware connection. To program the LA1234, you need to use the LA1234/LA12xx board boot image and corresponding programming process provided in the LA12xx SDK/BSP. The publicly available hostsw_la12xx repository mainly contains host-side software; the FreeRTOS side code is not in this repository. Therefore, you need to refer to the sections on LA12xx board boot and image programming in the LA12xx SDK User Guide / BSP release package.

S32G399には、DDRベースの共有メモリをAコアとMコアの両方でアクセスできるように設定してください。 チップS32G399では、DDRベースの共有メモリをAコアとMコアの両方がアクセスできるように設定してください。実装例やデモはありますか？ Re: For S32G399, configure DDR‑based shared memory to be accessed by both A‑Core and M‑Core. こんにちは、 @zhijie 投稿ありがとうございます。 私の知る限り、そのような正式なデモやサンプルは存在しないようですので、ご自身で開発する必要があるかもしれません。 MコアとAコア間の通信については、現在NXPがIPCFを提供していますが、デフォルトではSRAMをベースとしています。 BR チェイン Re: For S32G399, configure DDR‑based shared memory to be accessed by both A‑Core and M‑Core. NXPコミュニティ内でそのような実装を完成させた開発者はいらっしゃいますか?関連資料や経験談のご提供をいただければ大変ありがたく存じます。

SoM設計に基づくiMX95 PMIC出力に関する疑問 iMX95をベースにしたカスタムPCBを作成したかったので、iMX95 SoMの回路図をリファレンス回路図として使用しています。 私の理解では、PF09はマスターPMICとなり、SoCとARMコアの電圧を除くすべての電圧を出力します。これらのコア電圧はpf530xによって作られています。 私の疑問点は以下の通りです。 1.参照回路図では、PF09のLDO3がVDD_SoC電圧ラインも構成していますが、これはなぜでしょうか？ 2. そして、最大200mAまでしか供給できないことが示されていますが、SoCの電流要求はそれ以上で、もしPF09とPF530xの両方が同じ電圧を出しているなら、それは電源線をショートさせるようなものです。その場合、PF09のピンが電流を吸収して問題を引き起こすのでしょうか? 3. Pf09 LDOの電源出力を外して、もう一方のLDOを使うべきか、またはCANでしょうか?動作しますか?(「削除すべきか」や「CAN」など、明確な提案をしてください) 参考用の画像を下に添付します PF09の出力 VDD_SOC生成にPF530xを使用

For S32G399, configure DDR‑based shared memory to be accessed by both A‑Core and M‑Core. For chip S32G399, configure DDR‑based shared memory to be accessed by both A‑Core and M‑Core. Are there any implementation schemes and demos available? Re: For S32G399, configure DDR‑based shared memory to be accessed by both A‑Core and M‑Core. Hello, @zhijie  Thanks for your post. As far as I know, there seems no such similar formal demo/examples existed, you may need to develop it yourself. For communication between M and A cores, currently IPCF is provisioned by NXP, but it is by default based on SRAM. BR Chenyin Re: For S32G399, configure DDR‑based shared memory to be accessed by both A‑Core and M‑Core. Has any developer within the NXP Community completed such an implementation? Relevant documents or experience sharing will be greatly appreciated.

mcxn947 dma传输开启後没进入回调 #include "fsl_debug_console.h" #include "pin_mux.h" #include "clock_config.h" #include "board.h" #include "app.h" #include "fsl_flexio_spi_edma.h" #include "board.h" //#include "app.h" #include "fsl_debug_console.h" void BOARD_InitHardware ( void ); #include "fsl_debug_console.h" #include "fsl_flexio.h" #include "fsl_edma.h" #include "fsl_inputmux.h" #include "fsl_common.h" /* ハードウェア常数定义 */ #define DEMO_FLEXIO_BASE FLEXIO0 #define DEMO_DMA_BASE DMA0 #define DEMO_DMA_CH      0 /* DMA チャネル 61 を使用 */ #define CHANNEL_COUNT    20 /* 20路并行引 */ #define BIT_DEPTH        24 /* 24位深度 */ #define SHIFTERS_USED    8 /* 次回 DMA 充填 8 个 シフター */ /* データ缓冲区：DMA パフォーマンスを強化する必要があります */ SDK_ALIGN ( uint32_t g_dac_buffer [ BIT_DEPTH ], 32 ); edma_handle_t g_edma_handle ; volatile bool g_transfer_done = false ; /* DMA 完了回调 */ void EDMA_Callback ( edma_handle_t * handle , void * param , bool transferDone , uint32_t tcds ) {    if ( transferDone )     {        /* FlexIO の最後の一組のデータを確保します */        while ( ! ( FLEXIO_GetShifterStatusFlags ( DEMO_FLEXIO_BASE ) & 0x01U ));        /* 立即关闭 DMA 请要求、生成仮想假触発を防止 */        FLEXIO_EnableShifterStatusDMA ( DEMO_FLEXIO_BASE , 1 << 0 , false );        g_transfer_done = true ;    } } void Init_FlexIO_DAC ( void ) {    flexio_config_t fxioConfig ;    flexio_shifter_config_t shConfig = { 0 };    flexio_timer_config_t timConfig = { 0 };    FLEXIO_GetDefaultConfig ( & fxioConfig );    FLEXIO_Init ( DEMO_FLEXIO_BASE 、 & fxioConfig );    FLEXIO_Reset ( DEMO_FLEXIO_BASE );    /* 配置 8 个 Shifter 并行出力 */    for ( uint8_t i = 0 ; i < SHIFTERS_USED ; i ++ )     {        shConfig.timerSelect​​   = 0 ;        shConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive ;​​        shConfig . pinConfig     = kFLEXIO_PinConfigOutput ;        shConfig.pinSelect​​     = 0 ; /* 引脚から D0 開始 */        shConfig . pinPolarity   = kFLEXIO_PinActiveHigh ;        shConfig.shifterMode​​   = kFLEXIO_ShifterModeTransmit ;        shConfig.inputSource​​   = kFLEXIO_ShifterInputFromPin ;        shConfig . shifterStop   = kFLEXIO_ShifterStopBitDisable ;        shConfig . shifterStart  = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable ;        shConfig 。平行幅= CHANNEL_COUNT - 1U ; /* 20路并行宽度 */        FLEXIO_SetShifterConfig ( DEMO_FLEXIO_BASE , i , & shConfig );    }    /* タイマー 0 を SCLK 時間源として設定 */    timConfig.triggerSelect​​   = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT ( 0 );    timConfig.triggerPolarity​​= kFLEXIO_TimerTriggerPolarityActiveLow ;    timConfig.triggerSource​​   = kFLEXIO_TimerTriggerSourceInternal ;    timConfig . pinConfig       = kFLEXIO_PinConfigOutput ;    timConfig.pinSelect​​       = 20 ; /* 時刻信号出力 D20 */    timConfig.timerMode​​       = kFLEXIO_TimerModeDual8BitBaudBit ;    timConfig.timerDisable​​    = kFLEXIO_TimerDisableOnTimerCompare ;    timConfig.timerEnable​​     = kFLEXIO_TimerEnableOnTriggerHigh ;    /* 8 位 = 16 边沿線 (15)、周波数分周波数 = 10 */    timConfig.timerCompare​​    = ( 15U << 8U ) | 10U ;    FLEXIO_SetTimerConfig ( DEMO_FLEXIO_BASE , 0 , & timConfig ); } void Init_DMA_DAC ( void ) {    edma_config_t edmaConfig ;    /* 修正後の MCXN947 InputMux 接続 */    /* 結果 kINPUTMUX_Flexio0Shift0ToDma0Ch61Ena 依然报错，       kINPUTMUX_Flexio0Request0ToDma0Ch61Ena */    INPUTMUX_Init (INPUTMUX0);    //INPUTMUX_EnableSignal(INPUTMUX0, kINPUTMUX_Flexio0Shift0ToDma0Ch61Ena, true);    INPUTMUX_EnableSignal (INPUTMUX0, kINPUTMUX_FlexIO0ShiftRegister0RequestToDma0Ch61Ena , true );    EDMA_GetDefaultConfig ( & edmaConfig );    EDMA_Init ( DEMO_DMA_BASE , & edmaConfig );    EDMA_CreateHandle ( & g_edma_handle , DEMO_DMA_BASE , DEMO_DMA_CH );    EDMA_SetCallback ( & g_edma_handle , EDMA_Callback , NULL ); } void DAC_Transmit ( void ) {    edma_transfer_config_t xferConfig ;    edma_minor_offset_config_t offsetConfig ;    g_transfer_done = false ;    /*       パラメータ修正説明： 1.bytesEachRequest = 32 (每次触発行搬运 8 个 Shifter、每个 4 字节) 2.transferBytes = 96 (总共 24 位データ、每位 4 字节、24 * 4 = 96)       このように 96 % 32 == 0、承認すれば通過できます。    */    EDMA_PrepareTransferConfig ( & xferConfig 、 ( void * )g_dac_buffer, /* srcAddr */                               4 , /* srcWidth: 4文字节 */                               4 、 /* srcOffset: 4 */ ( void * ) & ( DEMO_FLEXIO_BASE -> SHIFTBUF [ 0 ]), /* destAddr */                               4 , /* destWidth: 4文字节 */                               4 、 /* destOffset: 4 */                               32 、 /* bytesEachRequest: 32 */                               96 /* transferBytes: 96 (！！修正点) */                               );    /* 提交配置 */    EDMA_SubmitTransfer ( & g_edma_handle , & xferConfig );    /* 配置地址回帰：マイナーループ終了後、目的地址减去 32 字节回帰 SHIFTBUF[0] */    offsetConfig.enableSrcMinorOffset​​  = false ;    offsetConfig.enableDestMinorOffset = true ;​​    offsetConfig.minorOffset​​           = -32 ;​    EDMA_SetMinorOffsetConfig ( DEMO_DMA_BASE , DEMO_DMA_CH , & offsetConfig );    /* DMA と FlexIO の要求 */    EDMA_StartTransfer ( & g_edma_handle );    FLEXIO_EnableShifterStatusDMA ( DEMO_FLEXIO_BASE , 1 << 0 , true ); } int main ( void ) {    /* 基础ハードウェア初期化 (時間钟/引脚) */    BOARD_InitHardware ();    Init_FlexIO_DAC ();    Init_DMA_DAC ();    /* 例データ充填 */    for ( int i = 0 ; i < BIT_DEPTH ; i ++ ) g_dac_buffer [ i ] = 0xAAAAA ;    （ １ ）​     {        DAC_Transmit ();        /* 等待ち回调执行 */        while ( ! g_transfer_done );        /* 間隔 */        SDK_DelayAtLeastUs ( 1000 、 SystemCoreClock);    } }     程序卡死在 while(!g_transfer_done); 問題はここにあります 通信・制御(I3C |I2C |SPI |FlexCAN |イーサネット |FlexIO) Re: mcxn947 dma传输开启后没有进入回调 コールバックは実行されませんでした。 ここではどのチャネルをDMAに使用すべきでしょうか？チャネル61ではアサーションが満たされません。チャネル61は16を超えることはできません。 DMAチャネルが0に設定されている場合、DMAコールバックは一切実行されません。 Re: mcxn947 dma传输开启后没有进入回调 こんにちは、 @justdomyself 1) デバッグ用のブレークポイントを設定し、eDMA割り込み関数とコールバック関数が実行されているかどうかを確認します。 2) 使用されているeDMAチャネルを確認してください。 ＃定義する DEMO_DMA_CH      / * DMAチャネル61を使用 */ ここではチャネル0が使用されているようです。 INPUTMUX_EnableSignal(INPUTMUX0, kINPUTMUX_FlexIO0ShiftRegister0RequestToDma0Ch61Ena, true); ただし、コメントとこのコード行から判断すると、チャネル61を使用しているようです。 BR アリス

Doubt regarding iMX95 PMIC output based on SoM design i wanted to make a custom pcb based on iMX95 and i am using the iMX95 SoM schematic as the reference schematic. As per what i understood, the PF09 will be the master pmic and will be making all the voltages except the soc and arm core voltages, these core voltages are made by pf530x. My doubts are: 1.  In the ref schematic LDO3 of PF09 is also making the VDD_SoC voltage line, why is it done? 2. And it is shown it can only source upto 200mA, but SoC current requirement is more than that, and if we both PF09 and PF530x is making the same voltages then it is like shorting the power lines, in such case will the pin at PF09 sink the current and then cause issues? 3. Should I/Can I remove the  power output from Pf09 LDO and just use the other one, will it work? (give a clear suggestion, regarding "should i remove" or "can i remove") images are attached below for reference PF09 outputs PF530x used for VDD_SOC generation

MBD中的LIN到CAN 我正在使用NXP MBD模块集，并通过LIN接收帧模块从CANoe上的LIN从站获取反馈，然后尝试使用CAN发送模块将LIN反馈发布到CAN总线上。为此，我使用了数据解复用器，但出现了维度错误。我也无法使用ldf文件。我还尝试将数据存储在存储器中并从中读取，这没有报错，但我仍然无法发布数据。 Re: LIN to CAN in MBD 你好， 你使用的是哪个版本的MATLAB？你用的是什么工具箱？如果可以的话，能否尝试发送一段模型代码片段和收到的错误信息？ 此致， 索林·班奇拉

对于 S32G399，配置基于 DDR 的共享内存，以便 A 核心和 M 核心都能访问。 对于芯片 S32G399，配置基于 DDR 的共享内存，以便 A 核心和 M 核心都能访问。是否有任何实施方案和示例可供参考？ Re: For S32G399, configure DDR‑based shared memory to be accessed by both A‑Core and M‑Core. 你好， @zhijie 感谢你的帖子。 据我所知，似乎没有类似的正式演示/示例，你可能需要自己开发。 目前，M 内核和 A 内核之间的通信中，IPCF 由 NXP 配置，但默认情况下它是基于 SRAM 的。 BR 陈银 Re: For S32G399, configure DDR‑based shared memory to be accessed by both A‑Core and M‑Core. NXP社区内是否有开发人员完成过此类实现？非常感谢您提供相关文件或分享经验。

Cold/warm PowerUp Detection without MC_RGM DES/FES registers I have a S32K312 (with SCB FS26) software, which should detect a cold/warm powerup. Due to HW layouts, the DES /FES registers cannot be used. Therefore, a memory mapped variable in the standby ram is used, which contains a magic number in case of warm powerups and undefined values in case of cold powerups. To preserve the magic number, this memory area isn’t initialized during startup (otherwise the information would be lost). But a read access on this variable leads to a HardFault. What is the official nxp way to detect cold/hot powerups, if DES/FES cannot be used? What needs to be done to handle the hardfault in that way, that there is a safe return to the function, which reads the uninitialized variable, and continue code execution? Re: Cold/warm PowerUp Detection without MC_RGM DES/FES registers Hello, What is the official nxp way to detect cold/hot powerups, if DES/FES cannot be used? Official way is always DES/FES. I cannot imagine the situation where these are not available for analyzes. Can you explain why DES/FES cannot be used? Are the registers inaccessible, cleared before the application can read them, or are you trying to determine something different than the reset source? Best regards, Peter Re: Cold/warm PowerUp Detection without MC_RGM DES/FES registers Hello Peter, thank you for reply. A functional reset of the MCU asserts the RSTB signal, which triggers the circuit outside of the MCU. The circuit then holds the reset for a longer time. Unfortunately this causes a destructive reset and DES=1. That's why DES/FES cannot be used. Best regards, Christopher

Skywell BE11 ヘッドユニット ブリックモード こんにちは、 私はハンガリー出身のアッティラ ポトンディです。 ヘッドユニットを元の状態に戻すためのご協力をお願いしたいのですが。 私はドイツで中古車を購入しましたが、スカイウェル販売店に送った手紙には何の返事もありません。 車体番号はLMELBL1P4NRC03065です。 スカイウェル BE11 NXP i.MX8QXP プロセッサ 残念ながら、どちらの国の代理店もメーカーも質問に答えてくれないので、あなたにお願いします。 ターミナル経由でいくつかのAPKファイルを削除しようとしたところ、システムがクラッシュし、ターミナル経由でパスワードの入力を求められました。 よろしくお願い申し上げます。 アッティラ Re: Skywell BE11 Head unit Brick mode こんにちは、 特にヘッドユニットが既に不安定な状態なので、この件に関しては非常に注意した方が良いでしょう。i.MX8QXPベースのシステムでは、システムのAPKを削除したり端末からファイルを変更したりすると、Androidが簡単に起動できなくなることがあります。正確なSkywellのファームウェアやビルド、そして正しい復旧手順がなければ、端末のパスワードを推測したり、さらにパッケージを削除したりするのはおすすめしません。