IAR IDEで「致命的なエラー:CPUセッションへの接続に失敗しました。中止されました!」 - MIMXRT1170 デバッグにCMSIS-DAPリンクを使用し、CMSIS-DAPファームウェアを正常にロードします。 IAR Workbenchバージョン9.50.2を使用しています井手。 私はコードをうまくビルドできます。 しかし、IAR IDEからのコード 「致命的なエラー:CPUセッションへの接続に失敗しました!」  「ダウンロードとデバッグ」 コードを取得しました。 この問題の背後にある解決策を見つけることができませんでした。 回复: IAR IDEで「致命的なエラー:CPUセッションへの接続に失敗しました。中止されました!」 - MIMXRT1170 そして、なぜそれがcm7ファイルのみをコンパイルしてデバッグするのか、keilではcm4とcm7の両方をコンパイルするのか、あなたはどんな考えでも持っています。 回复: IAR IDEで「致命的なエラー:CPUセッションへの接続に失敗しました。中止されました!」 - MIMXRT1170 ハイギャビン、 CMSIS-DAPデバッガはEVKに搭載されています。 よろしくお願いいたします。 よろしくお願いいたします チャリンドゥ 回复: IAR IDEで「致命的なエラー:CPUセッションへの接続に失敗しました。中止されました!」 - MIMXRT1170 次に、J-Link Proデバッガーを使用し、その動作を確認します。 回复: IAR IDEで「致命的なエラー:CPUセッションへの接続に失敗しました。中止されました!」 - MIMXRT1170 ハイギャビン CM7 Hello Worldの例も試してみましたが、エラーは残っています。 よろしくお願いいたします チャリンドゥ

About the problem of imx8m plus u-boot adapting to multiple models of DDR At present, the uboot of imx8m plus needs to modify the two files lpddr4_timing.c and imx8mp_evk.h to support different sizes of DDR. In this way, 4 different uboot firmwares need to be compiled for the same device with 2GB, 4GB, 6GB and 8GB. We currently have 2 devices that support 2GB, 4GB, 6GB and 8GB, which means there are 8 uboot firmwares. As a result, it brings great trouble to our production line. It is easy to make mistakes when burning different uboots for devices with different sizes of DDR. The same is true for code maintenance. If one code is modified, 8 uboots need to be produced. So, is there any way to make uboot compatible with different sizes of DDR? Re: 关于imx8m plus u-boot适配多型号DDR的问题 Got it.Thank you. Re: 关于imx8m plus u-boot适配多型号DDR的问题 Hello, It is needed to compile different U-boot firmware for each DDR configuration. Best regards.

imx8m と u-boot が複数の DDR モデルに適応する際の問題について 現在、imx8m plusのubootは、異なるサイズのDDRをサポートするために、lpddr4_timing.cとimx8mp_evk.hという2つのファイルを修正する必要があります。そのため、2GB、4GB、6GB、8GBの同じデバイスに対して、4つの異なるubootファームウェアをコンパイルする必要があります。現在、2GB、4GB、6GB、8GBをサポートするデバイスが2つあり、ubootファームウェアは8つあることになります。その結果、生産ラインに大きな支障が生じています。異なるサイズのDDRを持つデバイス用に異なるubootを書き込む際に、間違いが起きやすいです。コードのメンテナンスについても同様で、1つのコードを修正するだけで、8つのubootを作成する必要があります。では、ubootを異なるサイズのDDRと互換性を持たせる方法はありますか？ Re: 关于imx8m plus u-boot适配多型号DDR的问题 Hello, DDR構成ごとに異なるU-bootファームウェアをコンパイルする必要があります。 よろしくお願いいたします。

PCF85263 RTC INTA flag issue We're trying to use the pcf85263 rtc in stop-watch mode to generate a alarm and level signal on INTA, the INTA flag gets set correctly but we're unable to clear the INTA flag. We're trying to clear the alarm by sending 0x00 to register 2Bh. Looking at the logic analyzer it gets ACKed and even set but INTA pin remains high. Our config is as following description(also shown in the rtc.py file): Config:         Read 0x28 register to verify correct rtcm mode TEST USE         Disable battery switch 0x26 register 0x10 data         Set INTA pin mode 0x27 register 0x10 data         Enable stop bit 0x2E register 0x01 data         Set rtcm mode and more to 0x28 register 0x97 data         Battery switch disable 0x29 register 0x90 data         Set minutes to 0x02 register 0x00 data         Set minutes alarm to 0x09 register 0x02 data         Enable minutes (SW control) 0x10 register 0x02 data         Clear stop bit 0x2E register                 After business logic:         Clear flag 0x2B register   Apart from not being able to get the INTA pin down everything seems to work. Question: Is there something missing or are we doing something wrong? Clearing the INTA flag should set the INTA pin low right? Thank you in advance Re: PCF85263 RTC INTA flag issue Hi, I am not sure about this line in your code: self.__write_data(bytearray([0x27]), bytearray([0x10])) Please try to modify it to: self.__write_data(bytearray([0x27]), bytearray([0x02])) BRs, Tomas

S32G3 DDR test successful, but startup failed! Hi nxp, We want to conduct DDR modification testing on the demo board. DDR test successful, but startup failed! Can you give me some advice? Thank you!  Hardware: S32G-VNP-RDB3 Software: S32 Design Studio for S32 Platform 3.5 arm-trusted-firmware  ---> bsp35.0-2.5 uboot  ------->bsp35.0-2020.04 DDR test successful: Startup failed: Re: S32G3 DDR test successful, but startup failed! Hi @carlos_o  After I set the clock to 1600MHz, problem solved! Thank you very much! Re: S32G3 DDR test successful, but startup failed! Hi @DRAVE, Which version of S32DS do you have installed? In case is lower than Version 3.5 Update 14 please upgrade to the newest version. In my view I can see the following options: My S32DS is Version 3.5 Update 14 The BSP35 already has the code for initialize properly the DDR of S32G-VNP-RDB3. Is there a reason why you want to generate this code?  Please help me answering the above question to have an understanding of your objective and help you to reach it.  Re: S32G3 DDR test successful, but startup failed! hi @carlos_o , Just to add, I am using a  S32G-VNP-RDB3 demo board.  The model of DDR should be MT53E1G32D2FW-046 AUT: B. Re: S32G3 DDR test successful, but startup failed! Hi @carlos_o , 1. My frequency configuration is the default configuration of the tool. All configurations are as follows: 2. All test results are as follows: Init: Diags: Operational : Shmoo: 3. I have replaced the SD card for testing. Using the original fig.s32 file, the system can start up. System startup failed after burning the regenerated fig.s32 file. After replacing the file with ATF: Re: S32G3 DDR test successful, but startup failed! Hi @DRAVE, You can review the following to discard some errors: 1. Ensure correct frequency configurations in the tool input parameters  2. Please review DQ/DBYTE swapping settings in the tool per schematics 3. Set PHY ODT as 60Ohm in the tool parameter and share behavior. NXP design recommend PHY ODT 60Ohm as default settings (Keep DRAM ODT 40Ohm as default) 4. If initialization is successful with DDR tool, then run shmoo tests (Read/Write) and share the eye plots Also, you can review AN13354: S32G2 Vehicle Network Processor Clock Configuration Guide Application note Please answer the next questions: With the same SD card image, did the board work fine before, but could not work now? Flash the same image to another SD card. Then check if the board can work or not. Share also the test result of Diags, Operational and Shmoo. Let me know if this information helps. 

Debug the Cortex-M33 on iMX93EVK I am trying to get a debug connection to the Cortex-M33 on the iMX93EVK board, using a SEGGER J-Link. I want to be able to debug while Linux is running on the A55.  I tried debugging the hello_world demo app on the M33 while the A55 is in U-Boot, following the instructions in AN14120. The U-Boot commands: fatload mmc 1:1 80000000 sdk20-app.bin cp.b 0x80000000 0x201e0000 0x10000 bootaux 0x1ffe0000 start the firmware and the output shows up on the serial port. But when I try to connect using the SEGGER JLinkGDBServerExe it fails to find the device. The log shows this: 02-00000000-00-00000041-004D: TB9DF640 005:451.096 ****************************************************** 02-00000000-00-00000041-004A: TB9DF640 005:451.097 J-Link script: i.MX93 Cortex-M33 core J-Link script 02-00000000-00-00000041-004D: TB9DF640 005:451.098 ****************************************************** 02-00000000-00-00000042-0034: TB9DF640 005:451.523 InitTarget() end - Took 426us 02-00000000-00-00000042-004D: TB9DF640 005:452.146 TotalIRLen = ?, IRPrint = 0x..000000000000000000000000 02-00000000-00-00000044-005B: TB9DF640 005:453.793 Failed to identify target. Resetting via Reset pin and trying again. It uses the iMX93 J-Link script but fails to connect to the target. Attach from VS Code (with MCUXpresso extension) also does not work. I get the same result when I try to debug while the A55 is in Linux (after changing the kernel DTS to disable lpuart5). Only when I put the BOOT_MODE to Cortex-M33 (Infinite Loop) can the J-Link find the device, and I can debug the demo app using VS Code. Why doesn't the J-Link detect the target with the A55 in U-Boot or Linux? Regards, Sander Re: Debug the Cortex-M33 on iMX93EVK The solution to this problem was to switch off the UART5 from JTAG on the board with the DIP switches SW101. Re: Debug the Cortex-M33 on iMX93EVK The kernel version we build is imx-6.6.36-2.1.0. I do not know which pre-build image, it came pre-installed when we bought the EVK. It prints "NXP i.MX Release Distro 6.6-scarthgap imx93evk ttyLP0" on startup, and "Linux version 6.6.36-lts-next-gd23d64eea511" on /proc/version Under which name would the UART5 show up in /dev? There is a /dev/ttyLP0, would the UART5 show up as /dev/ttyLP5 or some other number?  Re: Debug the Cortex-M33 on iMX93EVK HI @Sander-ET! What kernel version are you compiling in Yocto and what pre-build image are you using? You can corroborate if the UART5 is not working if the UART is not listed in the folder /dev/ of the iMX Re: Debug the Cortex-M33 on iMX93EVK For the Cortex-M33 we are using the MCUXpresso SDK from git (MCUX_2.16.100). We try to start the debugger from Visual Studio Code, using the MCUXpresso extension. We tried the right-click Attach and Debug, both fail to connect but reset the board. For the Cortex-A we build an image using imx-docker (MACHINE="imx93-11x11-lpddr4x-evk", DISTRO="fsl-imx-xwayland", IMAGES="imx-image-core"). We boot this from SD card. The device tree has been modified to disable lpuart5. Is there a way to verify from Linux that lpuart5 really is disabled? We also tried to debug booting the original (demo) image in eMMC with the A55 in U-Boot. We get no JTAG connection with this image either. The suggested change of the u-boot environment did not help. Regards, Sander Re: Debug the Cortex-M33 on iMX93EVK HI @Sander-ET! What BSP are you using? Do you tried to right-click the project in the MCUXpresso for VS Code and choose "Attach to debug the project"? Also you can update the environment of u-boot like we recommend in this post.  Best Regards! Chavira

imx93 DSI send command fail in some case HI experts:    I got a problem when intergrade a mipi panel to imx93 board ,  the log is:    "dw-mipi-dsi-imx 4ae10000.dsi:failed to write command FIFo"     and the function "mipi_dsi_device_transfer" return with error=-110.    After more research,  and found that not all commands fail, but some command with too much parameters will fail, for example: the driver send the following commands: it will fail at command : 0xB4 , 0xD3, 0xD5 , 0xD6.   If I don't send the commands failed, the panel can show picture , but the picture position is   offset,  and I have confirmed the board is ok wit DSI TO HDMI,  and the panel is ok with imx8mini.     Dose anyone has any suggestion ?     Best Regards . Linux Re: imx93 DSI send command fail in some case Hi Zhiming: Thanks. And finally I found that add more timeout or don't send command in LPM will fix the problem. Re: imx93 DSI send command fail in some case Hello, The DSI controller in i.MX93 is different from i.MX8MM.  Please refer Table 526. Error Cause and Recover  in i.MX93 RM. For pld_w_err, the controller can send such long packet at one time. Please check with your panel vendor to see if you can split these long cmd lists. Best Regards Zhiming

S32DS licence available 0 Hello, I have installed the product in a laptop, it generates one licence? Then trying to install it on a PC, using the same activation code, says no licences available. Fulfillment ID: 120609221 How do I fix it? Thanks. Cio Re: S32DS licence available 0 All good now, thanks. Re: S32DS licence available 0 Hi,  the number of available licenses has been increased.  Re: S32DS licence available 0 hi @jiri_kral  i'm also facing same issues help

关于imx8m plus u-boot适配多型号DDR的问题 目前imx8m plus的uboot对于支持不同大小的DDR，要修改lpddr4_timing.c和imx8mp_evk.h这两个文件，这样对应2GB、4GB、6GB和8GB的同款设备就要编译4个不同的uboot固件。我们目前有2款设备支持2GB、4GB、6GB和8GB，那就有8个uboot固件，结果给我们的产线带来很大的麻烦，对不同大小DDR的设备烧写不同uboot很容易搞错。还有就是代码的维护方面也一样，修改了一处代码，就要生产8个uboot。所以请问下有没有办法能够对uboot支持不同大小的DDR做兼容性？ Re: 关于imx8m plus u-boot适配多型号DDR的问题 Hello, 需要针对每个DDR配置编译不同的U-boot固件。 顺祝商祺！

MIMX8QM6AVUFFAB は NRND になりました MIMX8QM6AVUFFAB現在はNRNDですが、他のiMx8QMもNRNDにする予定はありますか? Re:MIMX8QM6AVUFFABはNRNDになりました 代替案が推奨されていると助かります。

imx8mnano evkのj1003コネクタでgiposにアクセスする こんにちは、imx8mnanoevkのj1003コネクタのEXP_IO9ピンに接続されたLEDを点滅させようとしています。 私は次のリンクhttps://variwiki.com/index.php?title=MX8M_GPIO でkernalデバイスツリーの設定に従っています。 imx8mn-pinfunc.h で gpio 定義 #define MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 を見つけ、iomuxc ノードで編集された arch/arm64/boot/dts/freescale/fsl-imx8mn-evk.dtsi で定義MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9を追加しました。これは、imx8mn evk の "yellow:status" デフォルト LED が "yellow1:status」と bitbake imx-image-multimedia を実行してから、imx8mnano evk で画像をフラッシュしました。次に、gpioinfoコマンドを確認しましたが、「yellow:status」が「yellow1:status」に変更されておらず、gpioset gpiochip1 9 = 0/1とgpioget gpiochip1 9を試しましたが、ステータスに変更はなく、常に「1」です。  上記のアプローチが正しいかどうか知りたいのですが?..いいえの場合は、J1003ピンヘッダーのGPIOにアクセスする方法を提案します Re:imx8mnanoevkのj1003コネクタのgiposへのアクセス おかげで、私はmetionedリンクを使用してそれを行うことになっていました Re:imx8mnanoevkのj1003コネクタのgiposへのアクセス こんにちはホルヘ、 投稿をありがとう、私はそれに従い、gpiosetコマンドでj1003のLEDを制御することができました。同じgpio(EXP_IO 09)のledを制御するレシピcコードを書いて手順を知りたいのですが。私はあなたが言及したリンクに記載されているcコードを追加し、bitbakeを実行しましたが、エラーが発生しました。CまたはPythonでLEDを制御する手順を提案できますか(Python libgbiodパッケージをインストールしようとしましたが、エラーで失敗しました)。

PN7160 interfacing with STM32F7 MCU in Card Emulation mode Hi Team, I am trying to interface PN7160 NFC evaluation kit with STM32F732 MCU in card emulation mode using I2C interface. I explored the web for resources (particularly for this HW interface) for any general purpose library but I unable to find it. Kindly provide any Command sequence document, demo code/ library or other documents if available. Please do the needful. Thanks Re: PN7160 interfacing with STM32F7 MCU in Card Emulation mode *Note: Refer AN13288 for HW connection information with dev kit. Re: PN7160 interfacing with STM32F7 MCU in Card Emulation mode Hi, It worked for iPhone for me with STM32 based host MCU, the mistake which I made is I connected Vbat to 3.3V but it needs to be connected with 5V. I done the same. Now the ported demo application worked for me. Note: Refer AN13288 for HW connection information. Thanks for Support! Re: PN7160 interfacing with STM32F7 MCU in Card Emulation mode Thank you for suggestion, I am able to port library code with my STM32 architecture successfully. I am detecting the emulated tag (ISO14443-4 Type A) and able to read the emulated tag from Android device, but I am unable detect the emulated tag to perform Read/Write operation using iPhone. Please provide the configuration and changes needs to be done for example project so that I can use PN7160 with iPhone in Card emulation mode. Thanks.  Re: PN7160 interfacing with STM32F7 MCU in Card Emulation mode Hi @Krishan_T_S  I would suggest you refer to AN13288. section 5.2 The present code example can be easily ported to any other target providing I²C or SPI master and GPIO capabilities. The only module requiring adaptation is the TML component (relates to how the target provides this support), others modules being platform agnostic. reference code is SW6705,  you can get it from PN7160 product page. Regards Daniel

PN7160 と STM32F7 MCU とのインターフェース (カード エミュレーション モード) こんにちはチーム、 PN7160 NFC評価キットとSTM32F732 MCUをI2Cインターフェースを使用してカードエミュレーションモードでインターフェースしようとしています。私は汎用ライブラリのリソース(特にこのHWインターフェース)をWebで探しましたが、見つけることができませんでした。 コマンドシーケンスドキュメント、デモコード/ライブラリ、または利用可能な場合はその他のドキュメントを提供してください。 必要なことをしてください。 ありがとうございます 日時:PN7160 STM32F7カードエミュレーションモードでのMCUとのインターフェース *注: 開発キットとの HW 接続情報については、AN13288 を参照してください。 日時:PN7160 STM32F7カードエミュレーションモードでのMCUとのインターフェース 提案をありがとう、私は私のSTM32アーキテクチャでライブラリコードをうまく移植することができます。 エミュレートされたタグ(ISO14443-4 Type A)を検出し、エミュレートされたタグをAndroidデバイスから読み取ることができますが、エミュレートされたタグを検出し、iPhoneでの読み取り/書き込み操作を行うことができません。カードエミュレーションモードでiPhoneでPN7160を使用できるように、プロジェクトの例で行う必要がある構成と変更を提供してください。 感謝。

S32K311 HSE_SEND応答しません FWインストールは、FWのisntallデモを使用して、インストール後に追加すると、FWのバージョンを確認でき、この証明書はFWのインストールが成功しました。 その後、freertosの新しいプロジェクトを作成し、S32K344 AES EncryptDecrypt exsampleをマージしますが、FWバージョンの読み取りをテストすると、MU受信が保留中になります。 以下の添付ファイルは私のFWです exsample freertos exsample、チェックしてください

Accessing gipos on j1003 connector on imx8mnano evk Hi, I am trying to blink an led connected to EXP_IO9 pin on j1003 connector on imx8mnano evk. I have followed kernal device tree configuration in the following linkhttps://variwiki.com/index.php?title=MX8M_GPIO . I have found gpio definition #define MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 in imx8mn-pinfunc.h and added the definition MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9  in the iomuxc node edited arch/arm64/boot/dts/freescale/fsl-imx8mn-evk.dtsi, for verifying whether the correct .dtsi file I have edited "yellow:status" default led on imx8mn evk to "yellow1:status" and done bitbake imx-image-multimedia then flashed the image in imx8mnano evk. Then checked the gpioinfo command but there "yellow:status" is not changed to "yellow1:status", tried gpioset gpiochip1 9=0/1 and gpioget gpiochip1 9, but there is no change in status its always '1'. I would like to know whether the above approach is correct ?..if no suggest the approach to access the gpio's on j1003 pin header Re: Accessing gipos on j1003 connector on imx8mnano evk Hello @JorgeCas ,  may ask you where you find this information "EXP_IO9 is on line 11" please? I don't find the relation between EXP_IO9 and (gpiochip5, line 11) Regards Re: Accessing gipos on j1003 connector on imx8mnano evk thanks, I was to do it using the metioned link Re: Accessing gipos on j1003 connector on imx8mnano evk Hello, You could try with os in python to use bash. Best regards. Re: Accessing gipos on j1003 connector on imx8mnano evk Hello Jorge, Thanks for the post, I followed it and able to control the led on j1003 with gpioset commands. I would like to know the procedure by writing a recipe c code to control led  for the same gpio(EXP_IO 09). I have added the c code mentioned in the link mentioned  by you and done bitbake, but getting errors. can you suggest the procedure to control led in c or python(tried to install python libgpiod package but failed with errors).  Re: Accessing gipos on j1003 connector on imx8mnano evk Hello,   You can use the GPIO on our demo image without modify the device tree.   The GPIO pins of RPI connector are connected to a I2C port expander on I2C3.   Using gpioinfo you can see it on gpiochip5:   EXP_IO9 is on line 11 and you need to use the next command:   gpioset -c gpiochip5 11=1 or gpioset -c gpiochip5 11=0   Also, this link could be helpful.   Best regards.  

S32G2 Linux bsp emmc boot Hi,nxp team: Recently I am learning how to start EMMC, referring to Johnli's article "S32G_EMMC_Application". I have some questions. If I use bsp29 and follow the steps in the manual, I can start emmc, but if I use other versions, such as bsp38, the same steps will not start emmc. Since I am not very familiar with the u-boot instructions, I don't know which instructions I need to change when switching bsp. Please help me, thank you.The following is the link to the article I referred to： https://community.nxp.com/t5/NXP-Designs-Knowledge-Base/S32G-eMMC-application-doc/tac-p/1989587#M812 S32G-VNP-RDB2  Re: S32G2 Linux bsp emmc boot hi，jiajun_cheng Thank you for your reply. You can refer to the S32G2_LinuxBSP_38.0_User_Manual.pdf document Chapter 4, refer to the  address. The different addresses that BSP29 and BSP38  into DDR are related to the Image itself. When BSP38 burn DDR through SD card, it is very likely that the low address space has been occupied, resulting in a conflict. Hope it can help you! BR Joey Re: S32G2 Linux bsp emmc boot Hi, @Joey_z : What I want to know is the address you marked in the red box. How do you confirm it. Is it written in that document? Please guide me. Thank you. Re: S32G2 Linux bsp emmc boot hi,jiajun_cheng Can you show more of your error messages? I tried this document, loading BSP38 to emmc, some need some attention, I marked it in the following figure, I hope it can help you. BR Joey

S32K311 HSE_SEND无响应 首先我使用FW isntall demo安装FW，安装后我可以检查FW版本，这证明FW安装成功。 之后，我创建了一个 freertos 新项目，然后合并了 S32K344 AES EncryptDecrypt 示例，但是当我测试读取 FW 版本时，它在 MU 接收待处理时被阻止。 以下附件是我的 FW 安装示例 freertos 示例，请检查

S32K311 HSE_SEND not response Frist I install FW by use the FW isntall demo ，add after install I can check the FW version , this Certificate that FW install sucess.  after that I creat a freertos new project then merge the S32K344 AES EncryptDecrypt exsample ,but when I test read FW vesion it's block at MU receive pending.  the bellow attachments is my FW install exsample the freertos  exsample, check check it Re: S32K311 HSE_SEND not response Hi  lukaszadrapa,    thanks a lot for you help ,after I change to non-cacheable RAM than the problem solved Re: S32K311 HSE_SEND not response I found the reason. I can see now that you use DTCM memory for your data including HSE descriptor and gHseFwVersion. But HSE cannot see DTCM at 0x2000_0000 - 0x2000_FFFF. This address range is visible only for core. Other bus masters must use Backdoor address: So, either force all data objects used for communication with HSE to normal non-cacheable RAM or use Backdoor addresses. The first option makes more sense.  Regards, Lukas Re: S32K311 HSE_SEND not response Hi lukaszadrapa,   thansk for you reply, the bellow picture show those register ,and FW isntall state. by the way I don't know whether in  startup_cm7.s the XRDC_CONFIG_ADDR and LF_CONFIG_ADDR all config to 0 will impact  Re: S32K311 HSE_SEND not response Hi @niugh0928  What is the state of HSE GPR register (at 0x4039_C028) and FSR and GSR registers in MU at that moment? Regards, Lukas

How to insert deatime in PWM by eTPU of MPC5554 Hello, I am looking for document which explains how to insert deadtime of PWM by eTPU of MPC5554. I did read some documents, like "PMSM Vector Control, Driven by eTPU on MPC5500",but all these documents use MC33937 to generate deadtime. So I want to ask how can I generate deadtime for PWM by setting  up eTPU without using any pre-driver to generate deadtime? Is there any demo for me to study? Thank you very much! Emily Re: How to insert deatime in PWM by eTPU of MPC5554 Thanks a lot! Re: How to insert deatime in PWM by eTPU of MPC5554 Dead time is a parameter of PWMMAC function. It is generated by eTPU module. Pay attention to AN2969 - Using the AC Motor Control PWM eTPU Functions

访问 imx8mnano evk 上 j1003 连接器上的 gipos 你好，我正在尝试让连接到 imx8mnano evk 上 j1003 连接器上的 EXP_IO9 引脚的 LED 闪烁。 我已按照以下链接中的内核设备树配置进行操作https://variwiki.com/index.php?title=MX8M_GPIO 。 我在 imx8mn-pinfunc.h 中找到了gpio 定义#define MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9，并在编辑的 arch/arm64/boot/dts/freescale/fsl-imx8mn-evk.dtsi 中的 iomuxc 节点中添加了定义 MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9，为了验证正确的 .dtsi 文件，我已将 imx8mn evk 上的“yellow:status”默认 led 编辑为“yellow1:status”，并完成了 bitbake imx-image-multimedia，然后在 imx8mnano evk 中闪烁了图像。然后检查了 gpioinfo 命令，但“yellow:status”没有更改为“yellow1:status”，尝试了 gpioset gpiochip1 9=0/1 和 gpioget gpiochip1 9，但状态没有变化，始终为“1”。 我想知道上述方法是否正确？如果没有，建议使用访问 j1003 引脚接头上的 gpio 的方法 回复：访问 imx8mnano evk 上 j1003 连接器上的 gipos 谢谢，我打算使用上述链接进行操作 回复：访问 imx8mnano evk 上 j1003 连接器上的 gipos 你好，Jorge， 感谢您的帖子，我按照它操作，并能够使用 gpioset 命令控制 j1003 上的 led。我想通过编写配方 c 代码来了解控制相同 gpio（EXP_IO 09）的 led 的过程。我已经添加了您提到的链接中提到的 c 代码并完成了 bitbake，但出现了错误。您能否建议用 c 或 python 控制 led 的程序（尝试安装 python libgpiod 包但失败并出现错误）。