CodeWarrior 2.1 and CodeWarrior 10.6 PE Driver PE Driver(multilink_universal_install_12.2 ) can use on CodeWarrior 2.1 IDE ,but  it can not use on the CodeWarrior 10.7, it must instatll 12.7. Is PE Driver can used on the both CodeWarrior 2.1 IDE and CodeWarrior 10.7 IDE? Re: CodeWarrior 2.1 and CodeWarrior 10.6 PE Driver Hi, Could you please help me to resolve this error. PFB is me driver details The USB indication led is turned on and it is blue color.  Still the software is not detecting the hardware. Re: CodeWarrior 2.1 and CodeWarrior 10.6 PE Driver Thank you! Re: CodeWarrior 2.1 and CodeWarrior 10.6 PE Driver IT is not found elf.file ,reload the elf file to the path Re: CodeWarrior 2.1 and CodeWarrior 10.6 PE Driver Hi  Thank you, I solved the PEmicro recognition problem using the method above, but now I'm encountering the "load fail" issue. when I clicked the "connect(Reset)"button ,the new problem was appeared as below. And how can I solve this problem ?(load aborted) Re: CodeWarrior 2.1 and CodeWarrior 10.6 PE Driver Thank you for your replying Re: CodeWarrior 2.1 and CodeWarrior 10.6 PE Driver Can you try to install P&E patch available here: https://www.pemicro.com/downloads/download_file.cfm?download_id=463 This should update the support for all compatible PEmicro interfaces into CW MPC55xx/56xx v2.10 Stan Re: CodeWarrior 2.1 and CodeWarrior 10.6 PE Driver Hi,Thank you for your replying. My window is Windows 11 64bit , My drive and PE type is as following figure   When debuging on  CodeWarrior 2.10 using multilink_universal_install _12.7. It is not ok, When debuging on  CodeWarrior 2.10 using multilink_universal_install _12.0. It is  ok, Re: CodeWarrior 2.1 and CodeWarrior 10.6 PE Driver Hi,  I've just installed Drivers 12_7 on my Windows 10 64bit machine and use it with CodeWarrior for MPC55xx/56xx v2.10 and PEmicro Multilink FX (black probe) rev.C PEmicro Multilink PowerPC Nexus (blue probe) rev. All configurations work as expected. Do you observe any issue on your side? If yes, can you attach the error screenshot? Hope it helps. Stan Re: CodeWarrior 2.1 and CodeWarrior 10.6 PE Driver Hello, @stanish could you comment here? Best regards, Peter

S32G3 bsp38 u-boot loads PFE firmware Hi, I am using BSP38 and have programmed the fip.s32-sdcard file to the eMMC. During the U-Boot boot process, I encountered a failure loading the PFE firmware, returning -1. According to the output of mtd list, the PFE firmware should be located at address 0x0000030a0000-0x000004000000. I used Flashtool to program the s32g_pfe_class.fw file to address 0x30a0000 and set the pfengfw variable in the environment. Despite these steps, the PFE firmware still fails to load. Could you provide guidance on the correct steps to ensure that U-Boot loads the PFE firmware properly? Thanks, XD => print pfengfw pfengfw=0x30a0000 => pfeng info Failed to get speed of XPCS for emac1_xpcs** No partition table - mmc 0 ** PFEng firmware file 'mmc@0:1:s32g_pfe_class.fw' loading failed: -1 PFE mode: enable emac0: sgmii emac1: sgmii emac2: rgmii fw: '0x30a0000' (from env) => Re: S32G3 bsp38 u-boot loads PFE firmware Hello, @XD  Thanks for the reply. I've checked the related document, but seems currently no related script found, from my opinion, you may directly use the partation table of pre-built full images, then copy the PFE firmware to correct place. Sorry for your inconvenience. BR Chenyin Re: S32G3 bsp38 u-boot loads PFE firmware Hi Chenyin, Thank you for your reply. Do you have the partition table or the script to generate the image for reference? Thanks, XD Re: S32G3 bsp38 u-boot loads PFE firmware Hello, @XD  Thanks for the post. Yes, the uboot loads the PFE firmware from the partition 1. Currently, from the BSP UM, only the full disk image that generated from Yocto build includes both FIP and PFE firmware. BR Chenyin Re: S32G3 bsp38 u-boot loads PFE firmware It appears that the eMMC lacks a partition, and U-Boot requires a FAT partition to load the firmware file. Is there a way to generate a file that includes both the FIP and PFE firmware? Alternatively, is there another method to enable U-Boot to locate the firmware file? Thanks, XD

IMX93はカーネルバージョン6.6.36ではRMIIモードでPHYを見つけることができませんid こんにちは、みんな： I.MX9352チップ、同一ボード、カーネルバージョン6.1.22使用、100Mbpsイーサネットポートは正常ですが、カーネルバージョン6.6.36にアップグレード後、デバイスツリー構成は6.1.22と一致していますが、PHYスキャンができません。ご助力ください。 Re: IMX93 はカーネルバージョン 6.6.36 では RMII モードで PHY を検出できませんid ファームウェアはmx93a1-ahab-container.imgを使用しています。チップはA1だと思います。

文档_OTA_安全启动_88MW320 没有文档，只有示例。请帮我找到所需的文件 回复：Documentation_OTA_Secure-Boot_88MW320 你好， 请提供一些解释工作流程的文档，或者任何通用的secureboot.c，secureboot.h 和 boot.c 和 boot.h文件对我来说很有用。 此外，如果有文档解释 MQTT 和 HTTP 流程，那将会非常有帮助。@DanielRuvalcaba 回复：Documentation_OTA_Secure-Boot_88MW320 你好， 那么引导加载程序呢？是否有特定的 boot.c 文件？和 boot.h 或 secureboot.c 和 secureboot.h 此外，除了 SDK 包中的文档之外，还有其他可用的东西吗？我需要一些用于 HTTP、MQTT 的应用程序开发。 回复：Documentation_OTA_Secure-Boot_88MW320 您好，我正在使用适用于RDMW320-R0 (88MW320_xx_xxxx) 的 SDK 版本 2.9.13，该版本是从 MCUXpresso SDK 构建器下载的 问题是，当我下载与 SDK 一起生成的文档时，我没有获得有关 OTA、自定义引导加载程序开发、安全启动、HTTP/HTTPS、MQTT、MbedTLS 和类似 API 的应用程序说明或其他内容的详细信息。

IMX93 cannot find phy in RMII mode under 6.6.36 kernel version id Hello everyone: I.MX9352 chip, on the same board, using 6.1.22 kernel version, 100M Ethernet port is normal, but after upgrading to 6.6.36 kernel version, the device tree configuration is consistent with 6.1.22, but the phy cannot be scanned. Please help. Re: IMX93 cannot find phy in RMII mode under 6.6.36 kernel version id I use the mx93a1-ahab-container.img firmware. I think my chip should be A1. Re: IMX93在6.6.36内核版本下RMII模式下找不到phy id Hi @yangx! IF your board works with kernel 6.1.22 it is normal that should not work on kernel 6.1.36 and latest kernels. The kernel 6.1.22 and 6.1.22 works only on iMX93 with silicon version A0 the silicon version A1 works with kernel 6.1.36 an latest kernel versions. Please confirm that you have A1 silicon version version to use the latest kernel versions if not, you have to use the 6.1.22 kernel version . Best Regards! Chavira

Documentation_OTA_Secure-Boot_88MW320 ドキュメントはなく、例だけです。必要な書類を見つけるのを手伝ってください 日時:Documentation_OTA_Secure-Boot_88MW320 こんにちは ワークフローを説明するドキュメント、または一般的なsecureboot.cで助けてください。secureboot.h と boot.c と boot.hファイルは私のために働くでしょう。 さらに、MQTTとHTTPフローを説明するドキュメントがあれば、それは非常に役立ちます。@DanielRuvalcaba  日時:Documentation_OTA_Secure-Boot_88MW320 こんにちは ブートローダーはどうですか?特定のboot.cはありますかおよび boot.h または secureboot.c と secureboot.h また、そのSDKバンドルのドキュメント以外に、利用可能なものはありますか?HTTP、アプリケーション開発用のMQTTが必要です。 日時:Documentation_OTA_Secure-Boot_88MW320 こんにちは、MCUXpresso SDKビルダーからダウンロードしたRDMW320-R0(88MW320_xx_xxxx)用のSDKバージョン2.9.13を使用しています 問題は、SDKと一緒に生成されたドキュメントをダウンロードすると、OTA、カスタムブートローダー開発、セキュアブート、HTTP / HTTPS、MQTT、MbedTLSおよび同様のAPIの詳細なアプリケーションノートやその他のものを取得しないことです。

Documentation_OTA_Secure-Boot_88MW320 There are no documents, only examples. Please help me find the required documents Re: Documentation_OTA_Secure-Boot_88MW320 Hi, I will answer you in the internal case. Regards, Daniel. Re: Documentation_OTA_Secure-Boot_88MW320 Hello,  Please help with some document that explains the workflows, or any general secureboot.c, secureboot.h and boot.c and boot.h files would work for me.  Additionally if there would be documents explaining the MQTT and HTTP flow it will be really helpful.  @DanielRuvalcaba  Re: Documentation_OTA_Secure-Boot_88MW320 Hello, What about bootloaders? is there a specific boot.c and boot.h or secureboot.c and secureboot.h Also, apart from the documents in that SDK bundle, is there anything else that is available? I need something for HTTP, MQTT for application development. Re: Documentation_OTA_Secure-Boot_88MW320 Hi, Unfortunately, all the documentation regarding MCUXpresso SDK is the one available in the docs directory of the SDK bundle. We don’t have a document with specific instructions for secure boot using MCUXpresso SDK. Regards, Daniel. Re: Documentation_OTA_Secure-Boot_88MW320 Hello I am using SDK version 2.9.13 for RDMW320-R0 (88MW320_xx_xxxx) which was downloaded from MCUXpresso SDK builder The Issue is when I download the documentation generated along with the SDK, I don't getApplication notes or other stuff for OTA, Custom Bootloader Development, Secure Boot, HTTP/HTTPS, MQTT, MbedTLS and similar API's in detail.  Re: Documentation_OTA_Secure-Boot_88MW320 Hi, What SDK are you using? Regards, Daniel.

can/canfd on GLDBOX Hello,         I want to use can/canfd on GLDBOX, now the GLDBOX software is as default, Linux on A core, and M core is not used.  I need some guide:       1、Dose CAN/CANFD hardware resource designed for A core or M core or both?      2、How to control CAN/CANFD from A core?      3、Do I must install LLCE firmware before I use CAN/CANFD? Re: can/canfd on GLDBOX Hi, @yangjinzhuang  Thanks for your post. The CAN peripherals could be used by both A&M cores. You may simple operation the corresponding interface under Linux according to the chapter12&13 BSPUM If you are willing to use the LLCE-CAN interface, then LLCE firmware is a must. BR Chenyin

About the S32k142 timer Capture initializer crash When I use s32k142, I encounter the abnormal phenomenon of timer capture, hope someone can help to see the reason, thank you here. Let me describe the problem first. I first explain the code functions: 1, using timer 0 as PWM output 2, using timer 1 as input capture 3, using timer 2 as timing count, 4 using ADC0 ADC1 channel for ADC acquisition When I initialized the functions of each module in main, all the functions were running normally, as shown in the configuration figure below. But when I wrap all the initialization into a function and input a PWM signal to any of the capture pins, the running program crashes. If I block the timer capture configuration, the program works. What is the cause of this, why the timer capture configuration function into its own wrapped function will crash phenomenon.I have put the source code above, I hope it can be solved, thank you. Re: About the S32k142 timer Capture initializer crash Thank you very much for your reply，BR, Daniel. After I changed it to a global variable, it worked fine. Thank you for helping me solve the problem. Re: About the S32k142 timer Capture initializer crash Hi @Lw2, Can you test it with these structures being global not local? Thank you, BR, Daniel

Target error from Commit Flash write: Ep(04). 我的板子型号是MIMXRT685-EVK，我下载的SDK是SDK_2_16_000_EVK-MIMXRT685.zip。 步骤：build -> debug 提示如下： MCUXpresso IDE RedlinkMulti Driver v11.10 (Jul 2 2024 19:33:51 - crt_emu_cm_redlink build 741) Found chip XML file in C:/Users/carson.yu/Documents/MCUXpressoIDE_11.10.0_3148/workspace/evkmimxrt685_sctimer_pwm_with_dutycyle_change/Debug\MIMXRT685S.xml Reconnected to existing LinkServer process. Probe Firmware: LPC-LINK2 CMSIS-DAP V5.460 (NXP Semiconductors) Serial Number: DSA3CQMQ VID:PID: 1FC9:0090 USB Path: \\?\hid#vid_1fc9&pid_0090&mi_00#8&773e416&0&0000#{4d1e55b2-f16f-11cf-88cb-001111000030} Using memory from core 0 after searching for a good core processor is in secure mode debug interface type = CoreSight DP (DAP DP ID 6BA02477) over SWD TAP 0 processor type = Cortex-M33 (CPU ID 00000D21) on DAP AP 0 number of h/w breakpoints = 8 number of flash patches = 0 number of h/w watchpoints = 4 Probe(0): Connected&Reset. DpID: 6BA02477. CpuID: 00000D21. Info: Debug protocol: SWD. RTCK: Disabled. Vector catch: Disabled. Content of CoreSight Debug ROM(s): RBASE E00FE000: CID B105100D PID 0000095000 ROM (type 0x1) ROM 1 E00FF000: CID B105100D PID 04000BB4C9 ROM (type 0x1) ROM 2 E000E000: CID B105900D PID 04000BBD21 CSt ARM ARMv8-M type 0x0 Misc - Undefined ROM 2 E0001000: CID B105900D PID 04000BBD21 CSt ARM DWTv2 type 0x0 Misc - Undefined ROM 2 E0002000: CID B105900D PID 04000BBD21 CSt ARM FPBv2 type 0x0 Misc - Undefined ROM 2 E0000000: CID B105900D PID 04000BBD21 CSt ARM ITMv2 type 0x43 Trace Source - Bus ROM 2 E0041000: CID B105900D PID 04002BBD21 CSt ARM ETMv4.0 type 0x13 Trace Source - Core ROM 2 E0042000: CID B105900D PID 04000BBD21 CSt ARM CTIv2 type 0x14 Debug Control - Trigger, e.g. ECT ROM 1 E0040000: CID B105900D PID 04000BBD21 CSt type 0x11 Trace Sink - TPIU NXP: MIMXRT685S DAP stride is 1024 bytes (256 words) Inspected v.2 External Flash Device on SPI using SFDP JEDEC ID MIMXRT600_FlexSPI_B_MXIC_OPI.cfx Image 'MIMXRT600_FlexSPI_B_MXIC_OPI Jul 2 2024 18:29:23' Opening flash driver MIMXRT600_FlexSPI_B_MXIC_OPI.cfx VECTRESET requested, but not supported on ARMv8-M CPUs. Using SOFTRESET instead. Using SOFT reset to run the flash driver Flash variant 'JEDEC_FlexSPI_Device' detected (64MB = 1024*64K at 0x8000000) Closing flash driver MIMXRT600_FlexSPI_B_MXIC_OPI.cfx Connected: was_reset=true. was_stopped=false Awaiting telnet connection to port 3330 ... GDB nonstop mode enabled Opening flash driver MIMXRT600_FlexSPI_B_MXIC_OPI.cfx (already resident) VECTRESET requested, but not supported on ARMv8-M CPUs. Using SOFTRESET instead. Using SOFT reset to run the flash driver Flash variant 'JEDEC_FlexSPI_Device' detected (64MB = 1024*64K at 0x8000000) Writing 35604 bytes to address 0x08000000 in Flash Sectors written: 0, unchanged: 1, total: 1 Erased/Wrote sector 0-0 with 35604 bytes in 41msec Closing flash driver MIMXRT600_FlexSPI_B_MXIC_OPI.cfx Flash Write Done Flash Program Summary: 35604 bytes in 0.04 seconds (848.04 KB/sec) Starting execution using system reset and halt target with a stall address Retask read watchpoint 1 at 0x50002034 to use for boot ROM stall processor is in non-secure mode state - running or following reset request - re-read of state failed - rc Nn(05). Wire ACK Fault in DAP access state - running or following reset request - re-read of state failed - rc Nn(05). Wire ACK Fault in DAP access Warning - processor did not halt - gave up waiting flash - system reset failed - Ep(04). Cannot halt processor. Target error from Commit Flash write: Ep(04). Cannot halt processor. GDB stub (D:\nxp\LinkServer_1.6.133\binaries\crt_emu_cm_redlink) terminating - GDB protocol problem: Pipe has been closed by GDB. state - running or following reset request - re-read of state failed - rc Nn(05). Wire ACK Fault in DAP access 执行过 mass erase, 没什么用，跪求助跪求指教

Using ultralytics library on i.mx8M plus and i.mx8QuadMax for Yolov8 Ultralytics library requires opencv-python version >=4.6.0. can these two board's linux image support ultralytics library for yolov8 with opencv-python version 4.6.0? i.MX 8 Family | i.MX 8QuadMax (8QM) | 8QuadPlus i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Re: Using ultralytics library on i.mx8M plus and i.mx8QuadMax for Yolov8 Hi The latest BSP(L6.6.23) support OpenCV  4.9.0 Best Regards Zhiming

MIMXRT1170-EVKB 多核示例问题... 这是我第一次使用低级（非 Linux）多核设备，所以这可能是一个愚蠢的问题...... 我正在浏览“ MIMXRT1170-EVKB 的 MCUXpresso SDK 入门指南”（修订版）的第 6.4 和 6.5 节。0 — 2022 年 12 月 31 日），指的是 SDKTOP/boards/evkbmimxrt1170/multicore_examples/hello_world。我正在使用 SDK-2-16-100_MIMXRT1170-EVKB。我还有一个 JLink 编程器，连接到 EVKB 上的 20 针接头。 我第一次就能够构建/加载/运行 cm4/cm7 应用程序，但我没有完全遵循说明，因为它们对我来说没有意义（我必须为两个核心运行 gdb/load）。 第 6.4 节说要“构建”每个应用程序。这很好；但是第 6.5 节说：“ ...主核心调试器负责将主核心和辅助核心应用程序刷入 SoC 闪存... ”。对吗？我发现我必须对每个核心执行“加载”操作（使用 gdb）才能使一切正常工作。 此外，我尝试对 CM4 代码进行微小更改，但它似乎不是编程。gdb 的“加载”是否也会在编程之前清除所有内容？ 任何想法都将受到赞赏。 谢谢！ 回复：MIMXRT1170-EVKB 多核示例问题…… 好的，我想我现在明白了…… @Pavel_Hernandez ，pdf 非常有用，但是线程只是一组指令，告诉您在 IDE 中要按哪些按钮。如果试图真正理解事物，那就没什么用了。 我现在看到 CM4 的图像实际上作为名为“.core1_code”的部分合并到 CM7 的图像中。CM7 的构建依赖于之前构建的 CM4 图像，因此 CM7 的构建步骤之一是将 CM4 图像合并到 CM7 的内存映射中。这解释了为什么在使用 cm4 的 gdb 中执行“加载”时，它没有被推送到实际的 SPI 闪存空间。我不太喜欢这样做，但没关系。至少我现在明白了。 非常感谢，帮助很大！ 回复：MIMXRT1170-EVKB 多核示例问题…… 你好，我叫 Pavel，我会支持你的案例，我发现这个应用笔记可以帮助你更多地了解双核过程，请参阅第 2.1.2 章详细的启动流程。 有一些类似的论点，也许有助于理解。 “ ...主核心调试器负责将主核心和辅助核心应用程序刷入 SoC 闪存... ” i.MX RT1170 双核应用 也许这个其他线程可以帮助您在 IDE 上测试它。 如何使用 JLINK 调试 RT1170 双核 - NXP 社区 此致， 帕维尔 回复：MIMXRT1170-EVKB 多核示例问题…… 好吧，我不想声称这解决了这个问题，但我确实设法让两个核心都执行我的代码...... 我怀疑 gdb 如何告诉 JLINK 写入闪存，因此我没有使用连接到 jlink gdb 服务器的 gdb，而是创建了一个简单的 jlink 脚本来手动加载每个部分（见下文）。为此，我需要从 .elf 文件中提取每个可加载部分文件转换成自己的二进制文件。 对于创建的每个文件，我都可以运行此脚本： eoe 1 设备=MIMXRT1176DVMAA_cm7 速度 4000 si SWD r h 加载箱 elfsect_.flash_config.bin,0x30000400 加载箱 elfsect_.ivt.bin,0x30001000 加载箱 elfsect_.core1_code.bin,0x33fc0000 加载箱 elfsect_.interrupts.bin,0x30002000 加载箱 elfsect_.text.bin,0x30002400 加载箱 elfsect_.ARM.bin,0x30008d00 加载箱 elfsect_.init_array.bin,0x30008d08 加载箱 elfsect_.fini_array.bin,0x30008d0c 加载箱 elfsect_.data.bin,0x30008d10 去 出口 加载 CM7 一切正常。看起来，虽然 jlink 服务器表示它已验证下载，但验证失败了。 有人（NXP 支持）可以解释一下吗？ 回复：MIMXRT1170-EVKB 多核示例问题…… 更多信息... 我刚刚注意到，在 gdb 中运行“load”后，我的 JLinkGDBServerCLExe 窗口显示以下错误...... 错误：准备目标时超时，RAMCode 没有及时响应！ 无法执行 RAMCode-sidedPrepare() 确定闪存信息时出错（Bank @ 0x30000000）

We can measure RX signals from PHY but not TX signals coming from RT1176. Hello everyone, We are developing a new ethernet application with NXP i.MX RT1176 and TI DP83826E, but we are facing a connection problem that we are unable to establish ethernet communication. We are using DP83826 in basic mode and interfacing through RMII. The link is stablished and we are able to see RX signals from PHY while we are pinging from a computer connected to the board. But we are unable to exchange messages between the board and the computer.   I would really appreciate it if you could help me with some suggestions. i.MXRT Re: We can measure RX signals from PHY but not TX signals coming from RT1176. Hello @Habib_MS,  Thanks a lot for your message! We found the problem thanks to your app note recommendation, it was a problem with "ref_clock" pin. We changed "software input on" in MCUExpresso to "enabled" and ethernet worked well. Re: We can measure RX signals from PHY but not TX signals coming from RT1176. Hello @mdribeiro, In order to support you better, can you provide me the next information? - Are you currently using an SDK example, if the answer is yes, can you share me the name and your SDK version? - Which software stack was used for make ping in your board? - " But we are unable to exchange messages between the board and the computer", can you provide me more context about this comment, for example the PHY does not emit a signal, or it is emitting a signal, but the computer cannot interpret the information, etc? Also, I highly recommend see this app note in order to obtain more information about Ethernet Capabilities and PHY Connection of the RT1xxx series. BR Habib

MIMXRT1170-EVKB multicore example question... This is my first bit of experience with a low-level (not Linux) multicore device, so this may be a stupid question... I'm walking through sections 6.4 and 6.5 of  "Getting Started with MCUXpresso SDK for MIMXRT1170-EVKB" (Rev. 0 — 31 December 2022), which refers to SDKTOP/boards/evkbmimxrt1170/multicore_examples/hello_world.  I'm working with SDK-2-16-100_MIMXRT1170-EVKB. I also have a JLink programmer attached to the 20-pin header on the EVKB. I was able to build/load/run the cm4/cm7 applications the first time, but I didn't quite follow the instructions cause they don't make sense to me (I had to run gdb/load for both cores). Section 6.4 says to "build" each of the applications.  That's fine; but section 6.5 says: "..The primary core debugger handles flashing of both the primary and the auxiliary core applications into the SoC flash memory...".  Is that correct? I found that I had to execute the "load" operation (using gdb) for each of the cores to get anything to work. In addition, I tried to make a minor change to the CM4 code and it doesn't seem to be programming.  Does gdb's "load" also erase everything prior to programming? Any thoughts here would be appreciated. Thanks Re: MIMXRT1170-EVKB multicore example question... Ok, I think I get it now... @Pavel_Hernandez , the pdf was quite useful, but the thread is just a set of instructions that tell you what buttons to push in the IDE.  Not much good if trying to really understand things. I see now that the CM4's image is actually incorporated into the CM7's image as a section called ".core1_code".  The CM7's build depends on the CM4 image being built prior, so one of the CM7's build steps is to incorporate the CM4 image into the memory map of the CM7.  That explains why when doing a "load" when in gdb with the cm4, it was not being pushed to actual SPI flash space.  I don't really like the way this is done, but that's ok.  At least I understand it now. Thanks much, big help! Re: MIMXRT1170-EVKB multicore example question... Hello, my name is Pavel, and I will be supporting your case, I found this app notes where this could help you to understand more about the dual core process, please see the chapter 2.1.2 Detailed Boot flow. There is some similar argument, maybe could help to understand. "..The primary core debugger handles flashing of both the primary and the auxiliary core applications into the SoC flash memory..." i.MX RT1170 Dual Core Application Maybe this other thread could help you to test it on the IDE. How to use JLINK to debug RT1170 dual core - NXP Community Best regards, Pavel Re: MIMXRT1170-EVKB multicore example question... Well I don't want to claim that this fixed the problem, but I did manage to get both cores to execute my code... I was/am suspicious of how gdb tells JLINK to write to flash, so instead of using gdb hooked to the jlink gdb server, I just created a simple jlink script that would load each of the sections manually (see below).  To do that I needed to extract each of the loadable sections from the .elf file into their own binary file.  With each of the files created I was able to run this script: eoe 1 device=MIMXRT1176DVMAA_cm7 speed 4000 si SWD r h loadbin elfsect_.flash_config.bin,0x30000400 loadbin elfsect_.ivt.bin,0x30001000 loadbin elfsect_.core1_code.bin,0x33fc0000 loadbin elfsect_.interrupts.bin,0x30002000 loadbin elfsect_.text.bin,0x30002400 loadbin elfsect_.ARM.bin,0x30008d00 loadbin elfsect_.init_array.bin,0x30008d08 loadbin elfsect_.fini_array.bin,0x30008d0c loadbin elfsect_.data.bin,0x30008d10 go exit to load the CM7 and things worked.  It appears that while the jlink server was saying that it verified the download, the verification was failing. Can someone (NXP support) explain this? Re: MIMXRT1170-EVKB multicore example question... More information... I just noticed that my JLinkGDBServerCLExe window shows the following errors after I run "load" in gdb... ERROR: Timeout while preparing target, RAMCode did not respond in time! Failed to perform RAMCode-sided Prepare() Error while determining flash info (Bank @ 0x30000000)

MIMXRT1170-EVKBマルチコアの例の質問... これは、低レベルの(Linuxではない)マルチコアデバイスでの私の最初の経験なので、これは愚かな質問かもしれません... 「Getting Started with MCUXpresso SDK for MIMXRT1170-EVKB」のセクション 6.4 と 6.5 (Rev.0 — 31 December 2022)、これはSDKTOP/boards/evkbmimxrt1170/multicore_examples/hello_worldを指します。私はSDK-2-16-100_MIMXRT1170-EVKBを使用しています。また、EVKBの20ピンヘッダーにJLinkプログラマーを取り付けています。 私は初めてcm4 / cm7アプリケーションをビルド/ロード/実行することができましたが、指示が私には意味をなさないため、指示に完全には従わなかった(両方のコアでgdb / loadを実行する必要がありました)。 セクション 6.4 では、各アプリケーションを "ビルド" すると述べています。いいです;しかし、セクション6.5には次のように書かれています。プライマリ コア デバッガーは、プライマリ コア アプリケーションと補助コア アプリケーションの両方の SoC フラッシュ メモリへのフラッシュ処理を処理します。".それでよろしいですか。私は、何かを動作させるために、各コアに対して「ロード」操作(gdbを使用)を実行する必要があることがわかりました。 また、CM4のコードにマイナーチェンジをしてみましたが、プログラミングにはなっていないようです。gdbの "load"もプログラミング前にすべてを消去しますか? ここでのご意見はいただければ幸いです。 ありがとうございます Re:MIMXRT1170-EVKBマルチコアの例の質問... さて、今はわかったと思います... @Pavel_Hernandez、PDFは非常に便利でしたが、スレッドはIDEで押すべきボタンを指示する一連の命令にすぎません。物事を本当に理解しようとすると、あまり良くありません。 CM4の画像は、実際には「.core1_code」と呼ばれるセクションとしてCM7の画像に組み込まれていることがわかりました。CM7 のビルドは、以前にビルドされた CM4 イメージに依存するため、CM7 のビルド手順の 1 つは、CM4 イメージを CM7 のメモリ マップに組み込むことです。これは、cm4を使用してgdbで「ロード」を行うときに、実際のSPIフラッシュスペースにプッシュされていなかった理由を説明しています。私はこれが行われる方法があまり好きではありませんが、それは問題ありません。少なくとも今は理解しています。 どうもありがとう、大きな助け! Re:MIMXRT1170-EVKBマルチコアの例の質問... こんにちは、私の名前はPavelです、そして私はあなたのケースをサポートします、私はこれがデュアルコアプロセスについての詳細を理解するのに役立つことができるこのアプリのノートを見つけました、章2.1.2を参照してください詳細なブートフロー。 似たような議論がいくつかあり、理解するのに役立つかもしれません。 "..プライマリ コア デバッガーは、プライマリ コア アプリケーションと補助コア アプリケーションの両方の SoC フラッシュ メモリへのフラッシュ処理を処理します。" i.MX RT1170 デュアルコアアプリケーション たぶん、この他のスレッドはあなたがIDEでそれをテストするのを助けるかもしれません。 JLINKを使用してRT1170デュアルコアをデバッグする方法 - NXP Community よろしくお願いいたします パベル Re:MIMXRT1170-EVKBマルチコアの例の質問... まあ、これで問題が解決したとは言いたくありませんが、両方のコアでコードを実行することができました... 私はgdbがJLINKにフラッシュに書き込むように指示する方法に疑問を持っていたので、jlink gdbサーバーにフックされたgdbを使用する代わりに、各セクションを手動でロードする単純なjlinkスクリプトを作成しました（下記参照)。そのためには、 .elf から読み込み可能な各セクションを抽出する必要がありましたファイルを独自のバイナリファイルに入れます。 作成された各ファイルで、次のスクリプトを実行することができました。 EOEの1 デバイス=MIMXRT1176DVMAA_cm7 スピード4000 si SWDの r h ロードビン elfsect_.flash_config.bin,0x30000400 ロードビン elfsect_.ivt.bin,0x30001000 ロードビン elfsect_.core1_code.bin,0x33fc0000 ロードビン elfsect_.interrupts.bin,0x30002000 ロードビン elfsect_.text.bin,0x30002400 loadbin elfsect_。ARM.bin,0x30008d00 ロードビン elfsect_.init_array.bin,0x30008d08 ロードビン elfsect_.fini_array.bin,0x30008d0c ロードビン elfsect_.data.bin,0x30008d10 行く 出口 CM7をロードすると、うまくいきました。jlinkサーバーはダウンロードを確認したと言っていましたが、検証は失敗していたようです。 誰かが(NXPサポート)これを説明できますか? Re:MIMXRT1170-EVKBマルチコアの例の質問... 詳細情報... gdbで「load」を実行した後、JLinkGDBServerCLExeウィンドウに次のエラーが表示されることに気づきました... エラー:ターゲットの準備中にタイムアウトしました。RAMCodeは時間内に応答しませんでした。 RAMCode 側の Prepare() を実行できませんでした フラッシュ情報の決定中にエラーが発生しました (Bank @ 0x30000000)

i.MX RT1176 OCRAM performance questions Hi, I have some questions regarding i.MX RT1176 OCRAM performance: Is the OCRAM allocated from FlexRAM faster than OCRAM1 and OCRAM2? Is there a performance penalty if the M7 core accesses OCRAM1, and M4 accesses OCRAM2 simultaneously? Is there a performance penalty if both the M7 and M4 cores access OCRAM1 (or OCRAM2) simultaneously? Is there a difference in performance if the M4 accesses OCRAM allocated from FlexRAM rather than OCRAM1 or OCRAM2? Best, Kim Re: i.MX RT1176 OCRAM performance questions Thanks Omar, you confirmed my expectation. Best, Kim Re: i.MX RT1176 OCRAM performance questions 1. No. 2. Yes, both ocram access the same AXI bus so wait cycles are expected when accessed by multiple sources. 3. Yes, as they are accessed with the same AXI bus. 4. No To minimize the penalty it is suggested to cache the OCRAM to achieve better performance. Best regards, Omar

[FP: id verify fail] in codewarrior Studio Hi, I am trying to flash the uboot bin NOR flash in ls1046a and I am getting error like [FP: id verify fail] when using dump/verify/erase in codewarrior and none of the field is working. could you please help us to fix, Is this software/liscence issue but still it should work for 15 days since it is a trail version. Please help us. Thanks, Gopi Krishna M Lantronix Re: [FP: id verify fail] in codewarrior Studio Hello, Please share the process you followed and some screenshots of the issue.

iw611/iw612 and LE audio Dear NXP support, according iw611/iw612 Release Notes for Linux (RN00104) The firmware supports Bluetooth LE audio Does this mean that LC3 codec is supported too ? Thanks Best Regards Pier Re: iw611/iw612 and LE audio Thanks Ricardo, and sorry I didn't get your response before just sending mine. Can you please follow up with answers to my questions, preferably without any recitations of the documents. Apologies in advance for my inability to understand the docs as written. Re: iw611/iw612 and LE audio For context, there are other ambiguities about IW611 support for LC3, and the Auracast stack that requires it, in NXP docs: RN00104: Section 3.2.2 Bluetooth LE (Pier's reference) IW611 data sheet Section 1.3: Bluetooth Key Features lists Isochronous channels (ISOC) supporting LE Audio and Auracast™ Broadcast Audio but Section 4.2: Bluetooth Low Energy (LE) features lists Bluetooth LE isochronous channels with a footnote [6] that says: Bluetooth LE audio supported with external host running Low Complexity Communication codec (LC3) through HCI interface. There is no other mention of LC3 in the document, despite the fact that LC3 is a requirement for Auracast (as documented here and here). So, I'll reverberate Pier's question from the perspective of a developer trying to implement Auracast on i.MX8mp-based platform: Does the IW611 support LC3 in chipset hardware, or would implementing Auracast on i.MX8mp/IW611 require implementing the LC3 algorithm ourselves? If only the latter is true, can you provide any suggestion or reference implementations for doing this on the i.MX8mp's M7 co-processor? (In this case, assuming that this is what was implied in 2.2 above by external host running LC3 through HCI) Thanks in advance for your clarification and guidance! Re: iw611/iw612 and LE audio Hello Pier, Hope you are doing well. You can check on the Datasheet that Bluetooth LE audio supported with external host running Low Complexity Communication codec (LC3) through HCI interface. Hope this helps. Best Regards, Ricardo

uboot show BootOrder not defined after Kernel size changed from 30M to 50M U-Boot 2022.04 Kernel:5.15.71 I want to implement boot animation in the kernel. 100 pictures are linked in the kernel, resulting in the kernel changing from 30M to 50M. When booting, it was found that the uboot was stuck, indicating that the uboot could not be found No EFI system partition BootOrder not defined EFI boot manager: Cannot load any image switch to partitions #0, OK mmc2(part 0) is current device Scanning mmc 2:1... 62250 bytes read in 2 ms (29.7 MiB/s) BootOrder not defined EFI boot manager: Cannot load any image Re: uboot show BootOrder not defined after Kernel size changed from 30M to 50M Hello, In this case you will have to change the address in uboot and the cma memory. Regards

iw611/iw612 および LE オーディオ NXPサポートの皆様へ iw611/iw612 リリースノート for Linux (RN00104) に準拠 ファームウェアはBluetooth LEオーディオをサポートしています これはLC3コーデックもサポートされているということですか? ありがとうございます よろしくお願いいたします。 埠頭