MPC5744 etimer capture fail

[jefferson_ll]

Hi NXP,

I'm using etimer capture with MPC5744p chip.

I want to implement etimer capture by port A0 and get data and enter interrupt ISR.

When CFWM=0 after etimer capture done, it can enter into interrupt IRQ.

But CFWM=1 or CFWM=2 after etimer capture done, it can't enter into interrupt IRQ.

In this time the C2FCNT and C1FCNT always 0 that means the capture FIFO is not working ???

I just want use etimer and 1 capture pin to detect frequency.

Does following setting correct??
Please Help me thanks.

The following setting as bellow:

ETIMER_0.ENBL.R = 0x0; // disable Timer0 channels

ETIMER_0.CH[0].CTRL1.R = 0x3801; // Counts only rising edge of the MC_CLK (100MHz in RUN0),
// divide by 1, count up, count repeatedly, rollover
ETIMER_0.CH[0].CTRL1.B.SECSRC = 0;

ETIMER_0.CH[0].COMP1.R = 0xFFFF;
ETIMER_0.CH[0].CCCTRL.R = (0x0264) ; // compare on COMP1 when counting up, COMP2 when counting down
// CAPT2 on falling edge, CAPT1 on rising edge, 2 entries
// free-running mode

ETIMER_0.CH[0].CCCTRL.B.ONESHOT = 1;

ETIMER_0.CH[0].CCCTRL.B.CFWM = 1; //capture flag set as soon as more than 3 values will be in FIFOs
//CFWM=1: 2 capture enter IRQ, CFWM=0: 1 capture enter IRQ

ETIMER_0.CH[0].CTRL3.R = 0; //1:halt channel during debug mode, 0:Continue with normal operation during debug mode. (default)

ETIMER_0.CH[0].CTRL3.B.ROC = 0x03;

//interrupt
ETIMER_0.CH[0].INTDMA.B.ICF1IE = 1;
ETIMER_0.CH[0].INTDMA.B.ICF2IE = 1;
INTC_0.PSR[611].R = 0x8003; //priority setting 611 is INT vector index

//---clear interrupt flag
ETIMER_0.CH[0].STS.R=0xFFC0;

//=====pad setting
SIUL2.MSCR[0].B.IBE = 1; /* PA1: Enable pad for input - eTimer0 ch1 */
// SIUL2.MSCR[0].B.HYS = 1;
SIUL2.IMCR[59].B.SSS = 2; /* eTimer0 ch1: connected to pad PA1 */

ETIMER_0.ENBL.R = 0x0001; // Enable Timer0 channel 0

ETIMER_0.CH[0].CCCTRL.R |= 1; // starts the input capture process

[PetrS · Accepted solution]

Hi Jeff,

The issue, you have, is because the ONESHOT mode is selected. In this case after ARM is set single capture is performed, then no further captures will be performed until the ARM bit is set again.

Some time ago I posted frequency measurement example in the Community, you can refer to it; see

https://community.nxp.com/docs/DOC-104285

https://community.nxp.com/docs/DOC-330571

BR, Petr

[jefferson_ll]

Hi Petr,

Thanks for your description about ONESHOT and ARM bit.

I have modified the register setting the ONESHOT bit to 0 as free run mode and CFWM bit to 1.

In this case set ARM bit to 1, the rising and falling interrupt could be triggered after two times capture repeatedly.

Another question needs your help.

When the ARM bit to 1 the capture function works continuously when external signal always imports.

After some times capture the ARM bit set to 0 the capture function stopped.

There are no any rising and falling interrupt be triggered.

But I want to clear CAPT1 and CAPT2 before ARM bit to 1 again.

How do I clear CAPT1 and CAPT2 ?

[PetrS]

Hi Jeff,

you will clear the capture FIFO by reading the CAPT1/CAPT2 registers.
CTRL3[CnFCNT] bits reflect number of words in CAPTn FIFO, so can be used to know how many times the CATPn should be read.

BR, Petr

[tanmayeesapre]

Hi Petr,

I converted the attached example for MPC5643L board. The code gets stuck at - 

while(!(0x0080 & ETIMER_0.CHANNEL[1].STS.R)){} // wait for channel 1's capture2 flag
while(!(0x0080 & ETIMER_0.CHANNEL[0].STS.R)){}

I am trying to get a 32-bit counter going and need to read the values of CAPT1 and CAPT2 for it when the ICF2 flag is set. My code is getting stuck though and the flag never gets set.

Any ideas what might be going on?

Thanks,

Tanmayee