MPC5xxx知识库

讨论

******************************************************************************** * Detailed Description: * Initializes eQADC module for differnential single scan mode (with choosen GAIN * factor), converts specified command queue and displays results into terminal * window when EOQ is reached. * Differential analog input DAN0+:DAN0- needs to be connect externally between * pins ANA_0 and ANA_1 to see some valid numbers. * EVB potentiomenters can be used for the purpose. * As differential mode has been used, eQADC does not required to be calibrated. * * ------------------------------------------------------------------------------ * Test HW: XPC567XKIT516 - MPC5674ADAT516 Rev.C, MPC567XEVBFXMB Rev.B * MCU: PPC5674FMVYA264 * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * Fsys: 264/200/150/60 MHz * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Target: RAM, internal_FLASH * EVB connection: Potentiometers --> ADC inputs * USER_DEV_RV2(J4-7) --> ANA_0 (J18-3) DAN0+ * USER_DEV_RV3(J4-8) --> ANA_1 (J18-4) DAN0- * * Buttons --> ADC triggers * USER_DEV_1D(J4-2) --> TPU_A0 (J22-1) ********************************************************************************

******************************************************************************** * Detailed Description: * Initializes eQADC module, performs calibration and converts channel 145 * (bandgap voltage chosen as a source for the channel) and displays it into * terminal window. No external connection required excluding terminal via eSCI. * * ------------------------------------------------------------------------------ * Test HW: MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU: PPC5777CMM03 2N45H CTZZS1521A * Fsys: PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * ********************************************************************************

* Owner: b21190(Vlna Peter) * Version: 1.6 * Date: Nov-11-2015 * Classification: General Business Information * Brief: Example contains startup with PLL0 200MHz as system clock * ADC self-test demonstration ******************************************************************************** * Test HW: MPC57xx * Maskset: 1N83M (cut 2.0B) * Target : internal_FLASH * Fsys: 200MHz PLL0 as system clock ******************************************************************************** Revision History: 1.0 Oct-19-2015 b21190(Vlna Peter) Initial Version 1.1 Nov-11-2015 b21190(Vlna Peter) Added PPL0 200MHz as system clock 1.2 Dec-02-2015 b21190(Vlna Peter) Added Flash controller init 1.3 Dec-02-2015 b21190(Vlna Peter) Fixed system clock init 1.4 Feb-07-2017 b21190(Vlna Peter) SWT0 and SWT1 disabled in startup 1.5 May-31-2017 b21190(Vlna Peter) Fixed comments in AC6 (CLKOUT) 1.6 Jul-10-2018 nxa13250(Vlna Peter) Added ADC self-tests *******************************************************************************/

******************************************************************************** * Detailed Description: * * Configures the MCANs to transmit and receive a CAN FD message with or without * bit rate switching for data phase. This is defined by BRS macro. * Baudrate during arbitration phase is set to 500kbps, during data phase 1Mpbs * because of PHY used on the EVB. * * In this config, MCAN_0 transmits a message. MCAN_1 receives the message. * * MCAN_0 sends message each 1sec. This interval is generated by PIT. * Single TX buffer is used to send n bytes. The message ID is changed for each * transmission. Two standard and 2 extended IDs are sent. * * MCAN_1 is configured to receive a message, ISR is used to read new message. * There are 2 standard and 2 extended ID filter tables defined. Classic filter * configuration is set, means filter ID & mask. * Messages with matched standard ID are received into RXFIFO_0, messages with matched * extended ID then stored in RXFIFO_1. * * EVB connection: * * J37 and J38 to position 2-3 to connect MCAN1 TX/RX to transceiver * * CAN0-CANH on P15-1 to CAN1-CANH on P14-1 * CAN0-CANL on P15-2 to CAN1-CANL on P14-2 * * * ------------------------------------------------------------------------------ * Test HW: MPC5777C-512DS Rev.D + MPC57xx MOTHER BOARD Rev.C * MCU: SPC5777CCMM03 3N45H * Fsys: PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * use USB connector (J21) on minimodule * * EVB connection: ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) * ETPUA31 (PortP P23-14) --> USER_LED_2 (P7-2) * ********************************************************************************

* Owner: b21190(Vlna Peter) * Version: 1.0 * Date: May-09-2018 * Classification: General Business Information * Brief: BIST demonstration * ******************************************************************************** * Test HW: MPC57xx * Maskset: 3N23A * Target : internal_FLASH * Fsys: 200 MHz PLL with 40 MHz crystal reference * ******************************************************************************** Revision History: 1.0 Oct-22-2014 b21190(Vlna Peter) Initial Version 1.1 Mar-19-2015 b21190(Vlna Peter) Added ADC_0 driver 1.2 Mar-19-2015 b21190(Vlna Peter) Added STCU self-test for core1 *******************************************************************************/

******************************************************************************** * Owner: b21190(Vlna Peter) * Version: 1.0 * Date: May-09-2018 * Classification: General Business Information * Brief: BIST demonstration ******************************************************************************** * Test HW: MPC57xx * Maskset: 3N23A * Target : internal_FLASH * Fsys: 200 MHz PLL with 40 MHz crystal reference ******************************************************************************** Revision History: 1.0 Oct-22-2014 b21190(Vlna Peter) Initial Version 1.1 Sep-25-2018 b21190(Vlna Peter) STCU2 BIST Multicore *******************************************************************************/

******************************************************************************** * Detailed Description: * Purpose of the example is to show how to generate Multi-bit ECC error in * local DMEM memory. * ECC fault is generated with using of core register DMEMCTL0. If error * injection is enabled (DMEMCTL0[DPEIE]=1), subsequent write to DMEM creates * 2b ECC error in DMEM array and following read of this area causes bus error * (IVOR1 exception) or FCCU_Alarm_Interrupt. * Both function calls MEMU handler. * Example does not show any handling as it is application specific. * The example displays notices in the terminal window (connector J19 on * MPC57xx_Motherboard)(19200-8-no parity-1 stop bit-no flow control on eSCI_A). * No other external connection is required. * ------------------------------------------------------------------------------ * Test HW: MPC57xx_Motherboard + MPC5744P-144DC * MCU: PPC5744PFMLQ8,0N15P,QQAA1515N, Rev2.1B * Fsys: 200 MHz PLL with 40 MHz crystal reference * Debugger: Lauterbach Trace32 * Target: internal_FLASH, RAM * Terminal: 19200-8-no parity-1 stop bit-no flow control * EVB connection: default ********************************************************************************

* Detailed Description: * Test HW: MPC57xx + S32R274RRUEVB * Maskset: 1N58R * Target : internal_FLASH * Fsys: 240 MHz PLL with 40 MHz crystal reference for z7 and 120MHz for z4 * This example provides user with a configuration of clocks for all cores and all peripherals. * Peripherals and cores are supplied by maximum available clock configuration from PLLDIG block. ******************************************************************************** Revision History: 1.0 Apr-02-2019 b21190(Vlna Peter) Initial Version *******************************************************************************/

******************************************************************************** * Detailed Description: * Application performs basic initialization, initializes interrupts, blinking * one LED by Core0, second by Core1 (by interrupt), initializes and display * notice via UART terminal and then terminal ECHO. * An example re-configures default clock setting to first and then second * configuration to shows necessary steps to perform this transtition. * * ------------------------------------------------------------------------------ * Test HW: MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU: PPC5777CMM03 2N45H CTZZS1521A * Fsys: PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) * ETPUA31 (PortP P23-14) --> USER_LED_2 (P7-2) ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, initializes interrupts and NMI for * WKPCFG pin (GPIO213). * User needs to connect ETPUC9 pin to user switch and general purpose output * ETPUA30 to user LED 1: * ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) * WKPCFG (PortC P10-4) --> USER_SWITCHES (P6-4) * Jumper J523 position 1-2 needs to be OPEN! * * If rising edge is detected (i.e. button is pressed), machine check exception * is triggered and LED1 on is toggled. * * ------------------------------------------------------------------------------ * Test HW: MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU: PPC5777CMM03 2N45H CTZZS1521A * Fsys: PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) * WKPCFG (PortC P10-4) --> USER_SWITCHES (P6-4) * Jumper J523 position 1-2 needs to be OPEN! ******************************************************************************** Revision History: Ver Date Author Description of Changes 0.0 May-22-2019 David Tosenovjan Initial version *******************************************************************************/

******************************************************************************** * Detailed Description: * Example of core watchdog implementation on Cobra 55. It executes on core 0 * All the functions are in the file "watchdog.c" *WatchDogCreate(delay, FirstTimeout, SecondTimeout) -> create/configure the wathdog timer *WatchDogStart() -> start the watchdog timer *WatchDogService() -> acknowledge the watchdog timer * ------------------------------------------------------------------------------ * Test HW: MPC5777C-416DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU: PPC5777CMM03 2N45H CTZZS1521A * Fsys: PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH * ********************************************************************************

/* * Queue.h * * Created on: May 28, 2015 * Author: ShuLizhong */ #ifndef QUEUE_H_ #define QUEUE_H_ #ifdef _cplusplus extern "C" { #endif /*If you want to change the queue type(QUEUE_TYPE) and queue max size(QUEUE_MAX_SIZE), you should define it at front of include queue.h file. eg: ******in xxx.h file***** code**** #define QUEUE_TYPE Other type(unsigned int) #define QUEUE_MAX_SIZE Other size(100) #include "qeue.h" code**** */ #ifndef QUEUE_TYPE #define QUEUE_TYPE unsigned char #endif #ifndef QUEUE_MAX_SIZE #define QUEUE_MAX_SIZE 100 #endif #define bool unsigned int typedef enum { OK, FULL, EMPTY }QUEUE_STATUS; typedef struct { unsigned int tail; unsigned int head; unsigned int size; unsigned int length; QUEUE_TYPE data[QUEUE_MAX_SIZE]; }Queue_tag,*pQueue_tag; __inline void InitQueue(pQueue_tag q) { q->tail = q->head = q->size = 0; q->length = QUEUE_MAX_SIZE; } __inline QUEUE_STATUS EnQueue(pQueue_tag q,QUEUE_TYPE data) { if(q->size++ == QUEUE_MAX_SIZE) return FULL; q->data[q->tail] = data; q->tail = (q->tail+1) % QUEUE_MAX_SIZE; return OK; } __inline QUEUE_STATUS DeQueue(pQueue_tag q, QUEUE_TYPE *data) { if(q->size-- == 0) return EMPTY; *data = q->data[q->head]; q->head = (q->head+1) % QUEUE_MAX_SIZE; return OK; } __inline bool IsQueueEmpty(pQueue_tag q) { return q->size == 0; } __inline bool IsQueueFull(pQueue_tag q) { return q->size == QUEUE_MAX_SIZE; } __inline unsigned int GetQueueSize(pQueue_tag q) { return q->size; } __inline unsigned int GetQueueLength(pQueue_tag q) { return q->length; } /*__inline unsigned int DeMoreBytesFromQueue(pQueue_tag q,QUEUE_TYPE *data,unsigned int len) { unsigned int i = 0; len++; return 0; }*/ #ifdef _cplusplus } #endif #endif /* QUEUE_H_ */