* Detailed Description:
* Test HW: MPC57xx + S32R274RRUEVB
* Maskset: 1N58R
* Target : internal_FLASH
* Fsys: 240 MHz PLL with 40 MHz crystal reference for z7 and 120MHz for z4
* This example provides user with a configuration of clocks for all cores and all peripherals.
* Peripherals and cores are supplied by maximum available clock configuration from PLLDIG block.
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Revision History:
1.0 Apr-02-2019 b21190(Vlna Peter) Initial Version
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